EP2605132A1 - Procédé de gestion de la mémoire d'un ordinateur avec au moins une machine virtuelle - Google Patents

Procédé de gestion de la mémoire d'un ordinateur avec au moins une machine virtuelle Download PDF

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Publication number
EP2605132A1
EP2605132A1 EP11193314.9A EP11193314A EP2605132A1 EP 2605132 A1 EP2605132 A1 EP 2605132A1 EP 11193314 A EP11193314 A EP 11193314A EP 2605132 A1 EP2605132 A1 EP 2605132A1
Authority
EP
European Patent Office
Prior art keywords
operating system
memory
vmm
virtualization
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP11193314.9A
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German (de)
English (en)
Other versions
EP2605132B1 (fr
Inventor
Otto Niesser
Halil Caglar Ünver
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
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Siemens AG
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Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to EP11193314.9A priority Critical patent/EP2605132B1/fr
Publication of EP2605132A1 publication Critical patent/EP2605132A1/fr
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Publication of EP2605132B1 publication Critical patent/EP2605132B1/fr
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors

Definitions

  • the invention relates to a method for managing memory of a computer having at least one virtual machine according to the preamble of patent claim 1.
  • Microprocessor-controlled devices generally: computers
  • memory in which data and programs can be stored and which is accessed by at least one microprocessor.
  • the memory units generally individual bytes, are assigned unique physical addresses, by means of which the access takes place.
  • other types of memory can be managed by a computer, in particular mass storage in the form of hard disks, memory sticks, optical storage (CD-ROM, DVD, etc.) and even memory in data networks ("cloud memory").
  • An entry in the "page table”, ie the page table, is addressed with the first-mentioned share, the page entry resulting from this table entry, or its base address in which the desired memory cell is located.
  • the relevant memory cell is addressed or found by the offset portion of the desired address.
  • a corresponding multi-stage method is used, wherein for addressing a memory cell first the base register ("CR3") of the memory directory used (page directory) is specified, with a corresponding portion of the address an entry in this page Directory defined. This portion results in an associated page table, with a corresponding different portion of the desired address resulting in an entry of that page table. This entry in turn specifies the base address of the desired memory page, so that a further portion of the desired address, namely an offset value, finally leads to the correct memory cell.
  • CR3 base register
  • page directory page directory
  • This entry specifies the base address of the desired memory page, so that a further portion of the desired address, namely an offset value, finally leads to the correct memory cell.
  • the following is an arrangement to be considered, which corresponds to a personal computer or a similar data processing device.
  • a number of virtual machines are set up, which are managed by at least one virtualization control controller.
  • an operating system is installed, which uses the previously described "paging" for memory management. It must be ensured that the available resources, in particular the main memory, are reliably divided between the individual virtual machines is to avoid unwanted interactions.
  • the addressable memory including hardware inserted there (memory mapped devices), should be considered here.
  • the virtualization control (hypervisor, virtual machine monitor - VMM) are in the art for managing the "common” memory "shadow paging" or - on more modern processors - the largely corresponding procedures "Extended Page Table” (EPT, Fa Intel) and Nested Page Tables (NPT, AMD).
  • EPT Extended Page Table
  • NPT Nested Page Table
  • the page directory namely the shadow page tables
  • the shadow page directory is not expanded, and the access is emulated (Case 2), or the page fault error (Page Fault ) is passed to the "virtualized" operating system (case 3).
  • the virtualization controller must delete the previously established "shadow page directory” again or pretend it otherwise, so that the process begins again.
  • EPT or NPT also causes the subsequent connection of a second, extended page directory.
  • the virtual addresses used by the "virtualized" operating system are converted to guest physical addresses by means of its local page directory. So far, the process does not yet differ from the application in which the operating system runs directly on the machine without virtualization.
  • RTOS operating system
  • RTOS virtualization control system
  • the "real-time performance” is deteriorated, which primarily affects the so-called "latency”.
  • skips in the virtualization control depend on whether there is already an entry in the page tables (then no skip), or if the memory cell is addressed for the first time (then skip). In other words, the execution speed of the real-time operating system is no longer deterministic.
  • an operating system in particular a real-time operating system, which runs in a virtual machine, after its initialization, but before the execution of program portions of the user z. B. by means of a so-called.
  • VMM virtualization controller
  • the virtualization controller checks this memory allocation for admissibility and prevents any further changes to this assignment from this point in time.
  • a prerequisite for this is a (or limited choice) largely static memory allocation (s) of at least the (real-time) operating system. This means in particular that the memory allocation of the virtualization control is made known before program portions of a user come to expiration, and that This memory allocation is then no longer or at least not changed by other operating systems or virtual machines.
  • a method for managing memory of a computer with at least one virtual machine and with a virtualization controller wherein an operating system runs in the virtual machine, and wherein the virtualization controller uses extended page tables for checking and implementing the memory accesses to host physical addresses ,
  • the operating system transmits a default for the extended page tables to the virtualization controller, wherein the extended page tables are configured by the virtualization controller according to the transmitted pre-assignment.
  • the pre-assigned extended page table is advantageously used as a shadow page table (SPD1, PT1, SPD2, PT2, ...) used to translate the logical addresses to the host physical addresses.
  • the known "shadow paging" method essentially does not need to be changed, but can be used according to the invention with the pre-assigned extended page tables.
  • the memory access operating system advantageously uses local memory tables to convert logical addresses to guest physical addresses. This offers the advantage that for the use of the method according to the invention in EPT / NPT memory management by the operating system and the applications no changes in the process during the operation of the application are "seen", so that no changes to the operating system operating and running therein Applications must be provided.
  • the virtualization control checks the transmitted pre-assignment with regard to its admissibility. In this case, it can be ensured, for example, that memory-addressed hardware ("memory-mapped devices") is made accessible only to a specific virtual machine or to a specific operating system. Also other protection mechanisms (“memory protection”) can be realized with it.
  • the pre-assignment is determined by the operating system, in particular by a real-time operating system, and transmitted to the virtualization controller, so that the "preferred" real-time operating system can specify, for example, a particularly advantageous memory allocation for an application software for execution under its control.
  • a separate virtual machine for managing resources can also define the default setting and transmit it to the virtualization controller.
  • the transmission of the pre-assignment takes place before the start of running under control of the operating system, so that on the one hand no "time-consuming" configurations must be made at runtime of the application in question, and on the other hand any malicious software within the application, the memory allocation no longer adversely affect can.
  • the specified method can be used particularly advantageously if the operating system used is a real-time operating system.
  • the operating system used is a real-time operating system.
  • it is particularly important to pay attention to low latency and speed of execution.
  • This applies in particular to the cases in which an application designed as a software automation control is executed under the control of the real-time operating system.
  • the pre-assignment is advantageously optimized to the needs of the application, in particular to the needs of the software control designed as a software.
  • FIG. 1 an inventive memory access method is shown using the example of the known "shadow paging".
  • an operating system OS and an application running under the control of the operating system OS use memory tables PD, PT (page directory, page table) in the same way as if the operating system OS was running "natively" directly on a hardware.
  • the base register CR3 of the page table PD is virtualized in a virtual machine because of the operation of the OS. This means that for the conversion of the logical memory accesses into physical memory accesses, in fact not the “virtualized CR3" is used, but the "real CR3", which is under the control of a virtualization control VMM (Virtual Machine Monitor).
  • VMM Virtual Machine Monitor
  • the "real CR3" is selected using the "virtualized CR3". This means that a multiplicity of extended page tables SPD1 / PT1, SPD2 / PT2,... Can be present on the virtualization level, and after a change of the virtualized base register the real base register can also be changed. Such a change of the real base register "real CR3" can thus be made as soon as the operating system OS changes the "virtualized base register” by causing an exit (VM exit) in the virtualization control in such a case.
  • VM exit exit
  • entries of the page directory PD refer to different page tables PT. This applies to the exemplary assumed addresses a, b.
  • the address c can, for example, be located in a particularly large memory area which is addressed directly via the page directory PD.
  • the operating system OS addresses the page tables PD, PT, but for those actually executed Memory accesses the background "shadow tables" SPD1 / PT1 or (depending on the modified base register value) one of the other extended page tables SPD2 / PT2, SPD3 / PT3 etc.
  • the extended page tables SPD1 / PT1 and the other " Sets were "pre-assigned to extended page tables after a system startup of the OS or at least before the start of an application (not shown) and were locked against further write accesses. Because the extended page tables SPD1 / PT1 are completely pre-populated, no page faults can occur at the level of the virtualization control, unless these page faults already occurred when accessing the local page tables PD / PT. However, these local page faults are on the one hand under complete control of the operating system OS, and on the other hand do not lead to an exit into the virtualization control VMM, such jumps being avoided according to the invention. Only emulated accesses will interact with the virtualization control at this point, which, however, can only be avoided with mechanisms not described here anyway.
  • the virtualization controller VMM When implementing the method according to the invention by means of "Schadow paging", the virtualization controller VMM must be informed in advance of each memory allocation used in the system by hypercall.
  • the respective memory allocation is identified here by the base address CR3 of the corresponding page directory PD, and deposited with the virtualization controller VMM.
  • FIG. 2 becomes one to the FIG. 1 similar configuration outlined so that in the following only the differences will be discussed.
  • a memory access method according to the invention modified in accordance with the EPT or NPT method.
  • EPT Extend Page Directory
  • Extended Page Table Extended Page Table
  • the virtualization controller VMM is also informed of the desired memory allocation by means of a hypercall (VM exit).
  • VM exit By means of the mechanisms known to the known EPT / NPT methods, access by the operating system OS to physical addresses beyond this allocation is prevented. This happens without loss of performance.
  • the only allowed interaction with the Virtualization Control VMM (EPT / NPT Violation) occurs in cases where access needs to be emulated. However, errors that result in a "page fault" in the area of the operating system OS are intercepted there and do not lead to an exit into the virtualization control VMM.
  • the finished configured extended page tables SPD1, PT1, SPD2, PT2,... Or EPD / EPT can be transferred by the operating system OS to the virtualization controller VMM.
  • each memory area to be allocated is communicated individually by its own “Hypercall” the virtualization controller VMM. The procedure is then parameterized by a whole sequence of "hypercalls".
  • another, last "Hypercall” is necessary, which signals the virtualization controller VMM the end of the sequence and leads to a blocking of the configured memory allocations against further, subsequent changes.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
EP11193314.9A 2011-12-13 2011-12-13 Procédé de gestion de la mémoire d'un ordinateur avec au moins une machine virtuelle Active EP2605132B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP11193314.9A EP2605132B1 (fr) 2011-12-13 2011-12-13 Procédé de gestion de la mémoire d'un ordinateur avec au moins une machine virtuelle

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Application Number Priority Date Filing Date Title
EP11193314.9A EP2605132B1 (fr) 2011-12-13 2011-12-13 Procédé de gestion de la mémoire d'un ordinateur avec au moins une machine virtuelle

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EP2605132A1 true EP2605132A1 (fr) 2013-06-19
EP2605132B1 EP2605132B1 (fr) 2018-05-09

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1681630A1 (fr) * 2005-01-14 2006-07-19 Intel Corporation Virtualisation de mémoire physique dans un système de machine virtuel
US20110154104A1 (en) * 2009-12-23 2011-06-23 Swanson Robert C Controlling Memory Redundancy In A System

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1681630A1 (fr) * 2005-01-14 2006-07-19 Intel Corporation Virtualisation de mémoire physique dans un système de machine virtuel
US20110154104A1 (en) * 2009-12-23 2011-06-23 Swanson Robert C Controlling Memory Redundancy In A System

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