EP2593869A1

EP2593869A1 - Method and apparatus for checking a main memory of a processor

Info

Publication number: EP2593869A1
Application number: EP11728847.2A
Authority: EP
Inventors: Christian Hildner
Original assignee: Siemens AG
Current assignee: Siemens AG
Priority date: 2010-07-16
Filing date: 2011-07-01
Publication date: 2013-05-22
Also published as: WO2012007295A1; RU2013106793A; BR112013001166A2; DE102010027287A1; US20130124925A1; CN103119564A

Abstract

The invention relates to a method and an apparatus for checking a main memory (3) of a processor (1), comprising a cache memory (2) and a plurality of registers (R). According to the invention, before carrying out a memory test (T), a boot-up sequence which may be running at that time is interrupted, temporary data required for the memory test (T) is written to at least one register (6) and is held there, and the access from the cache memory (2) to the main memory (3) is activated. In this case, the access to the main memory (3) is carried out via the cache memory (2, 5) such that bit patterns (BM) are written to the cache memory (2, 5) and, via this, to the main memory (3), and are read out again from the main memory (3) via the cache memory (2) and are compared, wherein that area of the main memory (3) to be tested is larger than the size of the cache memory (2), and the boot-up sequence which was possibly interrupted before carrying out the memory test (T) is restarted or continued once the memory test (T) has been completed.

Description

description

Method and apparatus for testing a main memory of a processor

The invention relates to a method for testing a main memory of a processor. Furthermore, the dung ^¬ OF INVENTION relates to an apparatus for testing a main memory of a processor.

In modern computer systems, it is common that the processor has the largest possible and cost-effective main memory. For the execution of programs by the processor while various memory accesses, such as loading / reading, storing and / or writing data, operands and / or commands are required.

Due to safety and / or operating requirements, it is common practice to check parts of the main memory from time to time. Due to the size of the main memory and relatively long access times of the processor to the main memory a memory test takes a lot of time and contradicts ^{¬ in} example the demand for short run-up times of the processor.

The invention is therefore the object of a method for testing a main memory of a processor to accel ^¬ nigen. Furthermore, it is an object of the invention to simplify a device for checking the main memory.

The object with regard to the method according to the invention is achieved by the features specified in claim 1. With regard to the device, the object is achieved by the features specified in claim 11.

Advantageous embodiments of the invention are the subject of the dependent claims. In the method for testing a main memory of a Prozes ^¬ sors, said main memory having a plurality of memory cells, prior to performing a memory test an optionally currently running up sequence is interrupted and temporary required for the memory test data such. As program variables, written in at least one register or held there. In addition, the access from the cache memory is activated on the main memory, the access to the memory cells of the main memory via a cache memory during the memory test such erfindungsge ^¬ Mäss is stated that bit pattern to the cache memory and transfers these to the main memory written and read from the main memory via the cache memory and compared again, wherein the area of the main memory to be tested is greater than the size of the cache memory. ^Subsequently , the ^{startup sequence} , which may have been interrupted before the memory test is executed, is restarted or continued. After the memory test has ended, the cache memory is then disconnected from the main memory and the run-up sequence interrupted before the memory test is ^{executed is restarted} or continued. In addition, the bit patterns read out from the main memory are compared with generated desired bit patterns. In particular, the memory test is executed before a start of the operating system, wherein the currently running startup sequence is a pre-program or an initialization program of a computer program of the processor.

Such a method using at least one fast cache memory with much shorter access times allows a secure and compared to the prior art much faster test procedure for the main memory. In this case, the test of the main memory can be carried out stepwise and / or block by block. The processor is preferably designed as a microprocessor. Microprocessors are processors in which all components are arranged on a microchip. Advantageously, a pattern of zeroes and / or ones becomes the particular word by word, cells ^¬ wise and / or block-wise testing of the main memory as a bit pattern used. In this case, for example, the main memory in equal, independent areas, z. As words, blocks, and thus wordwise or blockwise, divided, which can be read or written differently in time. For example, sequential memory words are zyk ^¬ cally sequential read the following memory banks or -blocke ge ^¬ written or from these in. By testing consecutive memory banks, the access time can be shortened because the width of the data bus is limited to

Main memory is larger than the word width of the processor.

For a permanently safe operation of the main memory, one or more memory cells of the main memory are tested several times in a cell-by-cell test. Similarly, ^¬ the tested several times in a block-wise test one or more Speicherblö ^¬ bridge. Each memory cell is a ^¬ be known value and the complement (inversion) of the value written sawn, so that each bit times must hold the value "0" again to the value "1" and a ^¬.

In a simple embodiment, one or more memory cells and / or blocks of the main memory are cyclically tested. Alternatively or additionally, the test can be carried out event-controlled. For example, the Spei ^¬ chertest is led from ^¬ the boot loader before starting the operating system. In addition, activated automatically and at least one or more times ^¬ executed pursuant to a faulty execution of the memory test by the processor. Conveniently, a test of address and / or data ^¬ lines is performed prior to performing a memory test of the main memory. In this case, the tests of address and / or data lines are executed via the direct access of the processor to the main memory and not via the cache memory. The test of the address and / or data lines will thus be carried out in a conventional manner by the random access before the memory test. By means of the Ausfüh ^¬ tion of the test of the address and / or data lines before a memory test in particular possible manufacturing errors, eg. B. line interruptions, short circuits, identi ^¬ fices. The memory test to identify a memory chip failure is particular only be executed if at ^¬ de previous tests, that the test of the address lines and the test of the data lines, correctly, that is error free, run through.

To avoid data loss, temporary program data or variables are buffered in a register during a memory test, in particular after the test of the address and / or data lines and before the memory test. After the memory test, these program data or variables can be read out again and written to the cache memory and / or main memory. Specifically, when the number of registers for temporarily storing the temporary data is insufficient, the startup sequence ^¬ restarts ge and thus repeated to prepare the temporary data again ^¬. In the event that temporary data discarded during the memory test is no longer needed, the boot sequence will continue.

For analysis of the storage tests carried out the signal resulting from the comparison of the bit patterns result is written in a Regis ^¬ ter of the processor.

In an embodiment of the invention, a plurality of cache memories are used, wherein one of the cache memories for storing program code (also program or instruction Called cache) and another cache memory for storing current, ie currently used, data and / or variables, such as program variables and address data (also called data cache) is used. The cache memory storing the program code serves to accelerate the access to the program code. The data cache, ie the cache memory storing the temporary data, serves in particular for storing and accelerating accesses to the main memory.

Preferably, the program code and in particular the program code containing the memory test is stored in a read-only memory (ROM).

In a development of the invention, the program code containing the memory test is implemented in the main program. This prevents a subroutine call that would cause a healthy stack memory. Alternatively, the memory test may be implemented as a subroutine. In this case, the program is continued in subprogram calls; a return to the main program is prevented because of possibly lost program variables from the cache memory. With regard to the apparatus for testing the main memory, a cache memory according to the invention between the main memory and the processor arranged such that, during egg ^¬ nes memory testing access to the memory cells of the main memory via the cache memory is such executable that predetermined bit pattern to the cache Memory, in particular in its memory cells and via this into the main memory, in particular in its memory cells writable and read from these via the cache memory again, the processor compares the read out of the main memory nen bit pattern with desired bit patterns, otherwise the cache memory is separated from the main memory and for the recording of temporary data, in particular program data, is available, wherein the size of the cache memory is smaller than the area of the main memory to be tested.

The use of a cache memory as a cache with fast access times allows acceleration of memory tests of the main memory. Preferably, the cache memory can be integrated on the processor chip itself.

Further advantages, features and details of the invention are described below with reference to embodiments with reference to drawings. Show

1 schematically shows a block diagram of an execution ^¬ of a device for testing a Hauptspei- Chers, and

2 schematically shows a flow chart of a memory test for the main memory.

Corresponding parts are provided in all figures with the same reference numerals.

Figure 1 shows schematically a block diagram of an embodiment of an apparatus for testing a main memory 3 of a processor 1. The processor 1 may be a microprocessor whose components are arranged on a micro-chip (not shown in detail).

Between the processor 1 and the main memory 3 is a cache memory 2 as a buffer or buffer memory is arranged. The processor 1 is connected in a conventional manner via data, address, error and control lines 4 to the cache memory 2 and this to the main memory 3.

In this case, the processor 1 accesses for checking the main memory 3 with the interposition of the cache memory 2 to the main memory 3 to ^¬. The access to the main memory 3 via the cache memory 2 takes place only during the memory test, other if necessary, the cache memory 2 is separated from the main memory 3 (indicated by the dashed line 4).

The main memory 3 is a conventional large working memory rather of the processor 1. The access to the main memory 3, for example via 8-bit and / or 16-bit address channels or lines. The main memory 3 comprises groups of memory elements which are combined to form a memory cell 3.1 to 3.z (= smallest addressable unit). Each memory cell 3.1 to 3.z comprises 8 bits (= 1 byte). Several memory cells 3.1 to 3.z, z. B. 4 or 8 memory cells 3.1 to 3.z can be combined to form a 32-bit or 64-bit memory word, a memory block, a memory page and / or a memory bank. As a result, a simple addressing of in particular successive, equal and independent areas of the main memory 3 is possible.

The cache memory 2 is a fast buffer memory arranged between register memories R of the processor 1 and the main memory 3. In the illustrated embodiment, the cache memory 2 is outside of the processor ^¬ 1 and thus not arranged on the processor chip. Alternatively, the cache memory 2 may also be arranged on the processor chip (not shown).

The cache memory 2 has a comparison with the main memory 3 smaller storage capacity, for example in the kilobyte or ^{megabyte ¬} range, z. B. 1 MB, with shortest access times in the nanosecond range, whereas the storage capacity of the main memory 3 in the mega-, giga- or tetrabyte range, z. B. 512 MB, with low access times in the millisecond range. The cache memory 2 has, analogously to the main memory 3, a plurality of memory cells 2.1 to 2.n, which are combined or segmented according to specifications correspondingly in words, groups and / or blocks, which are independent of each other. represent areas. The cache memory 2 is used for storage of currently used data and / or variables, in particular special of dynamic program variables, such as address data. In addition, the device comprises at least one wide ^¬ ren cache memory 5 with a number of memory cells 5.1 to 5.m. The more cache memory 5 serves the spoke ^¬ tion of the program code. In this case, the cache memory 5 is a read memory 7, z. B. a ROM memory (ROM = read-only memory), downstream, in which the program code is stored ^¬ chert.

FIG. 2 schematically shows a flow chart of a memory test T for the main memory 3.

In general, the main memory 3 is regularly checked. Preferably, a memory test T is performed before the start of the loading ^¬ drive system. In contrast to conventional test methods, in the method according to the invention the processor 1 does not access the main memory 3 directly but via the cache memory 2. The access is executed by the processor 1 in such a way that at least one bit pattern BM is transferred to the cache memory 2 and via this is written to the main memory 3 and read out of this again. Subsequently, the re-read from the main memory 3 ^¬ BM bit pattern is compared with the generated target bit pattern. In the case of inequality of the two bit patterns, an error of the main memory 3 or a transmission error is inferred.

Conveniently, as a bit pattern BM is a pattern with zeros and / or ones in a predetermined length, z. 8-bit, 16-bit, 32-bit length. For example, bit data BM is used as the bit pattern. During the test, one or more of the memory cells 3.1 to 3.z of the main memory 3 are tested several times, in particular cyclically. In detail, upon activation of the memory test T and before the memory test T is carried out in a first step S1, optionally a test of address lines and / or data lines can be carried out in a conventional manner via a direct access and thus without an intermediate memory (shown in dashed lines). The optional test of address and / or Da ^¬ specific addresses are tenleitungen tested on generated bit patterns to shorts manufacturing defects, in particular line interruptions and / or to iden ^¬ ren. Only when the previously executed test of address and / or data lines has been executed without errors, the actual memory test T is started and executed.

In step S2, the program code for the memory test T, for example a program test with checking of writing and / or reading operations, is called. The program code is preferably called in the main program.

Prior to the access of the processor 1 to the cache memory 2 for testing the main memory 3, a currently running startup sequence is interrupted.

Optionally or additionally, in a step S2.1 temporary and not zutestende but erfor ^¬ derliche for the memory test T data such. For example, temporary program variables, data, are temporarily stored in one of the registers 6 and / or register memories R. The register R are as example ^¬ currently unused register of the processor 1. Alterna tively ^¬ the register memory can be R, and / or additional tabs 6 and disposed outside of the processor. 1

In a third step S3, access to the cache memory 2 for testing the main memory 3 is then activated. There- This can lead to invalid data, especially temporary program data.

In detail, the processor 1 is implemented in the test routine is activated, by means of which to test write and / or Le ^¬ seoperationen how commands, queries, not be executed directly to the main memory 3, but to the cache memory. 2 The test routine is, for example, in Ma ^¬ schin language (assembly language) or a higher programming language using an optimizing compiler written to hold temporary data in registers in place of the stack in the cache memory 2 or the main memory 3 and to store.

In step S4, the memory test T is then executed according to the implemented test routine. By means of the memory tests ^¬ T are defined accesses to the memory cells 2.1 to 2.n of the respective cache memory 2 in terms of type, fre- quency and / or circumferential and controlled. As a kind of

For example, access is defined and controlled by read or write operations. By way of example, the number of memory cells 3.1 to 3.m to be tested and / or memory blocks of the main memory 3 is specified as the scope.

In detail, one of the size of the test area of the main memory 3 to be written corresponding to ^¬ plurality of bit patterns BM in the cache memory 2 in a first loop. In this case, the cache memory 2 is smaller than the area of the main memory 3 to be tested, so that the cache memory 2 is overwritten with bit patterns BM during the memory test T and bit patterns BM are written into the area of the main memory 3 to be tested. In a second loop, the bit patterns BM of the region of the main memory 3 to be tested are then read out again via the cache memory 2 and compared with desired bit patterns. For example, block, word, and / or cells, bit ^¬ pattern BM in predetermined memory cells 2.1 to 2.n of the cache memory 2 and of these written into corresponding memory cells ^¬ 3.1 to 3.z of the main memory 3 from this via the Cache memory 2 again read and compared with target bit patterns. The result of the comparison is buffered, for example in a predetermined further register 6 and / or register memories R of the processor 1.

In step S5, the access to the Hauptspei ^¬ cher 3 via the cache memory 2 is deactivated after completion of the test routine for the memory test T then optional. In step S6, the stored result of the comparison of the bit pattern BM read out from the main memory 3 with the target bit patterns is checked. The result of the comparison has been written to the register 6 and / or one of the register R of the processor 1, so that this can be evaluated by an implementing in the processor 1 analysis routine.

In step S7, the data latched in step S3, and optionally in step S2.1 temporary data are then read again and the original startup sequence of the Prozes ^¬ sors 1 again started or initialized, that is, the broken before executing the memory test T-up sequence is started again, or optionally continued. The memory test T can be started several times, for example cyclically repeated or event-controlled. Insbeson ^¬ particular the memory test T is performed before the start of Betriebssys ^¬ tems. Also, further steps can be implemented.

The memory test T is implemented in particular as a program code or test routine in the main program of the processor 1. Alternatively, the program code of the memory test T can be used as be implemented. In this case, subsequent programs are only aufgeru ^¬ fen as a subroutine, since as a result of the memory test T by means of the cache memory ^¬ chers 2 temporary data, in particular address data in the cache memory 2 may have been lost. To enable a safe program flow, therefore, all other programs are called as a subroutine.

By means of the method according to the invention for testing the

Main memory 3 on the access to the cache memory 2, all memory cells 3.1 to 3.z of the main memory in ^¬ be tested individually. Through the use of cache memories 2, the memory test T is significantly accelerated.

Claims

claims

1. A method for testing a main memory (3) of a Pro ^¬ zessors (1) comprising a cache memory (2) and a plurality of registers (6) and / or memory register (R),

characterized in that prior to performing a memory test (T) is interrupted an optionally momen ^¬ tan running-up sequence for the memory test (T) required data temporary be written in at least one register (6) or held there and accessed from the cache memory ( 2) to the main memory (3) is activated, wherein the access to the main memory (3) via the cache memory (2) is carried out such that Bit ^¬ pattern (BM) in the cache memory (2) and via this written to the main memory (3) and read out from the main memory (3) via the cache memory (2) and compared, the area of the main memory (3) to be tested being greater than the size of the cache memory (2) and ge ^¬ optionally before executing the memory test (T) sub brochene up sequence after the end of the memory test (T) is restarted or continued.

2. The method according to claim 1,

characterized in that after the memory test (T) the access of the cache memory (2) to the main memory (3) is disconnected.

3. The method according to claim 1,

characterized in that in the case of an optional before the memory test (T) carried out tests of address lines and / or data lines, the memory test is started only after error-free testing of the address lines or data lines.

4. The method according to any one of the preceding claims, characterized in that a pattern with zeros and / or ones is used as the bit pattern (BM).

5. The method according to any one of the preceding claims, characterized in that by means of the memory test (T) one or more memory cells (3.1 to 3.z) of the Hauptspei ^¬ chers (3) are tested before starting the operating system.

6. The method according to any one of the preceding claims, characterized in that temporary, necessary for the Hochlaufse ^¬ quency data before the memory test (T) in a register (6) and stored during / after the memory test (T) again used / read.

7. The method according to any one of the preceding claims, characterized in that a resulting from the comparison of the bit pattern (BM) result in a register (6) of the processor (1) are written.

8. The method according to any one of the preceding claims, characterized in that a plurality of cache memories (2, 5) are used, wherein one of the cache memory (2) for

Storing temporary data, such as program variables, and another cache memory (5) for storing the program code.

9. The method according to any one of the preceding claims, characterized in that the program code in a read ^¬ memory (7) is deposited.

10. The method according to any one of the preceding claims, characterized in that the memory test (T) ausfüh ^¬ ing program code is implemented in the main program or in a Unterpro ^¬ gram without return option.

11. Device for checking a main memory (3) of a processor (1), comprising a cache memory (2) and several registers ^¬ (6),

characterized in that between the main memory (3) and the processor (1) at least one cache memory (2, 5) is arranged such that during the execution of a memory test (T) access to the main memory (3) via the cache memory (2, 5) is executable such that predeterminable bit pattern (BM) in the cache memory (2, 5 3) and readable from the main memory (3) again, the processor (1) comparing the bit pattern (BM) read from the main memory (3) with desired bit patterns, otherwise the approx ^¬ Memory (2) is separated from the main memory (3), wherein the size of the cache memory (2) is smaller than the area to be tested of the main memory (3).