EP2592800A1 - Routeur sur puce de réseaux - Google Patents

Routeur sur puce de réseaux Download PDF

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Publication number
EP2592800A1
EP2592800A1 EP11306458.8A EP11306458A EP2592800A1 EP 2592800 A1 EP2592800 A1 EP 2592800A1 EP 11306458 A EP11306458 A EP 11306458A EP 2592800 A1 EP2592800 A1 EP 2592800A1
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EP
European Patent Office
Prior art keywords
virtual network
output
router
virtual
request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
EP11306458.8A
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German (de)
English (en)
Inventor
Antonio-Marcello Coppola
Riccardo Locatelli
Esa Petri
Luca Fanucci
Sergio Saponara
Tony Bacchillone
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Grenoble 2 SAS
Original Assignee
STMicroelectronics Grenoble 2 SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
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Priority to EP11306458.8A priority Critical patent/EP2592800A1/fr
Priority to US13/673,505 priority patent/US9306844B2/en
Publication of EP2592800A1 publication Critical patent/EP2592800A1/fr
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/74—Address processing for routing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/58—Association of routers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/109—Integrated on microchip, e.g. switch-on-chip
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/70—Virtual switches
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/34—Source routing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/60—Router architectures

Definitions

  • Embodiments relate to virtual networks and in particular but not exclusively to virtual network routers. In particular but not exclusively, some embodiments relate to routers for networks on-chip with a virtual network support.
  • IP intellectual property
  • MPSoC multi-processor system-on-chip MPSoC
  • a router having: a plurality of virtual networks, each virtual network having a plurality of virtual network inputs and a plurality of virtual network outputs; the router further comprising: a plurality of output links, each virtual network output being associated with an output link; at least one decoder for decoding a header of a data unit received on a virtual network of one of the virtual network inputs and generating: a first request for allocating a virtual network output of the virtual network to the virtual network input; and a second request for allocating an output link associated with the virtual network output to the virtual network output; the router further comprising: arbitration circuitry for carrying out the arbitration of the first request and the arbitration of the second request in parallel.
  • Each virtual network may be associated with a decoder for decoding headers of data units received on virtual network inputs of the respective each virtual network and may generate a request for allocation of a virtual network output of the respective each virtual network to the data unit.
  • Each decoder may be further configured to generate a request for an output link associated with the requested virtual network output.
  • the arbitration circuitry may comprise a plurality of first arbiters, each first arbiter associated with one of the plurality of virtual networks. Each first arbiter may be configured to allocate the virtual network outputs to the virtual network inputs of the associated virtual networks in response to requests.
  • the arbitration circuitry may further comprise a plurality of second arbiters, each second arbiter associated with one of the output links. Each output link arbiter may be configured to allocate the respective associated output link to one of the virtual networks by allocating the output link to a virtual network output from said one of the virtual networks.
  • the router may be configured to provide a data unit to a virtual network in response to a virtual network identifier of the packet.
  • the virtual network identifier may correspond to a traffic class of the data unit.
  • the virtual network identifier may correspond to a one of a request or response traffic.
  • Each decoder may be configured to extract the routing information from a header of the data unit.
  • Each decoder may comprise combinational logic.
  • Each decoder may be configured to request the allocation of a virtual network output and request the allocation of an output link corresponding to the virtual network output for each data unit in accordance with the extracted routing information.
  • the data unit may comprise at least one flit.
  • the header may be contained in a first flit of the data unit.
  • the header may be a constant size for each data unit.
  • the header may be generated by a network interface of a network.
  • the first arbiter and second arbiters may comprise switches.
  • the router may further comprise an input buffer for each virtual network input.
  • the input buffers may be by-passable.
  • the router may be configured to bypass an input buffer of a virtual network input when there is no contention on a virtual network output requested for the virtual network input.
  • the virtual network router may further comprise an output buffer for each virtual network output.
  • the output buffers may be by-passable.
  • the virtual network router may be configured to bypass an output buffer of a virtual network output when there is no contention on an output link requested for the virtual network output.
  • a network comprising: a network interface for communication between a functional unit and a network, the network interface configured to determine a route of a data unit through the network and insert routing information indicative of the determined route in a header of the data unit; and a plurality of virtual network routers, each router having: a plurality of virtual networks, each virtual network having a plurality of virtual network inputs and a plurality of virtual network outputs; the router further comprising: a plurality of output links, each virtual network output being associated with an output link; at least one decoder for decoding a header of a data unit received on a virtual network of one of the virtual network inputs and generating: a first request for allocating a virtual network output of the virtual network to the virtual network input; and a second request for allocating an output link associated with the virtual network output to the virtual network output; the router further comprising: arbitration circuitry for carrying out the arbitration of the first request and the arbitration of the second request in parallel.
  • a method comprising: determining a route of a data unit through a network and inserting routing information indicative of the determined route in a header of the data unit; routing the data unit across the network, the routing comprising: inputting the data unit to one of a plurality of virtual network inputs of a virtual network in response to a virtual network indicator of the data unit; decoding a header of a data unit and generating: a first request for allocating a virtual network output of the virtual network to the virtual network input; and a second request for allocating an output link associated with the virtual network output to the virtual network output; the router further comprising: arbitration circuitry for carrying out the arbitration of the first request and the arbitration of the second request in parallel.
  • FIG. 1 shows an example of the multiprocessor system-on-chip MPSoC.
  • the MPSoC 100 may comprise several functional units 101.
  • the functional units may be for example IP cores.
  • the functional units 101 may be implemented on an integrated circuit and may form a system-on-chip SoC.
  • the MPSoC of figure 1 may also comprises a communication infrastructure 102.
  • the communication infrastructure 102 may facilitate communication between the different functional units or IP cores making up the system on-chip 100.
  • the communication infrastructure may carry and route packets of data between the functional units 101.
  • Figure 1 is by way of example only and embodiments may be applicable to system-on-chip implemented differently to figure 1 .
  • the system-on-chip may be implemented with different functional units, with all or only some of the functional units being IP cores.
  • the communication infrastructure 102 of figure 1 may be implemented as a network-on-a-chip.
  • an implementation of the network-on-chip may decouple the functional units 101 from a physical implementation of an infrastructure interconnecting the functional units 101. This may allow the functional units 101 to be implemented in different systems independent of the communication infrastructure used by that system.
  • On-chip connectivity may also be enhanced by the implementation of advanced communication features by the network on-chip. For example a network-on-chip may implement quality of service mechanisms in some embodiments.
  • Figure 2 shows an example of a network on-chip.
  • Figure 2 shows a first and second IP core 101, each connected to a network interface 201. It will be appreciated that two IP cores 101 is by way of example only and the network may provide a communication for hundreds of IP cores 101.
  • the network of figure 2 may comprise routers 203. It will be appreciated that the number of routers in a network may be dependent on for example the communication requirements of the network and a number of functional units communicating via the network.
  • Each of network interfaces 201 may be connected to a router 203 by a connection 202.
  • the connection 202 may be a physical wire implemented on an integrated circuit or may be any appropriate connection, for example an optical connection.
  • the routers 203 may receive data to be transmitted on the network from the network interface or from other routers 203 and may transmit and route the data accordingly until the data reaches its destination.
  • Routers 203 may send and transmit packets of information.
  • large packets may be broken into smaller portions or flits and the data may be transmitted in flits.
  • routers may decode an address in a packet header through use of routing tables.
  • the decoding of addresses in such a way may necessitate the router carrying out complex functions and may introduce latency in the data path.
  • These prior art routers may also have a pipeline stage after the address decoding in order to compensate for the complexity of the address decoding.
  • a packet header containing an address may be contained in a number of flits. In these cases, the router waits until all the flits making up the packet header are received before an address can be decoded. This may also introduce latency into the network.
  • Packets that are routed through a number of routers before reaching their destination may therefore experience this latency accumulating into a significant delay. This may be undesirable in latency sensitive systems.
  • Embodiments may implement a network-on-chip router supporting virtual networks.
  • the network on-chip router may realise a fully combinational data path.
  • a data path may be provided with a potential zero cycle delay when there is no contention.
  • Some embodiments may provide routers that guarantee no packets are lost while still being capable of routing a packet in zero cycles.
  • Figure 3 shows a router 300 according to an embodiment.
  • the router may support a configurable number of virtual networks 305, 306 and 307.
  • Figure 3 shows the router 300 having a first and second input 301 and 302 and a first and second output 303 and 304.
  • the first and second input 301, 302 and first and second output 303, 304 may be implemented as links to other elements of the network, for example as wires connecting the router 300 to at least one other router and/or to at least one functional unit.
  • the router 300 may support a first virtual network 305, second virtual network 306 and third virtual network 307.
  • Each virtual network may have virtual network inputs 308a, 308b and 308c, and 309a, 309b and 309c associated with each input 301, 302 over which data associated with that network is passed from the input 301, 302.
  • Each virtual network may have virtual network outputs 310a, 310b, 310c and 311a, 311b and 311 c for passing data from that virtual network to the outputs 303, 304.
  • the virtual network outputs 311a, 311b and 311c may be output to a first multiplexor 313 and the virtual network outputs 310a, 310b and 310c may be connected to a second multiplexor 312.
  • the first and second multiplexors 313 and 312 may provide outputs to a respective first and second output link 303 and 304.
  • the output links may be output links to other network elements and implemented similarly to the input links 301 and 302.
  • the first and second input links 301 and 302 may carry data packets. These data packets may be communication from other functional units across the network-on-chip. The data packets may be received from functional units and/or other routers. In some embodiments the input links may receive data associated with different virtual networks. For example a data packet for the first virtual network 305 may be associated with the virtual network input 308a and the virtual network output 311a.
  • the router may determine with which virtual network a packet corresponds.
  • the packet may be provided from the input link to the determined virtual network over the corresponding virtual network input.
  • a packet may be routed to a virtual network input according to a virtual network indicator
  • the router may also determine which virtual network output of that virtual network the packet is associated with.
  • the packet may carry information to which of the networks virtual network outputs that packet is destined. This indication may be in the form of routing information for example contained in a header of the packet.
  • Each virtual network may then route the packets received on its virtual network input to a virtual network output according to the received indication.
  • the router 300 may carry out routing for a plurality of virtual networks.
  • the multiplexors 313 and 312 may receive the packets output from the virtual networks and multiplex these packets onto the output links 303 and 304 respectively.
  • each of the virtual networks 305, 306 and 307 may be associated with a service class.
  • the first virtual network 305 may be associated with best effort data
  • the second virtual network 306 may be associated with guaranteed throughput data
  • the third virtual network 307 may be associated with low priority data.
  • Packets on the input links 301 and 302 associated with for example best effort data may be input via the virtual network inputs 309a and 308a respectively to the best effort virtual network 305.
  • Packets associated with the other service classes may be input to the respective virtual networks via the corresponding virtual network inputs.
  • virtual networks being associated with different service classes is by way of example only and the virtual networks may be associated with other types or classes of network traffic.
  • a virtual network may be reserved for request traffic while another virtual network is reserved for response traffic.
  • Figure 4 shows an example of a router as seen from the perspective of a virtual network.
  • Figure 4 may depict a router as seen from the perspective of the first virtual network 305.
  • FIG 4 shows a virtual network router 400.
  • the virtual network router 400 may have a first virtual network input 309a and a second virtual network input 308a from inputs links 302 and 301 respectively. It will be appreciated that these virtual network inputs may be the same virtual network inputs as depicted in Figure 3 . However they are not restricted to this.
  • the virtual network router 400 may also have a first virtual network output 311a and a second virtual network output 310a.
  • the virtual network router may provide outputs onto an output link 303 and 304.
  • the virtual network inputs 309a and 308a may be input into a first and second by-passable input buffer 402 and 401 respectively.
  • the output of each of these buffers may be connected to a switch 404 which may provide a first and second output to first and second optional by-passable output buffers 406 and 405 respectively.
  • the first and the second by-passable output buffers 406 and 405 may have respective outputs corresponding to the first and second virtual network outputs 311a and 310a.
  • the first and second output registers 408 and 407 may provide an output to the first and second output links 303 and 304. It will be appreciated that the first and second virtual network outputs 311 a and 310a may be multiplexed with outputs from other virtual networks onto the first and second output links 303 and 304.
  • the virtual network router 400 of figure 4 may receive packets associated with that virtual network from the first input link 301 on the virtual network input 309a and packets from the second input link 302 on the second virtual network input 308a.
  • the virtual network router 400 may also receive an indication of to which virtual network output the packets are to be routed.
  • this indication may be provided by a decoder.
  • the decoder may receive and decode a packet header containing routing information and generate the indication of the virtual channel output based on the address information.
  • the decoder may extract the routing information and generate routing requests to the switch for the received packet or flit.
  • the decoder may also generate a request for an output link in parallel with the request for the virtual network output.
  • the routing information may be contained in the first flit of a packet.
  • the first flit may contain an explicit indication of the output link on which the packet is to be output.
  • the routing information may contain an explicit indication as to which virtual channel output the packet is to be routed.
  • the network may make use of source routing.
  • a path for a packet is calculated before a packet is injected into the network.
  • the network interface may determine the path of the packet based on a destination of the packet.
  • routers such as router 400 may extract the routing information from the packet header. The information may indicate the immediate next destination for the packet, for example the next router. In this manner the router 400 may implement combinational logic to determine routing information in the packet header.
  • the header may contain a 'path' field.
  • the so-called 'path' field may contain a list of output ports identifiers, to be used by the routers crossed by the packet.
  • the router may consume or remove this information. For example it may perform a right shift on the 'path' field, so that the routing information for the next router is moved to the least significant bits.
  • the number of bits that identify the output port may depend on the total number of output ports in the router. It will be appreciated that the least significant bits are by way of example only, and the routing information may be in the most significant bits in which case a shift left may be performed.
  • the switch 404 may output the packets received on virtual network input 309a to the first or the second output buffer 406 and 405 according to a routing request from the decoder. Similarly the packets received on the second virtual network input 308a may be output to the first or second output buffer 406 and 405 according to a routing request from the decoder.
  • the packets may be buffered by the first and second bypassable output buffers 406 and 405 on the first and second virtual network outputs 311a and 310a until the first and second physical output links 304 and 303 become available.
  • the packets may then be passed to the first and second output register 408 and 409 to be output on the first and second output links 304 and 303.
  • the virtual network router 400 may serve to route packets from the virtual network inputs to virtual network outputs.
  • a virtual network input and output may be associated with a virtual channel of the router and packets may be routed according to those channels.
  • the first and second bypassable input buffers 402 and 401 may be used to buffer input packets when there is contention on the virtual network outputs 311a and 310a. For example if a packet on the second virtual network input 308a and a packet on the first virtual network input 309a request to be output on virtual network output 311a at the same time, one of the packets may be output and the other may be buffered in accordance with an output virtual network arbitration. Flits of a packet may also be buffered by the bypassable input buffers when a corresponding bypassable output buffer is full even if there is no contention on that output.
  • the bypassable input buffer may buffer flits of a packet until a requested output virtual channel is available.
  • the router and virtual networks may be such that if there is no contention on the virtual channel outputs the bypassable input buffers may be bypassed. By bypassing the input buffers in some embodiments a packet may traverse the switch with zero cycles.
  • the first and second bypassable output buffers 406 and 405 may buffer an output packet on the virtual network outputs 311a and 310a when an output link 303, 304 is not available.
  • the packet on the virtual channel output 310a or to 311a may bypass the output buffer 405 or 406 to be output on the physical output link without incurring a clock cycle.
  • a packet may traverse the data path of router 400 in zero cycles.
  • the buffers may receive an indication from output link and virtual network arbiters of any contention on the output links of virtual network outputs.
  • the indication may be provided to other control units of the router which may bypass the buffers in response to the indication.
  • bypassable input and output buffers may provide a flexible data path.
  • the flexible data path may allow a delay of a data packet through a virtual network router to be adjustable and data packets with no contention on the virtual output network and output link may be routed in zero cycles.
  • the output buffer may be optional.
  • the bypassable input buffers 402, 401 may provide buffering when an output link is not free and the output buffers may be removed.
  • the first and second output registers 408 and 407 may be optional. These registers may provide retiming for the output of the data packets onto the output link. In some embodiments this retiming may be to resynchronise the output packets with transmission timing of the network.
  • the switch 404 may be a crossbar switch. Alternatively the switch 404 may be any connecting switch connecting multiple inputs to multiple outputs.
  • the router 400 may additionally comprise a decoder for decoding routing information contained in the packet.
  • a decoder may be provided for each virtual network or may be provided for more than one virtual network.
  • the decode may comprise decoding logic.
  • the decoder may be connected to virtual network and link arbiters.
  • the virtual network of Figure 4 may be used to route a packet, for example as follows.
  • the packet may be transmitted with a virtual network identifier.
  • the virtual network identifier may be used by the router to input the packet to the correct virtual network input on the packets arrival.
  • the virtual network indicator may be for example be transmitted in parallel with the packet.
  • the virtual network indicator may be for example appended onto the packet when it is inserted into the network.
  • Routing information may be contained in a header of the packet.
  • the header may be contained within a first flit of the packet.
  • the routing information may be decoded by the decoder to determine to which output link and/or virtual network output the packet is to be routed.
  • the routing information may be used to generate requests for a virtual network output and output link.
  • the first flit may be adjustable so that the header may be entirely contained in the flit.
  • the header may be of a fixed size.
  • a routing algorithm carried out at an IP block or functional unit may generate the header and in some embodiments the header may remain unchanged by the routers.
  • the routing algorithm may be a deterministic algorithm and may carry out address decoding and other complex calculations to minimise the size of the header.
  • the routing algorithm may determine a routing path for a packet and may insert an indicator of an output link and/or virtual network output for each router.
  • the header may contain a series of bits indicating an output link with a bit position corresponding to a router.
  • the decoder may be implemented by combinational logic to determine the virtual network output or output link for the packet.
  • data for the data packet is generated by a functional unit.
  • the data may be passed to a network interface which receives an indication of a destination for the packet.
  • the network interface may generate routing information for the packet and insert this information in the packet header.
  • a complexity of the routing information may be minimised by performing any complex logic required for the routing algorithm in advance by the network interface. For example the routing information may be generated to provide an explicit routing information in the header of a packet.
  • the virtual network router 400 when the virtual network router 400 receives the first flit of a packet, it extracts routing information from the packet header. This may greatly simplify the decoding of an address for a packet as the data is readily available in the first flit containing the packet header. In some embodiments routing information may be available immediately. The routing information may be inserted in a packet header and that packet header may be contained within the first flit of a packet independent from flit size. In this manner in embodiments, routing information may be available immediately to the router and complex decoding may be avoided.
  • Figure 5 shows an example of the router 300 supporting a number of virtual networks.
  • the router 300 may comprise virtual network routers 305 and 306 for each supported virtual network.
  • the virtual network routers 305, 306 may be similar to virtual network router 400.
  • the router 300 receives packets on the first and second input link 301 and 302 and divides these packets up into the virtual network inputs 308a. 308b and 308c, and 309a, 309b and 309c. Virtual network inputs 308a and 309a are shown in figure 5. Figure 5 also shows the first virtual network 305 and the second virtual network 306.
  • the first virtual network 305 comprises the first and second bypassable input buffers 402 and 401, switch 404, the first and second bypassable output buffers 406 and 405 and the first and second output registers 408 and 407 as per Figure 4 .
  • the first and second virtual network outputs 311a and 310a from the first and second bypassable output buffers 406 and 405 are output to a first and second multiplexer 313 and 312 respectively.
  • the output of the multiplexers 313 and 312 may be input to the first and second output registers 408 and 407 respectively.
  • the first and second output registers 408 and 407 may output the data packets on the output links 303 and 304.
  • an output virtual network arbiter 501 may be connected to the first and second bypassable output buffers 406 and 405. In addition the output virtual network arbiter 501 may be connected to the switch 404. The arbiter 501 may be connected to a decoder 510 that decodes routing information for a packet. The decoder may provide requests for virtual network outputs for a virtual network input for decoded packet.
  • the decoder 510 may be connected to the arbiter 501 and arbiter 502, 503 and to buffers 401, 402, 405 and 406.
  • the decoder 510 may comprise a decoder for each of the virtual networks.
  • Each of the virtual network decoders may send requests to the link arbiter for each output link requesting that output link to be allocated to a virtual network output of the virtual network. For example a first decoder may request an output link for a virtual network output on a first virtual network and a second decoder may request an output link for a virtual network output of a second virtual network.
  • Each of the decoders may receive packets sent to the virtual network of that decoder and decode the packet headers.
  • the first and second multiplexers 313 and 312 may receive the virtual network outputs associated with the other virtual networks (not shown) in addition to the first and second virtual channel outputs 311 b and 310b from the second virtual network 306. It will be appreciated that the router 300 may comprise more than two virtual networks which may be similar to the first virtual network, and the multiplexer 312 and 313 will receive outputs from each of these networks.
  • Each of the multiplexer 313 and 312 may be associated with a link arbiter 503 and 502 respectively.
  • the link arbiter may be connected to the decoding logic and may receive a request from the decoding logic for an output link to be allocated to a virtual network output.
  • Each link arbiter 502, 503 may provide an input to a respective multiplexer 312 and 313.
  • the input links 301 and 302 receive packets.
  • a header of each packet may be contained in a first flit of the packet and the header may contain routing information.
  • the router 300 may provide that packet to one of the virtual networks based on a virtual network indicator of the packet.
  • Each virtual network may contain a decoder 510 for decoding a first flit of a packet containing routing information and determining a virtual network output.
  • Packets on the first and second virtual network inputs 309a and 308a for the first virtual network 305 are provided to the bypassable input buffers 402 and 401 respectively.
  • the switch 404 determines to which virtual channel output of the first virtual network the packets on the virtual network inputs 308a and 309a are to be transferred.
  • the output virtual network arbiter 501 receives an indication of the destinations of each of the packets. This may be in the form of a request from the decoding logic. In embodiments the output virtual network arbiter 501 may also receive an indication of the state of the bypassable input buffer. The output virtual network arbiter 501 may arbitrate the output of the packets to the virtual network outputs 310a and 311a. This may be dependent on a destination of a packet and a state of the bypassable input buffers.
  • the output virtual network arbiter 501 may provide arbitration concerning virtual network output contention for the virtual network outputs within the first network. It will be appreciated that in some embodiments when there is no output contention, in other words packets on the virtual channel inputs 308a and 309a do not request the same virtual channel output 310a and 311a, an input buffer may be bypassed and the packet may be passed to the virtual network output. It will be appreciated that if an input buffer already contains data the packet will be queued.
  • each of the virtual networks provide virtual network routing for the virtual channels associated with that network. This may be provided similarly to the first virtual network 305.
  • virtual network 306 carries out a virtual network routing for the virtual network inputs 309b and 308b and provides virtual network outputs 311 b and 310b to the first and second multiplexers 313 and 312.
  • the inputs to the first multiplexer 313 may be destined to the output link 303 and the inputs to the second multiplexer 312 may be destined to the output link 302.
  • a link arbiter 502 may be provided as a second level of arbitration in order to control the multiplexing of the inputs to the second multiplexer 312 to the output link 304.
  • a link arbiter 503 may be provided to control the multiplexing of multiplexer 313 of the input virtual channel outputs from the virtual networks to the output link 303.
  • the decoder 510 may generate requests to the output link and virtual network arbiters after decoding the packet header. These requests may be generated in parallel and in some embodiments the output link and virtual network output may be allocated in parallel. In these embodiments, a packet may cross a virtual network in zero cycles where there is no contention because it does not need to be buffered while output link arbitration is carried out. The output link may be allocated to a virtual network output before the allocation of the virtual network output is known. If the virtual network output request was not successful the virtual network output will have been allocated to another packet and this packet will be passed to the allocated output link.
  • first and second output registers 408 and 407 may be provided in order to provide retiming of the flits or data packets to be output on the output links 303 and 304.
  • the routing information accessed in the packet header may be decoded by use of combinational logic and may be done in zero cycles.
  • the output virtual network arbiter 501 provides the first level of arbitration. As discussed this arbitration may be with respect to virtual network inputs requesting the same virtual channel output on a virtual network.
  • the virtual network arbiter may allocate the virtual channel per packet. For example a flit for a packet header may be coded such that that packet is destined for the first virtual network input 309a and requests to be output on the virtual network output 310a. The output virtual network arbiter may then assign a channel from the virtual network input 309a to virtual network output 310a for that packet.
  • the virtual network outputs 310a and 311a may receive the arbitrated packets from the virtual network inputs 309a and 308a. These packets may be input to the multiplexer 312 and 313 along with other virtual network outputs from the other virtual networks.
  • the link arbiters 503 and 502 may provide a second level of arbitration. These link arbiters 502 and 503 in some embodiments may control the output of data back onto the physical links 303 and 304.
  • the virtual network arbiter may allocate virtual network outputs on a packet-by-packet basis and the output link arbiter may allocate the output links on a flit-by-flit basis.
  • the packets from the virtual network outputs may be buffered by the output buffers.
  • Embodiments may implement a speculation-like technique for generating requests to the output virtual network arbiter 501 and the link arbiters 502 and 503.
  • requests to the relative output link arbiter 502 or 503 may be generated in parallel with requests to the output virtual network. This may occur at a point before a flit has acquired ownership of the virtual network.
  • a first level of requests may be generated for the output virtual network arbiter 501 for each packet at a virtual network input, requesting one of the virtual network outputs.
  • Each virtual network output may correspond to an input to a second level of arbitration that arbitrates for an output link.
  • a first level request for a packet may request a virtual network output corresponding to a first output link and a second level request for that packet may request the output link.
  • the first and second level requests may be generated in parallel. If for example, the first level request is not granted but the second level request is, this will be due to another packet being granted the request for the virtual network output and a packet will be present on the virtual network output input into the second level arbitration.
  • the second level arbitration may be carried out being requests from packets that are at the virtual network inputs and packets that have been buffered on the input to the second level of arbitration.
  • Embodiments may allow requests from buffered packets or flits and non-buffered packets or flits to be arbitrated together. This may result in a simple arbitration that allows a packet to cross the router without an incurred delay when a virtual network output and output link is available.
  • Figure 6 shows an example of an embodiment of a method carried out by a router.
  • the router may receive a packet.
  • the packet may contain an indication of which virtual network it is associated with.
  • the router may pass the packet to the indicated virtual network at step 601.
  • a decoder 510 of the virtual network may decode routing information for the packet and determine a virtual network output and output link associated with the packet.
  • the routing information may be decoded through use of combinational logic.
  • the decoding may occur in less than a clock cycle.
  • the decoder 510 may generate a virtual network arbitration request 603. This request may be sent to the output virtual network arbiter 501.
  • the decoder 510 may also generate an output link request at step 604. This request may be sent to a link arbiter 502 or 503. In some embodiments the generation of requests at step 603 and 604 may be carried out in parallel. The requests may be generated from the routing information in the packet header.
  • a decoder 510 may extract routing information from the packet header contained in the first flit and determine on which virtual network output the packet is to be output. Once the routing information has been extracted, a request may be generated to the output virtual network arbiter as well as a parallel request to the output link arbiter. In this embodiment the request for the output link occurs before the virtual network output arbiter has allocated a virtual network output for the packet.
  • embodiments may generate the parallel request to the output link. Even though the output virtual network arbiter may not have granted the connection between the virtual channel input and output yet.
  • the virtual network output will be granted to the requesting packet. However if there is contention on the virtual network output, even if the virtual network output is not allocated to that packet, it will be allocated to another packet causing the contention.
  • a virtual packet will be output to the virtual output channel and hence regardless of the results of the arbitration by the virtual network arbiter, a packet will be available on the output link to be output to that physical output link. There will be data present on a virtual network output for which the output link has been assigned in response to a request regardless of whether that packet corresponds to data from which the request was generated.
  • routing of a packet may take place in zero cycles through parallel allocation of a virtual network output and output link and combinational decoding and bypassing of any pipeline stages such as buffers when there is no contention.
  • Embodiments may provide a purely combinational artificial path for a virtual router when there is no contention.
  • pipeline stages may be omitted.
  • the decoder may comprise a plurality of decoders, one for each virtual network. Each of the plurality of decoders may send respective requests to the link arbiters.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
EP11306458.8A 2011-11-09 2011-11-09 Routeur sur puce de réseaux Withdrawn EP2592800A1 (fr)

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