EP2549384A4 - Multi-core processor system, arbitration circuit control method, and arbitration circuit control program - Google Patents

Multi-core processor system, arbitration circuit control method, and arbitration circuit control program

Info

Publication number
EP2549384A4
EP2549384A4 EP10847910.6A EP10847910A EP2549384A4 EP 2549384 A4 EP2549384 A4 EP 2549384A4 EP 10847910 A EP10847910 A EP 10847910A EP 2549384 A4 EP2549384 A4 EP 2549384A4
Authority
EP
European Patent Office
Prior art keywords
cpu
access
circuit control
arbitration circuit
cpus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP10847910.6A
Other languages
German (de)
French (fr)
Other versions
EP2549384A1 (en
EP2549384B1 (en
Inventor
Koichiro Yamashita
Hiromasa Yamauchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of EP2549384A1 publication Critical patent/EP2549384A1/en
Publication of EP2549384A4 publication Critical patent/EP2549384A4/en
Application granted granted Critical
Publication of EP2549384B1 publication Critical patent/EP2549384B1/en
Not-in-force legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5083—Techniques for rebalancing the load in a distributed system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)

Abstract

CPUs acquire for each of the CPUs, a measured speed of access to a shared memory via an acquiring unit. The CPUs calculate for each of the CPUs response performance of the CPU from the measured access speed and a theoretical access speed for the CPU via a response performance calculating unit. Another CPU calculates ratios of access rights of the plurality of CPUs to the shared memory via an access ratio calculating unit such that a ratio of an access right of a CPU is larger than a ratio of an access right of another CPU whose response performance is higher than that of the CPU. The other CPU notifies an arbiter circuit of the ratios of the access rights calculated, via a notifying unit.
EP10847910.6A 2010-03-18 2010-03-18 Multi-core processor system, arbitration circuit control method, and arbitration circuit control program Not-in-force EP2549384B1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2010/054709 WO2011114496A1 (en) 2010-03-18 2010-03-18 Multi-core processor system, arbitration circuit control method, and arbitration circuit control program

Publications (3)

Publication Number Publication Date
EP2549384A1 EP2549384A1 (en) 2013-01-23
EP2549384A4 true EP2549384A4 (en) 2013-05-22
EP2549384B1 EP2549384B1 (en) 2018-01-03

Family

ID=44648624

Family Applications (1)

Application Number Title Priority Date Filing Date
EP10847910.6A Not-in-force EP2549384B1 (en) 2010-03-18 2010-03-18 Multi-core processor system, arbitration circuit control method, and arbitration circuit control program

Country Status (5)

Country Link
US (1) US9110733B2 (en)
EP (1) EP2549384B1 (en)
JP (1) JP5541355B2 (en)
CN (1) CN102804149B (en)
WO (1) WO2011114496A1 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103150005A (en) * 2013-03-01 2013-06-12 福州瑞芯微电子有限公司 Multi-core structure for asymmetric low-power mobile device
JP6060098B2 (en) * 2014-01-29 2017-01-11 日本電信電話株式会社 Response quality estimation apparatus, response quality estimation method and program
US9483299B2 (en) * 2014-06-30 2016-11-01 Bmc Software, Inc. Capacity risk management for virtual machines
JP6490552B2 (en) * 2015-09-29 2019-03-27 シャープ株式会社 Information processing apparatus, electronic apparatus, control program, and information processing apparatus control method
CN106793093B (en) * 2015-11-19 2019-12-06 大唐移动通信设备有限公司 Service processing method and device
US9971580B2 (en) 2016-03-18 2018-05-15 Intel Corporation Fast access and use of common data values relating to applications in parallel computing environments
CN105808357B (en) * 2016-03-29 2021-07-27 沈阳航空航天大学 Multi-core multi-thread processor with accurately controllable performance
JP6895719B2 (en) * 2016-06-24 2021-06-30 日立Astemo株式会社 Vehicle control device
FR3061327B1 (en) * 2016-12-26 2019-05-31 Thales METHOD FOR CONTROLLING A MULTI-HEART PROCESSOR AND ASSOCIATED CALCULATOR
US10824475B2 (en) * 2017-03-24 2020-11-03 Tata Consultancy Services Limited Systems and methods for estimating computation times a-priori in fog computing robotics
JP6995644B2 (en) * 2018-01-23 2022-01-14 日立Astemo株式会社 Electronic control device

Citations (2)

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US20060136681A1 (en) * 2004-12-21 2006-06-22 Sanjeev Jain Method and apparatus to support multiple memory banks with a memory block
EP1785828A1 (en) * 2005-11-01 2007-05-16 Hitachi, Ltd. Storage system

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JP2504818B2 (en) * 1988-11-24 1996-06-05 富士通株式会社 Common memory control method in multiprocessor device
JPH07281942A (en) * 1994-04-14 1995-10-27 Asahi Kasei Micro Syst Kk Arbitration method for shared resources
US5682522A (en) * 1995-07-18 1997-10-28 Silicon Integrated Systems Corp. Shared memory architecture of graphics frame buffer and hard disk cache
JPH10143382A (en) * 1996-11-08 1998-05-29 Hitachi Ltd Method for managing resource for shared memory multiprocessor system
JPH11110363A (en) 1997-09-30 1999-04-23 Sharp Corp Multiprocessor system
JP2002244917A (en) * 2001-02-15 2002-08-30 Matsushita Electric Ind Co Ltd Access management device and program
JP2003271404A (en) * 2002-03-19 2003-09-26 Fujitsu Ltd Multiprocessor system
US20060136381A1 (en) * 2004-12-17 2006-06-22 Glaser Howard J Method and system for a text based search of a self-contained document
JP2007004595A (en) 2005-06-24 2007-01-11 Hitachi Ltd Computer control method, computer, information processing system and program
EP1949203B1 (en) 2005-07-14 2011-11-30 Nxp B.V. Using historic load profiles to dynamically adjust operating frequency and available power to a handheld multimedia device processor core
TW200805047A (en) 2005-12-23 2008-01-16 Koninkl Philips Electronics Nv Performance analysis based system level power management
JP2008027245A (en) * 2006-07-21 2008-02-07 Matsushita Electric Ind Co Ltd Memory access controller and memory access control method
JP2008117001A (en) * 2006-10-31 2008-05-22 Matsushita Electric Works Ltd Shared memory interface
CN100562854C (en) * 2008-03-11 2009-11-25 浙江大学 The implementation method of load equalization of multicore processor operating system
US8209493B2 (en) * 2008-03-26 2012-06-26 Intel Corporation Systems and methods for scheduling memory requests during memory throttling
JP2009251871A (en) * 2008-04-04 2009-10-29 Nec Corp Contention analysis device, contention analysis method, and program
CN101610209B (en) * 2008-11-28 2011-08-03 北京网康科技有限公司 Method and device for multi-core parallel concurrent processing of network traffic flows

Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
US20060136681A1 (en) * 2004-12-21 2006-06-22 Sanjeev Jain Method and apparatus to support multiple memory banks with a memory block
EP1785828A1 (en) * 2005-11-01 2007-05-16 Hitachi, Ltd. Storage system

Non-Patent Citations (1)

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Title
See also references of WO2011114496A1 *

Also Published As

Publication number Publication date
JP5541355B2 (en) 2014-07-09
US9110733B2 (en) 2015-08-18
CN102804149A (en) 2012-11-28
US20130013834A1 (en) 2013-01-10
WO2011114496A1 (en) 2011-09-22
CN102804149B (en) 2016-01-13
JPWO2011114496A1 (en) 2013-06-27
EP2549384A1 (en) 2013-01-23
EP2549384B1 (en) 2018-01-03

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