EP2515426A1 - Schaltkreis - Google Patents

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Publication number
EP2515426A1
EP2515426A1 EP11250488A EP11250488A EP2515426A1 EP 2515426 A1 EP2515426 A1 EP 2515426A1 EP 11250488 A EP11250488 A EP 11250488A EP 11250488 A EP11250488 A EP 11250488A EP 2515426 A1 EP2515426 A1 EP 2515426A1
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EP
European Patent Office
Prior art keywords
current
inductive component
value
switching circuit
signal representative
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP11250488A
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English (en)
French (fr)
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EP2515426B1 (de
Inventor
Wilhelmus Hinderikus Maria Langeslag
Hans Halberstadt
Jeroen Kleinpenning
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NXP BV
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NXP BV
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Publication date
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Priority to EP11250488.1A priority Critical patent/EP2515426B1/de
Priority to CN201210113273.8A priority patent/CN102751877B/zh
Priority to US13/449,903 priority patent/US9036375B2/en
Publication of EP2515426A1 publication Critical patent/EP2515426A1/de
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Publication of EP2515426B1 publication Critical patent/EP2515426B1/de
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • H02M3/33523—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with galvanic isolation between input and output of both the power stage and the feedback loop
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0025—Arrangements for modifying reference values, feedback values or error values in the control loop of a converter

Definitions

  • the present disclosure relates to the field of switching circuits and methods of operating switching circuits, and particularly, although not exclusively, switching circuits that have a controller that is configured to determine an average output current of the switching circuit.
  • SMPS switched mode power supplies
  • the sensed output variable can then be used to regulate the SMPS so that the output is at the desired level. It is known to sense the output variable, compare it with a reference value at the secondary side, and send an error signal representative of the comparison to the primary side for regulation.
  • EP 1405397 discloses a current controlled switched mode power supply wherein the line voltage and primary current are emulated by means of an auxiliary winding on the primary side.
  • Current flowing in a resistor (R1) is buffered by means of first and second current mirrors to provide a voltage varying over time at an input of a pulse width modulator. This voltage is utilized to provide current mode controlled operation of the switch mode power supply.
  • a switching circuit comprising:
  • the magnetic flux in the inductive component may also be referred to as "magnetizing current”, and can be then the sum of all currents in the windings scaled by the turns ratios.
  • Integrating the voltage across the inductive component in order to generate a signal representative of the magnetic flux in the inductive component may be referred to as providing an emulated signal.
  • This emulated signal enables a more accurate value for the peak magnetization current to be determined and therefore more accurate switching circuit may be provided.
  • the switching circuit may be more accurate as more accurate feedback representative of the output of the circuit can be obtained, and therefore more accurate control of the circuit can be provided.
  • the controller may be configured to control the switch in order to provide a constant average output current in some examples.
  • the switch may be coupled between a voltage source and the inductive component.
  • the controller may be configured to use the signal representative of the magnetic flux in the inductive component to compensate for errors caused by propagation delay and/or resonance in the switching circuit.
  • Resonance may also be referred to as drain rise time in some embodiments, and can mean a maximum rise time of 1 ⁇ 4 x 2 x ⁇ x LC .
  • the rise time is determined by the current through the drain of the switch at switching-off, the total capacitance on the drain node and the input voltage.
  • Such errors may be introduced by the prior art when determining the peak magnetization current from signals at a primary side of a flyback converter (for example).
  • the switch may be a FET, or any other transistor.
  • the switch has a voltage at the source of the FET (Vsource), which can be measured by including a sense resistor at the source of the FET, and a desired value of the voltage at the source of the FET (Vsource,setpoint).
  • the controller may be further configured to record the value of the signal representative of the flux in the inductive component when the FET is switched off (S1) as a first value (A); and record the value of the signal representative of the flux in the inductive component at the start of the secondary stroke (S2) at the peak level of the flux as a second value (B).
  • the controller may be further configured to use the first value (A) and second value (B) to determine the ratio between the values of the signal representative of a flux in the inductive component at S1 and S2; and use the determined ratio to adjust Vsource or Vsource,setpoint in order to account for the peak magnetization current when controlling the switch.
  • the degree to which the magnetization current continues to increase after the FET is closed (that is, the signal at the gate of the FET goes low) can be determined, and recorded as the "determined ratio".
  • the determined ratio can then be used to offset a comparison between Vsource and Vsource,setpoint such that the average output current can be controlled more accurately.
  • a senseFET or current mirror may be used for monitoring the current through the switch.
  • the controller may be configured to multiply the value of Vsource,setpoint by first value/second value (A/B) to provide a corrected Vsource,setpoint signal, and compare the corrected Vsource, setpoint signal with Vsource in order to identify when the switch is to be operated.
  • the first and/or second values can be recorded from a previous cycle of operation of the switching circuit so that the switching circuit can be operated without having to wait for the second value to be recorded for a current cycle.
  • the controller may be configured to multiply a value of Vsource at S1 by second value/first value to determine the peak magnetization current.
  • the controller may be further configured to:
  • a primary stroke of the switching circuit can be considered as the period of time between the instant that the switch is closed and the instant of maximum magnetization current in the inductor.
  • a secondary stroke can be considered as the period of time that magnetic energy is flowing to the output up until the current in the inductive component crosses zero.
  • the primary stroke may be considered as the period of time between the instant that the switch is closed and the time at which the switch is turned off.
  • the controller may comprise an integrator configured to process the modified signal representative of the flux in the inductive component with a signal representative of the current through the switch in order to adjust the scaling factor (D). This may be performed in the analogue or digital domain.
  • the controller may comprise one or more switches that are configured to disconnect the modified signal representative of the magnetic flux in the inductive component and/or the signal representative of the current through the switch from the integrator such that the scaling factor (D) is not updated in accordance with signals that are not obtained during the primary stroke.
  • the controller may comprise a comparator configured to compare the signal representative of magnetic flux in the inductive component with the current through the switch during the primary stroke.
  • the controller may comprise an up/down counter that is configured to increase or decrease the scaling factor (D) in accordance with an output of the comparator.
  • the up/down counter may be configured not to adjust the scaling factor (D) if the output of the comparator is considered to represent an acceptable comparison between the modified signal representative of the magnetic flux in the inductive component and the signal representative of the current through the switch.
  • the comparator output may be processed at a specific moment in time related to a logic state of the system.
  • the controller may comprise a window comparator that is configured to increase or decrease the scaling factor (D) if the scaling factor (D) is outside a window.
  • a window comparator that is configured to increase or decrease the scaling factor (D) if the scaling factor (D) is outside a window.
  • the controller may be further configured to determine the average output current using the peak magnetization current value.
  • the average output current can be used in controlling the switch of the switching circuit.
  • the circuit may comprise an auxiliary winding coupled to the inductive component.
  • the auxiliary winding may be configured to provide the controller with a signal representative of the voltage across the inductive component.
  • the inductive component may be a transformer, and the controller may be configured to integrate the voltage across the magnetizing inductance of the transformer in order to generate the signal representative of the magnetization current in the transformer.
  • a switching circuit comprising:
  • a switching circuit comprising:
  • the inductive component may be a transformer, and in such examples, the controller may be configured to integrate the voltage across any winding of the transformer in order to generate the signal representative of the magnetizing current in the transformer.
  • Switching circuits that use a transformer as the inductive component include flyback converters, and embodiments of the invention can be useful for providing feedback whilst maintaining mains isolation between the primary and secondary sides of the transformer without having to use an opto-coupler as is known in the prior art.
  • the switching circuit may be configured to regulate its output, either directly or indirectly, in accordance with the peak magnetization current. This can provide for improved performance of the switching circuit in accordance with the feedback provided by the controller, which can represent a more accurate value for the output current than is achievable by the prior art.
  • the circuit may comprise an auxiliary winding coupled to the inductive component, wherein the auxiliary winding can be configured to provide a signal that is useable by the controller to generate the signal representative of the current in the inductive component.
  • the controller may comprise an integrator configured to generate the signal representative of the magnetizing current in the inductive component, wherein the integrator comprises:
  • the reset signal indicative of the current in the inductive component being zero may represent an indication of the end of the secondary stroke, or a turning point (which may be referred to as a "valley” or a “top”) in a voltage value at the auxiliary winding, or a turning point in the drain voltage during free resonance.
  • Free resonance is defined as resonance during the interval where both current in the transformer and parasitic capacitances at the transformer winding nodes ring, without forward current flowing in any diode in the output, or auxiliary supply.
  • the switching circuit may be a flyback converter, a boost converter, a buck converter, or any other type of switched mode power supply (SMPS) where energy is temporarily stored in an inductive component and released to an output thereafter (flyback conversion), or stored and transferred (buck conversion) or released and transferred (boost conversion).
  • SMPS switched mode power supply
  • the computer program may be a software implementation, and the computer may be considered as any appropriate hardware, including a digital signal processor, a microcontroller, and an implementation in read only memory (ROM), erasable programmable read only memory (EPROM) or electronically erasable programmable read only memory (EEPROM), as non-limiting examples.
  • the software may be an assembly program.
  • the computer program may be provided on a computer readable medium such as a disc or a memory device, or may be embodied as a transient signal.
  • a transient signal may be a network download, including an internet download.
  • One or more embodiments described herein relate to a switching circuit, such as a flyback converter, that has an inductive component including at least one winding and a switch coupled between a voltage source and the inductive component. Power can be transferred from a voltage source to the inductive component by operating the switch in accordance with a switch control signal.
  • a switching circuit such as a flyback converter
  • the switching circuit can also include a controller that is configured to use an emulated signal representative of the magnetic flux (which may also be referred to as magnetization current or magnetizing current) in the inductive component to accurately take into account a peak magnetization current value when controlling the switch. In this way, a more accurate average output current can be provided as the output of the switching circuit can be more accurately controlled.
  • a controller that is configured to use an emulated signal representative of the magnetic flux (which may also be referred to as magnetization current or magnetizing current) in the inductive component to accurately take into account a peak magnetization current value when controlling the switch. In this way, a more accurate average output current can be provided as the output of the switching circuit can be more accurately controlled.
  • Figure 1 illustrates a prior art flyback converter that senses an output variable, generates an error signal 120, and can send the error signal 120 to the primary side of the flyback converter via an optocoupler 122.
  • the circuit of Figure 1 receives a mains power signal 102, which is provided to a bridge rectifier 110 via a mains filter 108.
  • the positive output of the bridge rectifier 110 is provided to a first terminal of the primary side 106 of a transformer.
  • the second terminal of the primary side 106 of the transformer is coupled to the drain of a field effect transistor (FET) 104, and the source of the FET 104 is connected to the negative output of the bridge rectifier 110.
  • FET 104 is configured to operate as a switch that is connected in series with the voltage source 102 and the primary side 106 of the transformer such that power can be transferred from the voltage source 102 to the primary side 106 of the transformer when the switch is closed.
  • the FET 104 is operated in accordance with a switch control signal received at its gate from a flyback controller 130.
  • the flyback controller 130 is configured to cause the conduction channel of the FET 104 between the source and the drain to periodically conduct (thereby closing the switch) such that a desired output current 112 is provided at the output of the circuit.
  • the secondary side 107 of the transformer is connected to a diode 114 and a capacitor 116 in series, as is known in the art.
  • the signal at the junction between the diode 114 and capacitor 116 is taken as the output voltage 112, and in this example is also provided to a secondary control component 118.
  • the secondary control component 118 compares the output voltage (or any other output variable, such as current or power) with a reference value in order to generate an error signal 120 representative of the difference between the two signals.
  • the error signal 120 is provided to the light emitting diode 124 of an optocoupler 122, such that the error signal 120 can be passed from the secondary side of the circuit/transformer to a photo detector 126 of the optocoupler 122 that is associated with the primary side of the circuit/transformer. It will be appreciated that use of an optocoupler 122 maintains isolation between the primary and secondary sides of the circuit, which is a known feature of flyback converters.
  • the signal received at the photo detector 126 is then provided to the flyback controller 130 as a regulation input 128 such that the flyback controller 130 can adjust the operation of the FET/switch 104 in order to regulate the output to the desired level taking into account the error signal that has been received.
  • an optocoupler 122 and a secondary control 118 can be considered as too expensive, and this may be particularly true in the low power adaptor market and LED drivers market. Therefore, it may be desirable to provide a switching circuit that does not include an optocoupler.
  • Control of the output current without using an opto-coupler can be performed in different ways:
  • Figure 2 illustrates graphically the magnetization current 202 of the transformer and the drain voltage 204 of the switch at the primary side of a flyback converter.
  • the point in time represented by dotted line 206 represents the end of the secondary stroke.
  • Vin 208 represents the input voltage to the flyback converter, which is the output of the bridge rectifier 110 of Figure 1 .
  • the peak current through the MOSFET (I peak ) is required for use in the above equation.
  • the peak current through the MOSFET (I peak ) is not the equal to the peak of the magnetization current of the transformer (which is shown with reference 202 in Figure 2 ).
  • the diode conduction time (Tsec) is also measured (in a flyback system the output current is only flowing during Tsec) for use in the above equation.
  • the period time is set by the integrated circuit (IC).
  • IC integrated circuit
  • the period time has to be measured.
  • This second method can be more accurate than the first method identified above, as the potentially inaccurate variable "L” is not required to calculate the average output current (I out_av ) using the second method.
  • Dotted line 304 is the current through the MOSFET and solid line 302 is the magnetization current of the transformer.
  • the current through the MOSFET can be measured at the primary side of the transformer.
  • the magnetization current 302 is generally equal to the current 304 through the MOSFET (except for the capacitive spike 310) up until the MOSFET is switched off and the current 304 through the MOSFET falls sharply to zero. It can be seen that the magnetization current 302 continues to rise after the current 304 through the MOSFET falls sharply to zero. The magnetization current 302 reaches a "real I peak " 308 level that is greater than the maximum value of the current 304 through the MOSFET, and occurs after the maximum value of the current 304 through the MOSFET.
  • the difference between the peak current 308 value and the peak magnetization current 306 is referred to as an overshoot current 312.
  • the expected delay due to drain rise time and propagation delay error can be calculated as 100ns.
  • an error in the determined average current of at least 10% is introduced when the root mean square (RMS) mains voltage is changed from 90 V to 240 V.
  • the error in the determined average output current will be more than 15 %.
  • some standards require a maximum of 5 % error in the output current, these errors can prevent the standards from being satisfied.
  • One or more embodiments of the invention can be considered as providing compensation for the errors caused by propagation delay and/or drain rise time. This can be achieved by using an "emulated version" of the magnetization current to compensate for these errors.
  • FIG. 4 illustrates a switching circuit 400 according to an embodiment of the invention.
  • the switching circuit 400 comprises a voltage source 402, a switch 404 and an inductive component 406 all connected in series.
  • the switch 404 is operated in order to selectively transfer power from the voltage source 402 to the inductive component 406.
  • the switch can be a field effect transistor (FET) such as a MOSFET, a bipolar junction transistor (BJT), or any other suitable component(s) that can perform the necessary switching operation.
  • FET field effect transistor
  • BJT bipolar junction transistor
  • a primary stroke of the switching circuit can be considered as the period of time between the instant that the switch is closed and the instant of maximum magnetization current in the inductor, and a secondary stroke can be considered as the period of time that magnetic energy is flowing to the output up until the current in the inductive component crosses zero (see Figure 3 ).
  • the primary stroke may be considered as the period of time between the instant that the switch is closed and the time at which the switch is turned off.
  • the inductive component 406 comprises a single winding, although in other embodiments a transformer having two or more windings may be used.
  • voltage source 402, switch 404 and inductive component 406 can be part of a flyback converter or any other type of switched mode power supply (SMPS) where energy is temporarily stored in an inductor during a primary stroke and transferred to an output during a secondary stroke.
  • SMPS switched mode power supply
  • Such SMPS's can include a Buck converter, a Boost converter, and a Buck-Boost converter.
  • the switching circuit 400 also comprises a controller 408 that is configured to output a switch control signal 412 to regulate the switching circuit 400.
  • the controller 408 includes an integrator 430 that is configured to integrate the voltage across the inductive component 406 in order to generate a signal representative of a magnetic flux in the inductive component 406.
  • a magnetisation current is a current required to create the magnetic flux within the inductor component 406.
  • the magnetic flux in the inductive component 406 may be referred to as the magnetization current.
  • the generated signal representative of the magnetization current may be referred to as an emulated current.
  • the controller 408 can then use the emulated current to account for the real peak magnetization current in the inductive component in order to control the switch 404. As discussed above, the real peak magnetization current is shown with reference 308 in Figure 3 .
  • the controller 408 can use the signal representative of the current in the inductive component to more accurately determine the average output current such that operation of the switch 404 can be controlled to reduce the difference between the actual output current and the desired output current.
  • the signal representative of the current in the inductive component can be used to more accurately determine the peak magnetization current value for use in determining the average output current.
  • controller 408 Examples of implementations of the controller 408 are provided below.
  • FIG 5 illustrates a switching circuit 500 according to another embodiment of the invention.
  • the switching circuit 500 is based on a flyback converter, and components that have been described in relation to the flyback converter of Figure 1 , or are well known in the art, will not be described again here.
  • the switching circuit 500 includes an auxiliary/additional winding 510 coupled to the primary winding 506 of the transformer.
  • a signal that is experienced by the auxiliary winding 510 due to its magnetic coupling to the windings of the transformer 506, 507 is used as an FB (feedback) input to the flyback controller 508. It will be appreciated that the use of an auxiliary winding 510 maintains the isolation between the primary 506 and secondary 507 windings of the transformer of the flyback converter.
  • a first terminal of the auxiliary winding 510 is connected to ground, and a second terminal of the auxiliary winding 510 is connected to ground by two resistors 512, 514 in series.
  • the two resistors 512, 514 act as a resistive divider and the junction between the two resistors 512, 514 is connected to the controller 508 to provide the FB input signal to the controller 508.
  • it is the voltage at the FB input that is integrated in order to generate a signal representative of the current in the auxiliary winding 510.
  • an auxiliary winding 510 may not be required, and the signal for the FB input can be provided by a divided drain voltage with the DC component removed.
  • Such other embodiments are described and illustrated below with reference to Figures 14 and 15 . These embodiments may be particularly advantageous for Buck converters where it can be beneficial to use standard inductors, and not an extra winding.
  • Figure 6 illustrates further details of a controller 608 according to an embodiment of the invention. Also shown in Figure 6 are the auxiliary winding 610 and resistive divider 612, 614 that are the same as the corresponding components of Figure 5 .
  • the controller 608 includes an integrator 630, which is configured to provide an I emulate signal 632 that is representative of the magnetization current in the transformer.
  • the I emulate signal 632 may be considered as an "emulation" of the magnetization current.
  • the I emulate signal has the same shape as the current in the "magnetizing inductance" of the transformer.
  • the I emulate signal does not necessarily have the same magnitude as the current in the "magnetizing inductance".
  • the current in the magnetizing inductance is the sum of the currents in all of the individual windings scaled by the turns ratio.
  • the determination of the I emulate signal 632 can be performed in either the voltage domain, current domain, or digital domain, depending upon the implementation that is chosen.
  • An advantage to using the current domain is that negative voltages at an FB input pin of an associated IC can be prevented, or at least the likelihood of negative voltages at the pin can be reduced. Negative voltages can be undesirable for most integrated circuit (IC) processes, as special constructions may be necessary to account for negative voltages.
  • the emulated current (I emulate 632) can be set to an actual value at a "moment in time" when the integrator output 632 is known, thereby regulating the integrator 630. It is known that after the end of the secondary stroke, the voltage across the magnetizing inductance resonates due to the LC circuit provided in combination with the parasitic capacitance at the drain node of the MOSFET switch, thereby causing energy to resonate between the magnetizing inductance and the parasitic capacitance. At the valleys or tops of the resonating voltage, the current in the magnetizing inductance is zero, and therefore the integrator 530 can be reset to zero at the valleys or tops. Therefore, a "valley" or “top” is an example of a "moment in time” that is suitable for resetting the integrator 530.
  • the "valleys" and “tops” can be considered as moments when the rate of change of the voltage with respect to time (dV/dt) at a switching node (for example the drain node of the primary MOSFET, or the voltage at the auxiliary winding 610) is zero.
  • This so called 'valley' or 'top' can be detected by a circuit called a "valley detector” as is well known in the art, for example as provided by the TEA1507 GreenChipTM II SMPS control IC as manufactured by NXP.
  • a signal that can be received from a valley detector is illustrated by the "valley,top” signal 622 in Figure 6 .
  • An "end of sec. stroke” signal 624 is shown in Figure 6 , and this signal 624 is set high upon the determination of the end of the secondary stroke.
  • the "end of sec. stroke” signal 624 can be provided by a comparator or any circuit known in the art that can identify the end of the secondary stroke.
  • a logical OR gate 642 is provided, with its inputs provided by the "end of sec. stroke” signal 624 and the valley,top signal 622.
  • the output of the OR gate 642 is provided as an input to a pulse generator 644, the output signal 646 of which is connected to a reset pin of the integrator 630.
  • this example of resetting the integrator 630 enables a DC level of the integrator 630 to be set and controlled, thereby providing the integrator 630 with the functionality to account for any non-ideal components that occur in practical circuits.
  • Figure 7 graphically illustrates current and voltage values at nodes in the circuit of Figure 5 , with time passing from left to right.
  • the first signal 702 that is shown in Figure 7 is the voltage at the drain of the FET 504 in Figure 5 .
  • the second signal 704 is the voltage at the source of the FET 504.
  • the third signal 706 is the emulated voltage (V emu ) and represents the voltage that corresponds to the emulated magnetization current (I emulate 632) that is shown in Figure 6 .
  • the fourth signal 708 of Figure 7 is labelled Vs2, and is configured such that it goes high when the gate voltage of the FET 504 goes high.
  • the Vs2 signal 708 is configured to go low when the peak of the emulator voltage is reached. In one embodiment, this can be implemented with a comparator that detects when the drain voltage goes through the Vin level (see the first signal 702 of Figure 7 ), and in another embodiment when the voltage across an auxiliary winding crosses 0 V.
  • the fifth signal 710 is the voltage at the gate of the FET 504.
  • the secondary stroke (Tsec) of the operation of the circuit of Figure 5 is shown in Figure 7 with reference 712 and occurs between S2 and S3. Also shown in Figure 7 are times S1 and S2, whereby S1 represents the time at which the gate of the FET 504 is turned off, and S2 represents the time at which the peak of the magnetization current occurs.
  • the primary stroke can be considered as occurring between 0 and S2 or between 0 and S1.
  • the emulated voltage (Vemu) has a value of "A" at time S1 and a value of "B" at time S2. "A" and "B” can be used to compensate for errors in determining the peak magnetization according to some of the embodiments disclosed herein.
  • the threshold at which the circuit switches off the power switch (the peak current setpoint or Vsource,setpoint) can be reduced to take into account the difference between the peak current value through the FET 504 and the peak magnetization current. This overshoot 312 in the current is shown in Figure 3 .
  • FIG 8 illustrates schematically an embodiment of the invention for reducing the threshold at which the circuit switches off the power switch.
  • the original value of the threshold at which the circuit switches off the power switch is shown schematically as Vsource,setpoint 802 in Figure 8 .
  • the objective of this embodiment is to correct/adjust the value of Vsource,setpoint 802 so that it can be compared with the voltage at the source of the FET (Vsource 808) and better control the operation of the FET with a GateOff signal 806.
  • the corrected/adjusted value is shown as Vsource, setpoint,corrected 804 in Figure 8 .
  • Vsource does not accurately reflect the peak value of the current through the FET, as discussed above, and therefore this inaccuracy in Vsource can be accounted for by comparing Vsource with the signal Vsource, setpoint,corrected 804.
  • the Vsource,setpoint signal 802 is provided to a multiplier 812, where it is multiplied by "A/B".
  • the output of the multiplier 812 is the adjusted Vsource,setpoint,corrected signal 804.
  • the Vsource,setpoint,corrected signal 804 is provided as an input to a comparator 810, along with the Vsource signal 808, and the output of the comparator 810 is used to control the gate of the FET with the GateOff signal 806.
  • the values for "A” and “B” that are used by the multiplier 812 are sampled from the emulated voltage signal (Vemu 814) from the previous cycle of operation through timely operation of switches 816, 818.
  • a first switch 816 is operated by a Vgate signal to sample Vemu 814 when the gate of the FET goes low in order to provide the value of "A” for the multiplier 812. This corresponds to the value of "A” shown at time S1 in Figure 7 .
  • a second switch 818 is operated by a Vs2 signal in order to provide the value of "B” for the multiplier 812, and this corresponds to the value of "B” shown at time S2 in Figure 7 .
  • This embodiment of the invention can reduce the target value for the voltage at the source of the FET (Vsource,setpoint) such that it is suitable for comparing with the measured value for the voltage at the source of the FET, and take into account an expected overshoot in the magnetization current compared with the current through the FET based on the measured operation of a previous cycle of operation.
  • Vsource,setpoint value can be used to calculate the average output current using the following equation, whereby the non-corrected version of the Vsource,setpoint signal (as opposed to the Vsource,setpoint,corrected signal that is actually used to control operation of the FET) provides a more accurate reflection of the maximum voltage than is achievable with the prior art.
  • I out_av V source_setpoint R sense ⁇ N p N s ⁇ T sec 2 ⁇ T period
  • this embodiment there is no compensation of the delay of comparator 810, the delay of the driver is compensated, and the error of the multiplier 812 is the error that will be present in the calculated average output current. Also this embodiment of the invention only works for a peak current controlled system.
  • This embodiment can also be provided by using the emulated voltage/current and performing the required mathematics using digital operations.
  • integration may be necessary. This can be implemented by internal capacitors, an external capacitor or a digital integrator, as non-limiting examples.
  • the control algorithm will regulate the Vsource,setpoint parameter in order to set the following expression to be equal to zero: ⁇ 0 T period ⁇ I out_av dt - N p 2 ⁇ N s ⁇ R sense ⁇ ⁇ S ⁇ 2 S ⁇ 3 ⁇ V source_setpoint dt
  • the lout_av value in this equation is the desired value, and is constant.
  • the recorded value of the voltage at the source of the FET can be increased to take into account the overshoot/error between the peak current value through the FET 504 and the peak magnetization current. In this way, an adjusted value of the voltage at the source of the FET can be compared with the (unadjusted) setpoint value to improve the accuracy of operation.
  • Figure 9 illustrates schematically an embodiment of the invention for increasing the recorded voltage at the source of the FET (Vsource 902).
  • This embodiment can be used with both peak current control and voltage mode control (on-time control) of the circuit.
  • the increased values for the voltage at the source (Vsource,real 904) can be directly compared with an unmodified value for the threshold at which the circuit switches off the power switch (the peak current setpoint or Vsource,setpoint).
  • Vsource signal 902 is sampled when the gate signal goes low by operation of switch 906, which is at time S1 in Figure 7 .
  • This sampled value of Vsource is labelled Vsource,sample 908 in Figure 9 and is provided as an input to a multiplier 910.
  • the other inputs for the multiplier 910, namely "A" and "B” are sampled in the same way as for Figure 8 .
  • the multiplier is configured to multiply the Vsource,sample signal 908 by "B/A" in order to provide the increased value of the voltage at the source of the FET when the gate goes low, and this signal is labelled Vsource,real 904 in Figure 9 .
  • the error of the multiplier 910 is the error that will be present in the calculated average output current.
  • this embodiment can also be provided by using the emulated voltage/current and performing the required mathematics using digital operations.
  • integration may be necessary. This can be implemented by internal capacitors, an external capacitor or a digital integrator.
  • the control algorithm will regulate the maximum Vsource value (current mode control) or the on-time (voltage mode control) parameters in order to set the following expression to be equal to zero: ⁇ 0 T period ⁇ I out_av dt - N p 2 ⁇ N s ⁇ R sense ⁇ ⁇ S ⁇ 2 S ⁇ 3 V source_real dt
  • the lout_av value in this equation is the desired value and is constant.
  • a scaling factor (D) can be applied to the emulated voltage such that it can be used to directly record the peak value for the magnetization current, and hence can be used to accurately determine the average output current.
  • FIG 10 illustrates schematically an embodiment of the invention for adjusting the amplitude of the emulated voltage signal Vemu 1002 to a modified emulated signal VemuM 1004 that can be used in calculations to accurately determine the average output current.
  • This embodiment updates a scaling factor "D" 1006 that is applied to the emulated voltage Vemu 1002 whilst the voltage (Vgate) at the gate of the FET is low and a Vs2NOT signal is high.
  • the Vs2 signal is described above in relation to Figure 7 , and it will be appreciated the Vs2NOT signal is the inverse of the Vs2 signal. In this way, the scaling factor is adjusted such that that the modified signal VemuM 1004 is brought into line with the voltage at the source of the FET (Vsource 1012).
  • the scaling factor is fixed. In this way, the emulated voltage signal Vemu 1002 continues to rise after the voltage at the source Vsource drops to zero, and is scaled by a value such that it is representative of the magnetization current in the transformer of a flyback converter.
  • the emulated voltage signal Vemu 1002 is provided as an input to a multiplier 1008.
  • the emulated voltage signal Vemu 1002 is multiplied by "D" (discussed below) in order to provide the modified emulated voltage signal VemuM 1004.
  • the difference between VemuM 1002 and Vsource 1012 is stored at capacitor 1020.
  • the stored difference voltage can be supplied to the inverting input of amplifier 1010. When the difference is positive the value of D will decrease. When the difference is negative the value of D will increase.
  • the amplifier 1010 has a capacitor 1030 connected between its output and inverting input in order to provide an integrator.
  • a first switch 1014 is provided between the output of the multiplier that provides the VemuM signal 1004 and a first plate of capacitor 1020.
  • the first switch 1014 is operated in accordance with the Vgate signal (see Figure 7 ).
  • a second switch 1016 is connected between Vsource 1012 and a second plate of the capacitor 1020.
  • the second switch 1020 is also driven by the Vgate signal. Sampling of the voltage difference between VemuM and Vsource across the capacitor 1020 occurs when Vgate is high. When the gate is turned off and Vgate switches from high to low, the signal has been sampled.
  • a third switch 1018 is connected in series between the first plate of the capacitor and the inverting input of the amplifier 1010.
  • the third switch is controlled by a Vs2NOT signal.
  • a fourth switch 1022 is connected between the second plate of the capacitor 1020 and ground. When the Vs2NOT signal goes high, the second input of capacitor 1020 is connected to ground via fourth switch 1022 and the first input of capacitor 1020 is connected to the inverting input of amplifier 1010 by the third switch 1018.
  • the difference charge (caused by the difference of VemuM and Vsource) is dumped in capacitor 1030, which results in a change of signal D 1006.
  • the non-inverting input of the amplifier is coupled to ground.
  • the circuit of Figure 10 can therefore store the difference between VemuM and Vsource on capacitor 1020 when Vgate is high.
  • Vgate When Vgate is set low the sampled value will be retained by the capacitor. This sampled value is used to update the amplifier 1010.
  • the integrator When the first 1014 and second 1016 switches are open (Vgate is low) and the third 1018 and fourth 1022 switches are closed (Vs2Not is high), the integrator is updated and therefore the output signal D 1006 of the integrator is updated.
  • the third switch 1018 is open signal D 1006 is kept constant.
  • the scaling factor (D) is updated once for every switching cycle.
  • the switching cycle may not require updating very often as it is unlikely to significantly change between operating cycles of the circuit.
  • the required D value can change slowly when the temperature changes. Therefore, embodiments of the invention can update the gain (D 1006) once per mains cycle, for example by sampling the difference between Vemu 1004 and Vsource 1012 signals using switches that are controlled by signals derived from a mains input.
  • the output of the Amplifier 1010 is the signal labeled "D" 1006 and is provided to the multiplier 1008 so that the modified emulated voltage signal VemuM 1004 is brought closer to the Vsource signal 1012 during the primary stroke of the circuit.
  • the amplitude of VemuM 1004 is adjusted by a control loop such that VemuM 1004 is made equal to Vsource 1012 during the primary stroke.
  • the peak value of the emulated magnetization current can then be used as the real Ipeak. This is independent of peak current mode control or voltage mode control (on-time control).
  • the gain of the emulator function is changed such that the emulator current follows the source current during the primary stroke.
  • integration may be necessary. This can be implemented by internal capacitors, an external capacitor or a digital integrator.
  • the control algorithm will regulate the maximum Vsource value (current mode control) or the on-time (voltage mode control) parameter in order to set the following expression to be equal to zero: ⁇ 0 T period ⁇ I out_av dt - N p 2 ⁇ N s ⁇ R sense ⁇ ⁇ S ⁇ 2 S ⁇ 3 V emuM_max dt
  • the period of time between S2 and S3 represents the secondary stroke, as illustrated in Figure 7 .
  • the lout_av value in this equation is the desired value and is constant.
  • the emulator voltage is integrated during the secondary stroke in order to determine lout_av. This is in contrast to embodiment 3 whereby lout_av is calculated as a function of Tsec and Ipeak.
  • the period of time between S2 and S3 represents the secondary stroke, as illustrated in Figure 7 .
  • This equation applies for both peak current mode control and voltage mode control (on-time control).
  • integration may be necessary. This can be implemented by internal capacitors, an external capacitor or a digital integrator.
  • the control algorithm will regulate the following equation to 0 by changing the maximum Vsource value (current mode control) or the on-time (voltage mode control): ⁇ 0 T period ⁇ I out_av dt - N p 2 ⁇ N s ⁇ R sense ⁇ ⁇ S ⁇ 2 S ⁇ 3 V emuM t dt
  • the lout_av value in this equation is the desired value and is constant.
  • a principle that can be applied by embodiments 3 and 4 is to adapt the gain of the emulator in such a way that during the primary stroke the emulator voltage is equal to the source voltage, and therefore the emulated magnetization current is made equal to the actual magnetization current.
  • Vsource 1012 and VemuM 1004 are sampled at the moment the gate of the FET goes low. These sampled values are compared with each other, and if they are not the same, then the gain of the emulator is adjusted.
  • Adjusting the gain of the emulator can also be implemented in a digital way. For example, when the emulator voltage is too low, the gain is increased by one step/increment. When the emulator voltage is too high, the gain is decreased by one step/increment. Alternatively, the gain can be adjusted when it is not within a range of values, for example by use of a window comparator.
  • Figure 11 illustrates an embodiment whereby an up/down counter 1120 is used to incrementally adjust the scaling factor D 1106 that is applied to the Vemu signal 1102 by the multiplier 1108.
  • the up/down counter 1120 is clocked by the Vgate signal 1122 so that the gain (D 1106) that is applied to the emulated voltage signal Vemu 1120 is only adjusted at a falling edge of the Vgate signal 1122, that is, once every switching cycle.
  • the up/down counter 1120 can be clocked once every mains cycle instead of once every switching cycle.
  • Input is supplied to the up/down counter 1120 from a comparator 1110 output.
  • the comparator 1110 compares the VemuM signal 1104, supplied to its inverting input, with a Vsource signal 1112, supplied to its non-inverting input.
  • the Vsource signal 1112 and VemuM signal 1104 in this example are analogous to the Vsource signal 1012 and VemuM signal 1004 in Figure 10 .
  • the comparator provides a positive output to the up/down counter 1120 if Vsource 1112 is greater than VemuM 1104 and a negative output if Vsource 1112 is less than VemuM 1104.
  • the polarity of the output determines whether the count is increased or decreased.
  • the comparator 1110 output in this example is processed at a specific moment in time, related to a logic state of the system. The falling edge of Vgate can be used as a signal for comparison to occur, or the result of the comparison to be used.
  • Figure 11 provides just one of numerous potential digital implementations for providing an emulator with a gain that is updated in accordance with an embodiment of the invention.
  • a principle that is applied by such embodiments is to adjust the gain of the emulator by comparing the primary current with the emulator output, and this can include a comparison between the filtered or integrated source voltage and the filtered of integrated emulator voltage.
  • the average output current can be controlled in any way that is known in the art, and include methods that are implemented in the TEA1401 integrated circuit (with an external capacitor). Any specific method of controlling the average output current is outside the scope of this disclosure.
  • Embodiments disclosed herein use an emulator, which can use analogue or digital integration.
  • the input of the emulator can be generated by a winding or by a dc-decoupled measurement of the drain voltage of the primary MOSFET.
  • an extra winding on the coil can be undesirable.
  • Figure 12 illustrates an embodiment of the invention including a Buck converter.
  • a Buck converter With a Buck converter the load is connected to the high voltage, and therefore the load current high side should not be measured. Therefore, the peak current at the low side is measured.
  • SOPS Self Oscillating Power Supply
  • the output current is almost equal to the peak current divided by two.
  • a similar method as described for the Flyback converter can be used.
  • Figure 13 illustrates example signals in the Buck converter circuit of Figure 12 , and the signals that are shown in Figure 13 are similar to those described above with reference to Figure 7 . Shown in Figure 13 is a period of time labeled Tint, which represents the primary and secondary strokes, but not any ringing that occurs after the end of the secondary stroke.
  • Tint a period of time labeled Tint
  • the methods of embodiments 1 to 3 above can be difficult to implement as the ringing in the output current is not taken into account.
  • the ringing current in a Buck converter flows through the load.
  • An approximation can be made by replacing Tsec with Tint in the equations for calculating lout_av.
  • the regulation algorithm for Flyback converters includes an integration that is started at S2, but for a Buck converter, this integration has to start at 0. In the Buck converter case, we always need to use the sample for Ipeak, A and B from a previous cycle. However, as indicated above, for some embodiments that use a Flyback converter, samples from a current cycle can be used as integration is not started until after Ipeak, A and B are recorded from a present cycle.
  • Embodiment 4 can be considered as most suitable for a Buck converter, as the emulator signal is adjusted and continuously available.
  • I out_av 1 T period ⁇ ⁇ 0 T period
  • I out dt 1 T period ⁇ ⁇ 0 T period
  • integration may be necessary. This can be implemented by internal capacitors, an external capacitor or a digital integrator.
  • the control algorithm will regulate the following equation to 0 by changing the maximum Vsource value (current mode control) or the on-time (voltage mode control): ⁇ 0 T period I out_av ⁇ dt - 1 R sense ⁇ ⁇ 0 T period V emuM t ⁇ dt
  • the lout_av value in this equation is the desired value and is constant.
  • an auxiliary winding may not be required to provide the signal representative of the voltage across the inductive component that is integrated to obtain the emulated signal.
  • the signal representative of the voltage across the inductive component can be provided by any other suitable means.
  • a resistive divider 1402 in series with a blocking capacitor 1404 can be used to provide the signal to the FB pin of the controller, as shown in Figure 14 .
  • a capacitive divider 1502 with a resistor 1504 in parallel with the capacitor that is connected to ground can be used to provide the signal to the FB pin of the controller.
  • any known way of providing a signal that can be integrated in order to generate a signal representative of a magnetization current in the inductive component and can be used to determine the output current of the switching circuit can be used, and that an auxiliary winding is just one example of a component that can do this.
  • FIG 16 illustrates an integrator 1630 according to an embodiment of the invention that is configured to operate in the voltage domain, although it will be appreciated that the integrator function can be realized in many ways.
  • the integrator 1630 receives an FB input 1615 from a resistive divider 1614, 1616 in the same way as discussed with reference to Figure 5 .
  • the voltage at the FB input pin 1615 is also available for sensing the output voltage.
  • the integrator 1630 includes an operational amplifier (opamp) 1636 with integrator function using a feedback capacitor Ci 1638 between the opamp output and the negative input of the opamp 1636.
  • the voltage to be integrated is first converted to a current by resistor R3 1634, and then integrated via the feedback capacitor Ci 1638.
  • an optional buffer 1632 can be provided between the FB input pin 1615 and the input to the opamp 1636. This may be required if the internal conversion resistor (R3 1634) is not large compared to the external divider (R1 1614 and R2 1616), which is typically the case as R1 1614 and R2 1616 are external resistors and R3 1634 is an internal resistor.
  • the buffer 1632 may not be needed for the integrator function because the output signal lemulate 1632 will be compared with a value of about zero - this means that the scaling factor of the integrator 1630 may not be important in determining the shape of the lemulate signal 1632, and it will still return to zero at about the same time even if the scaling is incorrect.
  • the optional buffer 1632 may be used to prevent, or reduce, a voltage division error.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
EP11250488.1A 2011-04-20 2011-04-20 Schaltkreis Active EP2515426B1 (de)

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US13/449,903 US9036375B2 (en) 2011-04-20 2012-04-18 Controller that determines average output current of a switching circuit

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US9036375B2 (en) 2015-05-19
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US20130100711A1 (en) 2013-04-25
CN102751877B (zh) 2015-12-09

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