EP2504910A1 - Switching mode power supply comprising asynchronous limiter circuit - Google Patents

Switching mode power supply comprising asynchronous limiter circuit

Info

Publication number
EP2504910A1
EP2504910A1 EP10782264A EP10782264A EP2504910A1 EP 2504910 A1 EP2504910 A1 EP 2504910A1 EP 10782264 A EP10782264 A EP 10782264A EP 10782264 A EP10782264 A EP 10782264A EP 2504910 A1 EP2504910 A1 EP 2504910A1
Authority
EP
European Patent Office
Prior art keywords
transistor
drain
source
power transistor
mos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP10782264A
Other languages
German (de)
French (fr)
Other versions
EP2504910B1 (en
Inventor
Laurent Chevalier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ST Ericsson SA
STMicroelectronics Alps SAS
Original Assignee
ST Ericsson SA
ST Ericsson Grenoble SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ST Ericsson SA, ST Ericsson Grenoble SAS filed Critical ST Ericsson SA
Publication of EP2504910A1 publication Critical patent/EP2504910A1/en
Application granted granted Critical
Publication of EP2504910B1 publication Critical patent/EP2504910B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H02M1/34—Snubber circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H02M1/34—Snubber circuits
    • H02M1/344—Active dissipative snubbers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/0812—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
    • H03K17/08122—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type

Definitions

  • the present invention relates to switching mode power supply devices wherein at least a portion of the control circuit of which is embodied on an integrated circuit.
  • Integrated circuits are usually in the form of rectangular casings equipped on one or several sides or on one of their surfaces, with pins which make it possible to establish electrical connections with a circuit that is external to the casing, for example a power source or a load circuit.
  • the casing encloses a silicon chip comprising integrated components such as for example transistors or diodes. These integrated components are connected to their external environment via an assembly of connections, such as metallic tracks or connecting wires of all kinds.
  • connecting member is used to designate the assembly of connections that ensure the electric connection between an input and/or output of an integrated component of the chip and a circuit or component external to the casing.
  • This connecting member comprises the connection between the input and/or output of the integrated component and the corresponding connecting pad on the silicon chip, the connection between the connecting pad and the corresponding pin of the casing and the connection between the casing pin and the circuit or external component.
  • a connecting member may be modelized as an inductance L p mounted in series with a resistance R p as shown in fig.l.
  • the inductance value L is of the order of a few nanohenries (nH) and the resistance value R is of around a hundred milliohms (mQ) .
  • the connecting member thus serves as a direct current source when the voltage at its terminals varies.
  • This switching mode power supply comprises a p- channel MOS power transistor, referenced PI, series- mounted with an n-channel MOS power transistor, referenced Nl, between a positive supply terminal VDD and a negative supply terminal GND of an external supply circuit.
  • Power transistors PI and Nl are made on the silicon chip of an integrated circuit CI. They are connected to the terminals VDD and GND via connecting members modeled as a parasitic inductance in series with a parasitic resistance. More particularly, the source of the transistor PI is connected to the terminal VDD via a connecting member CN1 and the source of transistor Nl is connected to the terminal GND via a connecting member CN2.
  • transistors PI and Nl are connected to a first end of an external inductance L via a connecting member CN3, the other end of the inductance L being connected to an external load circuit comprising a load resistance R L parallel-mounted with a load capacitor C L .
  • transistors PI and Nl operate in switching mode to generate a voltage VS at the load circuit terminals, which voltage VS is lower than voltage VDD.
  • Transistors PI and Nl are controlled by substantially identical control signals.
  • the power transistors PI and Nl have their source and drain connected to connecting members. These connecting members create overvoltages at transistors PI and Nl when they are switching, as illustrated in figs. 3 and 4.
  • Fig.3 shows two curves:
  • a first curve represents the voltage, referenced VS p i, on the source of transistor PI
  • a second curve represents the voltage, referenced VSNI, on the source of transistor Nl .
  • Fig.4 shows a curve representing the voltage, referenced VD p i, on the drain of the transistor PI and transistor Nl .
  • voltage instabilities VS P i, VS N i and VD P i appear during the switching of transistors PI and Nl .
  • These instabilities are particularly due to parasitic inductances and resistances of the connecting members which serve as sources of direct current at the instant the transistors Nl and PI switch.
  • These instabilities thus create overvoltages between the drain and the source of transistors PI and Nl, leading to their weakening. As illustrated in figs. 3 and 4, these overvoltages can reach 9 volts for transistor PI during its switching from the on-state to off-state.
  • Another solution consists in replacing each power transistor PI and Nl by a plurality of parallel-mounted power transistors, for example a small transistor, an average transistor and a transistor of larger size, and to switch them one after the other by starting by the smallest transistor and ending by the largest one, such as to gradually make the current crossing the parasitic inductance of the connecting members vary.
  • a plurality of parallel-mounted power transistors for example a small transistor, an average transistor and a transistor of larger size
  • An object of the present invention is to propose another solution without the aforementioned drawbacks.
  • a reduction in the current variation of the connecting members is proposed, when the device power transistors switch in order to maintain the drain-source voltage of the power transistors below a predetermined threshold value when they switch.
  • the object of the invention is a switching mode power supply device, such as a buck-type DC-DC voltage converter or a charge pump, comprising at least one MOS power transistor made on an integrated circuit and operating in switching mode, the drain and the source of said MOS power transistor being connected, via connecting members having a non-null inductance, to one or several external circuits to said integrated circuit, characterized in that it further comprises a limiter circuit able to limit the current variations in at least one of said connecting members during the switching of said MOS power transistor.
  • a switching mode power supply device such as a buck-type DC-DC voltage converter or a charge pump
  • the limiter circuit is mounted between the drain and the source of the MOS power transistor.
  • the limiter circuit is only active during the switching of the power transistor.
  • the power transistor is a p-channel transistor and the limiter circuit comprises:
  • a resistance series mounted with a capacitor between the source and the drain of the power transistor, the source of the power transistor being connected to a first terminal of the resistance and the drain of the power transistor being connected to a first terminal of the capacitor, at least one p-channel MOS transistor having its gate connected to an intermediate point between said resistance and said capacitor, its drain connected to the drain of the MOS power transistor and its source connected to the source of the MOS power transistor.
  • this limiter circuit advantageously further comprises a second p-channel MOS transistor mounted between the drain of said first transistor and the drain of the power transistor, the source of said second transistor being connected to the drain of the first transistor and the drain and gate of said second transistor being connected to the drain of the MOS power transistor.
  • the power transistor is an n-channel transistor and the limiter circuit comprises:
  • a resistance mounted in series with a capacitor between the source and drain of the power transistor, the source of the power transistor being connected to a first terminal of the resistance and the drain of the power transistor being connected to a first terminal of the capacitor,
  • At least one first n-channel MOS transistor having its gate connected to an intermediate point between said resistance and said capacitor, its drain connected to the drain of the MOS power transistor and its source connected to the source of the MOS power transistor.
  • the limiter circuit advantageously further comprises a second n-channel MOS transistor mounted between the drain of the first transistor and the drain of the power transistor, the source of said second transistor being connected to the drain of the first transistor and the drain and the gate of said second transistor being connected to the drain of the MOS power transistor.
  • the present invention also relates to a portable equipment comprising a switching mode power supply device such as defined previously.
  • Fig.5 the electric diagram of a buck-type switching mode power supply in accordance with the invention ;
  • Fig.10 curves representing the voltage of the drain and the voltage of the gate of a power transistor of the charge pump of fig.9;
  • Fig.11 curves representing the currents circulating through transistors of the charge pump of fig.9.
  • the invention is described for two types of switching mode power supplies: a buck-type DC/DC voltage converter and a negative charge pump circuit.
  • switching mode power supplies comprising at least one power transistor operating in switching mode and having its drain and its source connected to connecting members comprising a non- null parasitic inductance.
  • Fig.4 represents the electric diagram of a buck-type DC/DC voltage converter in accordance with the invention. With respect to the converter illustrated in fig.2, it further comprises a limiter circuit able to limit the current variations in the connecting members CN1, CN2 and CN3 during the switching of transistors PI and Nl .
  • This circuit is mounted between the drain and the source of the transistor PI and enables to maintain the drain- source voltage of transistor PI below a threshold value during the switching of transistors PI and Nl .
  • This limiter circuit comprises two p-channel MOS transistors, referenced P2 and P3, mounted in series between the source and the drain of transistor PI.
  • the source and the drain of the transistor P2 are connected respectively to the source of transistor PI and to the source of transistor P3.
  • the drain and gate of transistor P3 are connected to the drain of transistor PI.
  • a resistance Rl is series-mounted with a capacitor CI between the source and the drain of transistor PI.
  • the resistance Rl is mounted between the source and the gate of transistor P2 and the capacitor CI is mounted between the gate of transistor P2 and the drain of transistor P3.
  • Fig.7 shows the currents, referenced I P i, I N i and I P2 , flowing respectively through transistors PI, Nl and P2.
  • Fig.8 to be compared to figs. 3 and 4, represents the voltages VS P i, VS N i and VD P i in the circuit of fig.5.
  • transistor PI is switched before the transistor Nl in order to prevent a short-circuit current between VDD and GND at the instant the transistor Nl starts conducting.
  • transistor PI gradually opens (gate voltage VG p i increases)
  • the gate voltage VG P 2 of transistor P2 decreases.
  • the latter provides the current I p2 to inductance L and to the load circuit during the switching of transistors PI and Nl .
  • the presence of such a current makes it possible to prevent the discontinuities or the too rapid variations of current flowing through the connecting members CN1, CN2 and CN3 of the circuit, thus, leading to limiting the overvoltages at the drain source voltage of power transistors PI and Nl .
  • this circuit arrangement enables to maintain the drain source voltage of transistors PI and Nl below 6 volts.
  • the reaction time of the limiter circuit can be adjusted by acting on the values of resistance Rl and capacitor CI.
  • the limiter circuit advantageously comprises two series-mounted MOS transistors as in the present case, in order to spread over these two transistors the drain-source voltage of transistor PI and to increase the robustness of the limiter circuit.
  • Fig.9 represents the electric diagram of a negative charge pump in accordance with the invention.
  • the charge pump comprises a first stage for charging a capacitor CF with a first charge voltage Vdd and a second stage for, after disconnection of the first stage, providing the inverse voltage -Vdd to a load circuit.
  • Both stages are constituted of MOS power transistors made on an integrated circuit CI'.
  • the capacitor CF and the load circuit are external to the integrated circuit CI'.
  • the transistors of the integrated circuit are connected, via connecting members, to external supply terminals VDD and GND, able to provide the charge voltage vdd .
  • the first stage comprises a p-channel MOS power transistor, referenced P10, having its source connected to the supply terminal VDD via a connecting member CN10 and its drain connected to a first terminal of the external capacitor CF via a connecting member CN11.
  • the first stage also comprises an n-channel MOS power transistor, referenced N10, having its source connected to the supply terminal GND via a connecting member CN12 and its drain connected to a second terminal of the external capacitor CF via a connecting member CN13.
  • the second stage comprises an n-channel MOS power transistor, referenced Nil, having its drain connected to the drain of the transistor P10 and its source connected to the supply terminal GND via the connecting member CN12 or another connecting member.
  • the second stage also comprises an n-channel MOS power transistor, referenced N12, having its drain connected to the drain of the transistor N10 and its source connected to the external load circuit via a connecting member CN14.
  • the load circuit is modeled by a storage capacitor C L' mounted parallel to a load resistance R L' .
  • this charge pump is completed by a limiter circuit able to limit the current variations within the connecting members when the transistor Nil switches.
  • This limiter circuit is mounted between the drain and the source of transistor Nil and enables to maintain the drain-source voltage of the transistor Nil below a threshold value when it changes states .
  • This limiter circuit comprises two n-channel MOS transistors N13 and N14, mounted in series between the source and the drain of the transistor Nil.
  • the source and the drain of transistor N13 are connected respectively to the source of transistor Nil and to the source of the transistor N14.
  • the drain and gate of transistor N14 are connected to the drain of transistor Nil.
  • a resistance R2 is mounted in series with a capacitor C2 between the source and the drain of transistor Nil.
  • the resistance R2 is mounted between the source and the gate of transistor N13 and the capacitor C2 is mounted between the gate of transistor N13 and the drain of transistor N14.
  • Fig.10 represents the voltage, referenced VD N n, on the drain of the transistor Nil and the voltage, referenced VS N n, on the source of the transistor Nil.
  • Fig.11 represents the currents, referenced INI I , INI 2 and INI3, flowing respectively through the transistors Nil, N12 and N13.
  • the limiter circuit enables to limit the overvoltages between the drain and the source of the power transistor Nil at the instant it stops conducting (switching to the off-state) of the transistors Nil and N12.
  • the current I N i 3 pass through the transistors N13 and N14. The result is that the current variations in the connecting members CN11 and CN12 are reduced during this phase.
  • the limiter circuit is completely asynchronous with respect to the rest of the control circuit of the switching mode power supply and is triggered autonomously. Furthermore, it is only triggered off during switching of the power transistors. Thus, it is only active during these switching phases. In addition, when it is active, there is no current loss as the current crossing it is supplied to the load circuit.
  • Such a limiter circuit may be set-up in all types of switching mode power supplies comprising power transistors operating in switching mode and is advantageously mounted between the drain and the source of the power transistor undergoing the strongest overvoltages during switching. If the switching mode power supply comprises several power transistors undergoing strong overvoltages, it is possible to provide a limiter circuit for each one of them.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention relates to a switching mode power supply device comprising at least one MOS power transistor (P1;N11) made on an integrated circuit (CI; CI') and operating in switching mode, the drain and the source of said at least one MOS power transistor being connected, via connecting members (CN1, CN3; CN11, CN12) having a non-null inductance, to one or several external circuits to said integrated circuit. According to the invention, the device further comprises a limiter circuit (R1, C1, P2, P3) able to limit the current variations in at least one of said connecting members during the switching of said MOS power transistor. This limiter circuit (R1, C1, P2, P3) enables to maintain the drain -source voltage of the MOS power transistor below a predetermined threshold value when it commutes.

Description

SWITCHING MODE POWER SUPPLY COMPRI SING ASYNCHRONOUS LIMITER CIRCUIT
The present invention relates to switching mode power supply devices wherein at least a portion of the control circuit of which is embodied on an integrated circuit.
Integrated circuits are usually in the form of rectangular casings equipped on one or several sides or on one of their surfaces, with pins which make it possible to establish electrical connections with a circuit that is external to the casing, for example a power source or a load circuit. The casing encloses a silicon chip comprising integrated components such as for example transistors or diodes. These integrated components are connected to their external environment via an assembly of connections, such as metallic tracks or connecting wires of all kinds.
In what follows, the term "connecting member" is used to designate the assembly of connections that ensure the electric connection between an input and/or output of an integrated component of the chip and a circuit or component external to the casing. This connecting member comprises the connection between the input and/or output of the integrated component and the corresponding connecting pad on the silicon chip, the connection between the connecting pad and the corresponding pin of the casing and the connection between the casing pin and the circuit or external component.
A connecting member may be modelized as an inductance Lp mounted in series with a resistance Rp as shown in fig.l. The inductance value L is of the order of a few nanohenries (nH) and the resistance value R is of around a hundred milliohms (mQ) . The connecting member thus serves as a direct current source when the voltage at its terminals varies.
Within the framework of switching mode power supplies having a control circuit embodied by an integrated circuit, the presence of such connecting members creates overvoltages at the drain-source voltage and the gate-source voltage of the MOS transistors of the supply control circuit, thus leading to weakening these transistors and rendering them less reliable.
This issue will be shown hereafter in the framework of a DC/DC buck-type switching mode power supply the electric diagram of which is represented on fig.2.
This switching mode power supply comprises a p- channel MOS power transistor, referenced PI, series- mounted with an n-channel MOS power transistor, referenced Nl, between a positive supply terminal VDD and a negative supply terminal GND of an external supply circuit. Power transistors PI and Nl are made on the silicon chip of an integrated circuit CI. They are connected to the terminals VDD and GND via connecting members modeled as a parasitic inductance in series with a parasitic resistance. More particularly, the source of the transistor PI is connected to the terminal VDD via a connecting member CN1 and the source of transistor Nl is connected to the terminal GND via a connecting member CN2. The drains of transistors PI and Nl, connected together, are connected to a first end of an external inductance L via a connecting member CN3, the other end of the inductance L being connected to an external load circuit comprising a load resistance RL parallel-mounted with a load capacitor CL. When in operation, transistors PI and Nl operate in switching mode to generate a voltage VS at the load circuit terminals, which voltage VS is lower than voltage VDD. Transistors PI and Nl are controlled by substantially identical control signals. It is worth noting that however, in order to prevent a short-circuit current between VDD and GND at the instant the transistor starts conducting Nl (switching to the on-state) , the opening of the transistor PI (switching to the off-state) is slightly controlled before the closing of transistor Nl (switching to the on-state) .
As can be seen on fig.2, the power transistors PI and Nl have their source and drain connected to connecting members. These connecting members create overvoltages at transistors PI and Nl when they are switching, as illustrated in figs. 3 and 4.
Fig.3 shows two curves:
- a first curve represents the voltage, referenced VSpi, on the source of transistor PI, and
a second curve represents the voltage, referenced VSNI, on the source of transistor Nl .
Fig.4 shows a curve representing the voltage, referenced VDpi, on the drain of the transistor PI and transistor Nl .
As can be seen on these figures, voltage instabilities VSPi, VSNi and VDPi appear during the switching of transistors PI and Nl . These instabilities are particularly due to parasitic inductances and resistances of the connecting members which serve as sources of direct current at the instant the transistors Nl and PI switch. These instabilities thus create overvoltages between the drain and the source of transistors PI and Nl, leading to their weakening. As illustrated in figs. 3 and 4, these overvoltages can reach 9 volts for transistor PI during its switching from the on-state to off-state.
There are solutions consisting in increasing the transition time of the power transistor PI, to reduce these over-voltages. One of these solutions consists in decreasing the size of the control inverters (also called control buffers) of the power transistors PI and Nl such as to obtain longer transition times. This solution is nevertheless not really adapted for most current switching mode arrangements which use a high switching frequency. It also penalizes the transitional behavior of the device and the power Supply Rejection Ratio (PSRR) .
Another solution consists in replacing each power transistor PI and Nl by a plurality of parallel-mounted power transistors, for example a small transistor, an average transistor and a transistor of larger size, and to switch them one after the other by starting by the smallest transistor and ending by the largest one, such as to gradually make the current crossing the parasitic inductance of the connecting members vary.
In these two cases, the transition times must be extended significantly to have any effect on the over- voltages.
Summary of the invention
An object of the present invention is to propose another solution without the aforementioned drawbacks. According to the invention, a reduction in the current variation of the connecting members is proposed, when the device power transistors switch in order to maintain the drain-source voltage of the power transistors below a predetermined threshold value when they switch.
To this end, the object of the invention is a switching mode power supply device, such as a buck-type DC-DC voltage converter or a charge pump, comprising at least one MOS power transistor made on an integrated circuit and operating in switching mode, the drain and the source of said MOS power transistor being connected, via connecting members having a non-null inductance, to one or several external circuits to said integrated circuit, characterized in that it further comprises a limiter circuit able to limit the current variations in at least one of said connecting members during the switching of said MOS power transistor.
According to a specific embodiment, the limiter circuit is mounted between the drain and the source of the MOS power transistor. Advantageously, the limiter circuit is only active during the switching of the power transistor.
According to a specific embodiment, the power transistor is a p-channel transistor and the limiter circuit comprises:
a resistance series mounted with a capacitor between the source and the drain of the power transistor, the source of the power transistor being connected to a first terminal of the resistance and the drain of the power transistor being connected to a first terminal of the capacitor, at least one p-channel MOS transistor having its gate connected to an intermediate point between said resistance and said capacitor, its drain connected to the drain of the MOS power transistor and its source connected to the source of the MOS power transistor.
In this embodiment, this limiter circuit advantageously further comprises a second p-channel MOS transistor mounted between the drain of said first transistor and the drain of the power transistor, the source of said second transistor being connected to the drain of the first transistor and the drain and gate of said second transistor being connected to the drain of the MOS power transistor.
According to another specific embodiment, the power transistor is an n-channel transistor and the limiter circuit comprises:
a resistance mounted in series with a capacitor between the source and drain of the power transistor, the source of the power transistor being connected to a first terminal of the resistance and the drain of the power transistor being connected to a first terminal of the capacitor,
- at least one first n-channel MOS transistor having its gate connected to an intermediate point between said resistance and said capacitor, its drain connected to the drain of the MOS power transistor and its source connected to the source of the MOS power transistor.
In this embodiment, the limiter circuit advantageously further comprises a second n-channel MOS transistor mounted between the drain of the first transistor and the drain of the power transistor, the source of said second transistor being connected to the drain of the first transistor and the drain and the gate of said second transistor being connected to the drain of the MOS power transistor.
The present invention also relates to a portable equipment comprising a switching mode power supply device such as defined previously.
Brief description of the drawings The invention will be better understood and other objects, details, characteristics and advantages will become more apparent in the following detailed explanatory description, with reference above to the accompanying drawings, which represent:
- Fig.l, already described, the modelization diagram of a connecting member,
Fig.2, already described, the electric diagram of a buck-type DC/DC switching mode power supply of the prior art;
- Figs. 3 and 4, already described, curves representing the voltages of the drain and source of the power transistors of the switching mode power supply of fig .2 ;
Fig.5, the electric diagram of a buck-type switching mode power supply in accordance with the invention ;
Fig.6, curves representing the gate voltages of the transistors of the switching mode power supply of fig .5 ;
- Fig.7, curves representing the currents circulating through the transistors of the switching mode power supply of fig.5;
Fig.8, to compare with figs .3 and 4, curves representing the voltages of the drain and source of the transistors of the switching mode power supply of fig.5; Fig.9, the electric diagram of a negative charge pump in accordance with the invention;
Fig.10, curves representing the voltage of the drain and the voltage of the gate of a power transistor of the charge pump of fig.9; and
Fig.11, curves representing the currents circulating through transistors of the charge pump of fig.9. The invention is described for two types of switching mode power supplies: a buck-type DC/DC voltage converter and a negative charge pump circuit. Of course it can be applied to other types of switching mode power supplies comprising at least one power transistor operating in switching mode and having its drain and its source connected to connecting members comprising a non- null parasitic inductance.
Buck-type continuous voltage converter
Fig.4 represents the electric diagram of a buck-type DC/DC voltage converter in accordance with the invention. With respect to the converter illustrated in fig.2, it further comprises a limiter circuit able to limit the current variations in the connecting members CN1, CN2 and CN3 during the switching of transistors PI and Nl . This circuit is mounted between the drain and the source of the transistor PI and enables to maintain the drain- source voltage of transistor PI below a threshold value during the switching of transistors PI and Nl .
This limiter circuit comprises two p-channel MOS transistors, referenced P2 and P3, mounted in series between the source and the drain of transistor PI. The source and the drain of the transistor P2 are connected respectively to the source of transistor PI and to the source of transistor P3. The drain and gate of transistor P3 are connected to the drain of transistor PI. A resistance Rl is series-mounted with a capacitor CI between the source and the drain of transistor PI. The resistance Rl is mounted between the source and the gate of transistor P2 and the capacitor CI is mounted between the gate of transistor P2 and the drain of transistor P3.
The operating of the converter is illustrated by figs. 6, 7 and 8.
Fig .6 shows
- the voltage, referenced VGPi, of the gate of the transistor PI,
-the voltage, referenced VGNi, of the gate of transistor Nl, and
the voltage, referenced VGP2, of the gate of transistor P2. Fig.7 shows the currents, referenced IPi, INi and IP2, flowing respectively through transistors PI, Nl and P2.
Fig.8, to be compared to figs. 3 and 4, represents the voltages VSPi, VSNi and VDPi in the circuit of fig.5.
With reference to figs. 6 and 7, transistor PI is switched before the transistor Nl in order to prevent a short-circuit current between VDD and GND at the instant the transistor Nl starts conducting. As transistor PI gradually opens (gate voltage VGpi increases) , the gate voltage VGP2 of transistor P2 decreases. The latter provides the current Ip2 to inductance L and to the load circuit during the switching of transistors PI and Nl . The presence of such a current makes it possible to prevent the discontinuities or the too rapid variations of current flowing through the connecting members CN1, CN2 and CN3 of the circuit, thus, leading to limiting the overvoltages at the drain source voltage of power transistors PI and Nl . As illustrated in fig.8, this circuit arrangement enables to maintain the drain source voltage of transistors PI and Nl below 6 volts.
The reaction time of the limiter circuit can be adjusted by acting on the values of resistance Rl and capacitor CI. The higher the capacitance of capacitor CI, the earlier the transistor PI switches to the on-state in order to supply current to the inductance L and to the load circuit. The higher the resistance value Rl, the longer the transistor P2 continues to supply current to the inductance L and to the load circuit.
Moreover given that the overvoltages take place when the limiter circuit supplies the maximum of current, the latter advantageously comprises two series-mounted MOS transistors as in the present case, in order to spread over these two transistors the drain-source voltage of transistor PI and to increase the robustness of the limiter circuit. Negative charge pump
Fig.9 represents the electric diagram of a negative charge pump in accordance with the invention. In this example, the charge pump comprises a first stage for charging a capacitor CF with a first charge voltage Vdd and a second stage for, after disconnection of the first stage, providing the inverse voltage -Vdd to a load circuit. Both stages are constituted of MOS power transistors made on an integrated circuit CI'. The capacitor CF and the load circuit are external to the integrated circuit CI'. The transistors of the integrated circuit are connected, via connecting members, to external supply terminals VDD and GND, able to provide the charge voltage vdd .
The first stage comprises a p-channel MOS power transistor, referenced P10, having its source connected to the supply terminal VDD via a connecting member CN10 and its drain connected to a first terminal of the external capacitor CF via a connecting member CN11. The first stage also comprises an n-channel MOS power transistor, referenced N10, having its source connected to the supply terminal GND via a connecting member CN12 and its drain connected to a second terminal of the external capacitor CF via a connecting member CN13.
The second stage comprises an n-channel MOS power transistor, referenced Nil, having its drain connected to the drain of the transistor P10 and its source connected to the supply terminal GND via the connecting member CN12 or another connecting member. The second stage also comprises an n-channel MOS power transistor, referenced N12, having its drain connected to the drain of the transistor N10 and its source connected to the external load circuit via a connecting member CN14. The load circuit is modeled by a storage capacitor CL' mounted parallel to a load resistance RL' .
As for the buck-type converter, the presence of a parasitic inductance in the connecting members creates overvoltages between the drain and the source of the power transistors of the integrated circuit, particularly between the drain and the source of transistor Nil. According to the invention, this charge pump is completed by a limiter circuit able to limit the current variations within the connecting members when the transistor Nil switches. This limiter circuit is mounted between the drain and the source of transistor Nil and enables to maintain the drain-source voltage of the transistor Nil below a threshold value when it changes states .
This limiter circuit comprises two n-channel MOS transistors N13 and N14, mounted in series between the source and the drain of the transistor Nil. The source and the drain of transistor N13 are connected respectively to the source of transistor Nil and to the source of the transistor N14. The drain and gate of transistor N14 are connected to the drain of transistor Nil. A resistance R2 is mounted in series with a capacitor C2 between the source and the drain of transistor Nil. The resistance R2 is mounted between the source and the gate of transistor N13 and the capacitor C2 is mounted between the gate of transistor N13 and the drain of transistor N14.
The behavior of the voltage at the terminals of the transistor Nil is illustrated by figs.10 and 11. Fig.10 represents the voltage, referenced VDNn, on the drain of the transistor Nil and the voltage, referenced VSNn, on the source of the transistor Nil. Fig.11 represents the currents, referenced INI I , INI 2 and INI3, flowing respectively through the transistors Nil, N12 and N13. As can be seen from these figs., the limiter circuit enables to limit the overvoltages between the drain and the source of the power transistor Nil at the instant it stops conducting (switching to the off-state) of the transistors Nil and N12. The current INi3 pass through the transistors N13 and N14. The result is that the current variations in the connecting members CN11 and CN12 are reduced during this phase.
It is worth noting that, in these two embodiments, the limiter circuit is completely asynchronous with respect to the rest of the control circuit of the switching mode power supply and is triggered autonomously. Furthermore, it is only triggered off during switching of the power transistors. Thus, it is only active during these switching phases. In addition, when it is active, there is no current loss as the current crossing it is supplied to the load circuit.
Such a limiter circuit may be set-up in all types of switching mode power supplies comprising power transistors operating in switching mode and is advantageously mounted between the drain and the source of the power transistor undergoing the strongest overvoltages during switching. If the switching mode power supply comprises several power transistors undergoing strong overvoltages, it is possible to provide a limiter circuit for each one of them.

Claims

1. A switching mode power supply device comprising at least one MOS power transistor (P1;N11) made on an integrated circuit (CI;CI') and operating in switching mode, the drain and the source of said at least one MOS power transistor being connected together, via connecting members (CN1, CN3; CN11, CN12) having a non-null inductance, to one or several external circuits to said integrated circuit,
characterized in that it further comprises a limiter circuit able to limit the current variations in at least one of said connecting members during the switching of said MOS power transistor, said limiter circuit comprising :
- a resistance (Rl, R2) mounted in series with a capacitor (CI, C2) between the source and the drain of the power transistor, the source of the power transistor being connected to a first terminal of the resistance and the drain of the power transistor being connected to a first terminal of the capacitor, and
- at least a first MOS transistor (P2, N13) having its gate connected to an intermediate point between said resistance and said capacitor, its drain connected to the drain of the MOS power transistor and its source connected to the source of the MOS power transistor.
2. The device according to claim 1, characterized in that the limiter circuit is mounted between the drain and the source of said MOS power transistor.
3. The device according to claim 1 or 2, characterized in that said limiter circuit is only active during the switching of the power transistor (P1;N11) .
4. The device according to any one of claims 1 to 3, characterized in that the MOS power transistor (PI) and said first MOS transistor (P2) are p-channel transistors.
5. The device according to claim 4, characterized in that the limiter circuit further comprises a second n- channel MOS transistor (P3) mounted between the source of said first transistor and the source of the power transistor, the source of said second transistor being connected to the drain of the first transistor and the drain and gate of said second transistor being connected to the drain of the MOS power transistor.
6. The device according to any one of claims 1 to 3, characterized in that the MOS power transistor (Nil) and said first MOS transistor (N13) are n-channel transistors .
7. The device according to claim 6, characterized in that the limiter circuit further comprises a second MOS n-channel transistor (N14) mounted between the drain of said first transistor and the drain of the power transistor, the source of said second transistor being connected to the drain of the first transistor and the drain and gate of said second transistor being connected to the drain of the MOS power transistor.
8. A portable equipment comprising a switching mode power supply device according to any one of claims 1 to 7.
EP10782264.5A 2009-11-25 2010-11-22 Switching mode power supply comprising asynchronous limiter circuit Active EP2504910B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0958375 2009-11-25
PCT/EP2010/067940 WO2011064169A1 (en) 2009-11-25 2010-11-22 Switching mode power supply comprising asynchronous limiter circuit

Publications (2)

Publication Number Publication Date
EP2504910A1 true EP2504910A1 (en) 2012-10-03
EP2504910B1 EP2504910B1 (en) 2015-03-04

Family

ID=42226481

Family Applications (1)

Application Number Title Priority Date Filing Date
EP10782264.5A Active EP2504910B1 (en) 2009-11-25 2010-11-22 Switching mode power supply comprising asynchronous limiter circuit

Country Status (4)

Country Link
US (1) US8704502B2 (en)
EP (1) EP2504910B1 (en)
KR (1) KR101740084B1 (en)
WO (1) WO2011064169A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2587648A1 (en) 2011-10-28 2013-05-01 ST-Ericsson SA Charge pump circuit
DE102014006894A1 (en) * 2014-05-09 2015-11-12 Andreas Stihl Ag & Co. Kg Capacitor power supply for small electrical consumers with high power requirements
US11557971B2 (en) * 2019-11-07 2023-01-17 Mediatek Inc. Switching regulator using protection circuit for avoiding voltage stress and associated power management integrated circuit

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4754388A (en) * 1985-07-15 1988-06-28 Harris Corporation Regulator circuit for converting alternating input to a constant direct output
US4891728A (en) * 1986-12-23 1990-01-02 Siemens Aktiengesellschaft Circuit arrangement for limiting the switch-on current and for providing an over voltage protection in switch mode power supply devices
ATE162672T1 (en) * 1991-04-04 1998-02-15 Koninkl Philips Electronics Nv CIRCUIT ARRANGEMENT
US5686751A (en) 1996-06-28 1997-11-11 Winbond Electronics Corp. Electrostatic discharge protection circuit triggered by capacitive-coupling
US6198257B1 (en) * 1999-10-01 2001-03-06 Metropolitan Industries, Inc. Transformerless DC-to-AC power converter and method
US7249267B2 (en) * 2002-12-21 2007-07-24 Power-One, Inc. Method and system for communicating filter compensation coefficients for a digital power control system
US7710092B2 (en) * 2003-02-10 2010-05-04 Power-One, Inc. Self tracking ADC for digital power supply control systems
US8085024B2 (en) * 2008-04-29 2011-12-27 Exar Corporation Self-tuning digital current estimator for low-power switching converters
US8269475B2 (en) * 2009-02-17 2012-09-18 Texas Instruments Incorporated Class DH amplifier
US8040117B2 (en) * 2009-05-15 2011-10-18 Flextronics Ap, Llc Closed loop negative feedback system with low frequency modulated gain

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2011064169A1 *

Also Published As

Publication number Publication date
WO2011064169A1 (en) 2011-06-03
KR101740084B1 (en) 2017-05-25
US8704502B2 (en) 2014-04-22
EP2504910B1 (en) 2015-03-04
KR20120116946A (en) 2012-10-23
US20120235654A1 (en) 2012-09-20

Similar Documents

Publication Publication Date Title
US8487667B2 (en) Hybrid power device
US9791480B2 (en) Current sensing of switching power regulators
KR101062265B1 (en) Step-down switching regulator
US8766711B2 (en) Switching circuit with controlled driver circuit
US7535733B2 (en) Method of controlling DC-to-DC converter whereby switching control sequence applied to switching elements suppresses voltage surges at timings of switch-off of switching elements
US10075079B2 (en) Driver for low emission switching regulator
US8836380B2 (en) Bootstrap circuit
KR20170131452A (en) Drive for cascode stack of power FETs
CN110943722A (en) Driving circuit
US20160043657A1 (en) Rectifier With Voltage Detection
US10256813B2 (en) Fast transient high-side gate driving circuit
EP2504910B1 (en) Switching mode power supply comprising asynchronous limiter circuit
US10505440B1 (en) Active snubber for switching power converter
US8274269B2 (en) Switching circuit and small-size high-efficiency DC-DC converter for portable devices including the same
CN116868496B (en) Control device and control method for power conversion device
Kalenteridis et al. A soft start-up technique for inrush current limitation in DC-DC converters
US10819234B2 (en) Switching converter with a self-operated negative boost switch
JP2017093047A (en) Protection circuit
KR101491929B1 (en) Rf rectifying circuit
US20120049812A1 (en) Switched-Mode Converter
Park et al. Improvements in light-load efficiency and operation frequency for low-voltage current-mode integrated boost converters
JP5644686B2 (en) Switching element drive circuit
US8742802B2 (en) Gate driving circuit
CN115473426B (en) Output crosstalk prevention circuit for rectifier bridge multiplexing
CN212627662U (en) Driver circuit and driver

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20120607

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

DAX Request for extension of the european patent (deleted)
GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

RIC1 Information provided on ipc code assigned before grant

Ipc: H03K 17/081 20060101ALI20140919BHEP

Ipc: H02M 1/34 20070101ALI20140919BHEP

Ipc: H02M 3/158 20060101AFI20140919BHEP

INTG Intention to grant announced

Effective date: 20141010

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: AT

Ref legal event code: REF

Ref document number: 714624

Country of ref document: AT

Kind code of ref document: T

Effective date: 20150415

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602010022877

Country of ref document: DE

Effective date: 20150416

REG Reference to a national code

Ref country code: DE

Ref legal event code: R082

Ref document number: 602010022877

Country of ref document: DE

Representative=s name: GRUENECKER PATENT- UND RECHTSANWAELTE PARTG MB, DE

Ref country code: DE

Ref legal event code: R082

Ref document number: 602010022877

Country of ref document: DE

Representative=s name: WUESTHOFF & WUESTHOFF, PATENTANWAELTE PARTG MB, DE

Ref country code: DE

Ref legal event code: R081

Ref document number: 602010022877

Country of ref document: DE

Owner name: OCT CIRCUIT TECHNOLOGIES INTERNATIONAL LTD., IE

Free format text: FORMER OWNERS: ST-ERICSSON (FRANCE) SAS, GRENOBLE, FR; ST-ERICSSON SA, PLAN-LES-OUATES, CH

Ref country code: DE

Ref legal event code: R081

Ref document number: 602010022877

Country of ref document: DE

Owner name: ST-ERICSSON (GRENOBLE) SAS, FR

Free format text: FORMER OWNERS: ST-ERICSSON (FRANCE) SAS, GRENOBLE, FR; ST-ERICSSON SA, PLAN-LES-OUATES, CH

REG Reference to a national code

Ref country code: AT

Ref legal event code: MK05

Ref document number: 714624

Country of ref document: AT

Kind code of ref document: T

Effective date: 20150304

Ref country code: NL

Ref legal event code: VDEP

Effective date: 20150304

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150604

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150304

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150304

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150304

Ref country code: HR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150304

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150304

REG Reference to a national code

Ref country code: LT

Ref legal event code: MG4D

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150304

Ref country code: RS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150304

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150605

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150304

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150304

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 6

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150706

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150304

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150304

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150304

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150304

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150704

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150304

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602010022877

Country of ref document: DE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150304

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150304

26N No opposition filed

Effective date: 20151207

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150304

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150304

Ref country code: LU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20151122

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20151130

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20151130

REG Reference to a national code

Ref country code: IE

Ref legal event code: MM4A

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150304

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 7

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20151122

REG Reference to a national code

Ref country code: DE

Ref legal event code: R082

Ref document number: 602010022877

Country of ref document: DE

Representative=s name: GRUENECKER PATENT- UND RECHTSANWAELTE PARTG MB, DE

Ref country code: DE

Ref legal event code: R081

Ref document number: 602010022877

Country of ref document: DE

Owner name: OCT CIRCUIT TECHNOLOGIES INTERNATIONAL LTD., IE

Free format text: FORMER OWNERS: ST-ERICSSON (GRENOBLE) SAS, GRENOBLE, FR; ST-ERICSSON SA, PLAN-LES-OUATES, CH

Ref country code: DE

Ref legal event code: R081

Ref document number: 602010022877

Country of ref document: DE

Owner name: ST-ERICSSON (GRENOBLE) SAS, FR

Free format text: FORMER OWNERS: ST-ERICSSON (GRENOBLE) SAS, GRENOBLE, FR; ST-ERICSSON SA, PLAN-LES-OUATES, CH

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SM

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150304

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150304

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO

Effective date: 20101122

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150304

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150304

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 8

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150304

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150304

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150304

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20231127

Year of fee payment: 14

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20231127

Year of fee payment: 14

Ref country code: DE

Payment date: 20231129

Year of fee payment: 14