EP2437291A3 - Wiring design system of semiconductor integrated circuit, semiconductor integrated circuit, and wiring design program - Google Patents

Wiring design system of semiconductor integrated circuit, semiconductor integrated circuit, and wiring design program Download PDF

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Publication number
EP2437291A3
EP2437291A3 EP11184277A EP11184277A EP2437291A3 EP 2437291 A3 EP2437291 A3 EP 2437291A3 EP 11184277 A EP11184277 A EP 11184277A EP 11184277 A EP11184277 A EP 11184277A EP 2437291 A3 EP2437291 A3 EP 2437291A3
Authority
EP
European Patent Office
Prior art keywords
integrated circuit
semiconductor integrated
clock wiring
wiring design
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP11184277A
Other languages
German (de)
French (fr)
Other versions
EP2437291A2 (en
Inventor
Yuuichi Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of EP2437291A2 publication Critical patent/EP2437291A2/en
Publication of EP2437291A3 publication Critical patent/EP2437291A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/396—Clock trees
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/06—Power analysis or power optimisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A semiconductor integrated circuit including a grid-shaped clock wiring for supplying clock signals to flip flop circuits is provided, wherein
a clock wiring line has a smaller effect on distribution operation of clock signals in said grid-shaped clock wiring is thinned out from clock wiring lines forming said grid-shaped clock wiring, thereby reducing electric power consumption in said grid-shaped clock wiring,
the clock wiring lines are sequentially selected in the order of increasing the number of the flip flop circuits supplying said clock signals and the number of the clock wiring lines corresponding to a fraction of all the clock wiring lines are thinned out and eliminated.
EP11184277A 2004-11-19 2005-11-18 Wiring design system of semiconductor integrated circuit, semiconductor integrated circuit, and wiring design program Withdrawn EP2437291A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004335629 2004-11-19
EP05809336A EP1814152A4 (en) 2004-11-19 2005-11-18 Semiconductor integrated circuit wiring design system, semiconductor integrated circuit, and wiring design program

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
EP05809336.0 Division 2005-11-18

Publications (2)

Publication Number Publication Date
EP2437291A2 EP2437291A2 (en) 2012-04-04
EP2437291A3 true EP2437291A3 (en) 2012-04-11

Family

ID=36407315

Family Applications (2)

Application Number Title Priority Date Filing Date
EP11184277A Withdrawn EP2437291A3 (en) 2004-11-19 2005-11-18 Wiring design system of semiconductor integrated circuit, semiconductor integrated circuit, and wiring design program
EP05809336A Withdrawn EP1814152A4 (en) 2004-11-19 2005-11-18 Semiconductor integrated circuit wiring design system, semiconductor integrated circuit, and wiring design program

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP05809336A Withdrawn EP1814152A4 (en) 2004-11-19 2005-11-18 Semiconductor integrated circuit wiring design system, semiconductor integrated circuit, and wiring design program

Country Status (4)

Country Link
US (1) US7844935B2 (en)
EP (2) EP2437291A3 (en)
JP (1) JP5076503B2 (en)
WO (1) WO2006054786A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008147331A (en) * 2006-12-08 2008-06-26 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit and method for correcting semiconductor integrated circuit
US9058459B1 (en) * 2013-12-30 2015-06-16 Samsung Electronics Co., Ltd. Integrated circuit layouts and methods to reduce leakage

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010011362A1 (en) * 2000-01-27 2001-08-02 Nec Corporation Semiconductor layout design method and apparatus
US20030052724A1 (en) * 2001-09-18 2003-03-20 Nec Corporation Clock signal distribution circuit

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2877128B2 (en) * 1997-02-13 1999-03-31 日本電気株式会社 Layout method and apparatus
JP2000021992A (en) * 1998-07-06 2000-01-21 Seiko Epson Corp Clock signal wiring method, flip-flop arrangement method, power supply wiring method and wiring method
FR2781065B1 (en) * 1998-07-10 2000-08-25 St Microelectronics Sa METHOD OF PLACING-ROUTING A GLOBAL CLOCK CIRCUIT ON AN INTEGRATED CIRCUIT, AND ASSOCIATED DEVICES
JP4315532B2 (en) * 1999-08-04 2009-08-19 株式会社ルネサステクノロジ Wiring data generation method and large-scale integrated circuit device designed by the method
JP2002043550A (en) 2000-07-26 2002-02-08 Mitsubishi Electric Corp Semiconductor integrated device and method for setting and arranging clock driver circuit used in semiconductor integrated device
JP4931308B2 (en) * 2001-09-28 2012-05-16 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit device
JP3920124B2 (en) 2002-03-26 2007-05-30 Ｎｅｃエレクトロニクス株式会社 Semiconductor integrated circuit clock wiring method and semiconductor integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010011362A1 (en) * 2000-01-27 2001-08-02 Nec Corporation Semiconductor layout design method and apparatus
US20030052724A1 (en) * 2001-09-18 2003-03-20 Nec Corporation Clock signal distribution circuit

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
MADHAV P DESAI ET AL: "SIZING OF CLOCK DISITRBUTION NETWORKS FOR HIGH PERFORMANCE CPU CHIPS", PROCEEDINGS OF THE 33RD. DESIGN AUTOMATION CONFERENCE 1996. LAS VEGAS, JUNE 3 - 7, 1996; [PROCEEDINGS OF THE DESIGN AUTOMATION CONFERENCE (DAC)], NEW YORK, IEEE, US, vol. CONF. 33, 4 June 1996 (1996-06-04), pages 389 - 394, XP000640347, ISBN: 978-0-7803-3294-2 *
VANDENBERGHE L ET AL: "Optimal wire and transistor sizing for circuits with non-tree topology", COMPUTER-AIDED DESIGN, 1997. DIGEST OF TECHNICAL PAPERS., 1997 IEEE/AC M INTERNATIONAL CONFERENCE ON SAN JOSE, CA, USA 9-13 NOV. 1997, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 9 November 1997 (1997-11-09), pages 252 - 259, XP010261062, ISBN: 978-0-8186-8200-1, DOI: 10.1109/ICCAD.1997.643528 *

Also Published As

Publication number Publication date
US7844935B2 (en) 2010-11-30
EP1814152A4 (en) 2011-03-23
EP2437291A2 (en) 2012-04-04
EP1814152A1 (en) 2007-08-01
US20080141207A1 (en) 2008-06-12
JPWO2006054786A1 (en) 2008-06-05
JP5076503B2 (en) 2012-11-21
WO2006054786A1 (en) 2006-05-26

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