EP2430660A1 - Image sensor for imaging at a very low level of light - Google Patents

Image sensor for imaging at a very low level of light

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Publication number
EP2430660A1
EP2430660A1 EP10731768A EP10731768A EP2430660A1 EP 2430660 A1 EP2430660 A1 EP 2430660A1 EP 10731768 A EP10731768 A EP 10731768A EP 10731768 A EP10731768 A EP 10731768A EP 2430660 A1 EP2430660 A1 EP 2430660A1
Authority
EP
European Patent Office
Prior art keywords
voltage
transfer
charges
gate
potential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP10731768A
Other languages
German (de)
French (fr)
Inventor
Yvon Cazaux
Benoît Giffard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, Commissariat a lEnergie Atomique et aux Energies Alternatives CEA filed Critical Commissariat a lEnergie Atomique CEA
Publication of EP2430660A1 publication Critical patent/EP2430660A1/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/148—Charge coupled imagers
    • H01L27/14831—Area CCD imagers
    • H01L27/1485—Frame transfer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1464—Back illuminated imager structures

Definitions

  • the present invention relates to the field of integrated image sensors and, more particularly, sensors allows ⁇ a good detection at low illumination. Presentation of the prior art
  • image capture devices are known.
  • the most common structure of these sensors comprises a plurality of elementary detection devices or pixels, each comprising a photodiode formed in a semiconductor substrate, associated with a charge transfer device and a charge reading circuit that has been transferred. It is generally sought to minimize the number of sensor elements by using a read circuit for several photodiodes.
  • incident photons penetrate the semiconductor substrate and form electron-hole pairs in the substrate. The electrons of these pairs are then captured by the photodiode and then transferred by the charge transfer transistor to the associated readout circuit.
  • the patent application US 2007/0176216 describes a structure comprising, in addition to the aforementioned elements, devices, associated with each pixel, allowing the amplification of photogenerated electrons in this pixel to improve the sensitivity of the sensors.
  • CCD registers charge transfer device
  • Figure 1 illustrates a pixel of an image sensor comprising a charge multiplication stage and 2A to 2E are potential curves illustrating the functioning ⁇ that pixel during different steps of the detection.
  • the pixel of FIG. 1 is formed in and on a P-type substrate 10 biased to a reference voltage, for example ground.
  • a photodiode consisting of a heavily doped N-type region (N +).
  • the photodiode is illuminated by a light beam 13.
  • an isolated transfer gate 14 controlled by a transfer signal V ⁇ .
  • Next to the transfer gate 14 are formed several isolated grids for the multiplication of charges by avalanche effect.
  • FIGS. 2A to 2E illustrate the potential in the substrate 10, in the plane of FIG. 1, during different stages of the image capture. In these figures, a single cycle of storage, transfer and multiplication of electrons is described. The potential illustrated in each of these figures is the potential in the substrate 10 along a line that is will call later "line of maximum potential". This line passes, deep in the substrate, by the points of strongest polarization opposite isolated grids and in the photodiode.
  • the maximum polarization line passes through more or less deep points in the substrate. Note that, in the following description, we will call the grid 16 "multiplication grid" although this grid also plays a role during the initial stage of transfer.
  • FIG. 2A shows the potential curve in the photodiode 12 and in the substrate 10 during an initial charge storage phase in the photodiode 12.
  • the illumination of the sensor of FIG. 1 causes the storage of electrons in the region 12 and the potential of this region, initially equal to V ] _, decreases to reach a value V2 which is a function of the number of electrons stored and therefore the number of incident photons.
  • V ⁇ applied to the transfer gate is zero to form a potential wall and to prevent electrons from coming out of the photo ⁇ diode 12.
  • the potential ⁇ l, associated with the first multiplication grid of Charges 16 is, preferably just before the transfer step, set at a voltage V3, greater than V ] _, in anticipation of the next step.
  • Vr j substantially equal to or slightly greater than V ] _, is applied ⁇ on the transfer gate 14, while the voltage ⁇ l applied to the first charge multiplication gate 16 is equal to V3 (greater than V ] _) and that the voltage ⁇ 2 applied to the second multiplication gate 18 is zero.
  • the charges stored in the photodiode 12 are thus transferred into the potential well formed in the substrate 10, below the first multiplication grid 16.
  • the voltage V ⁇ (transfer gate) returns to a reference potential while the voltage ⁇ 2 remains at this reference potential, for example equal to zero, which blocks the electrons in the region of the substrate 10 located under the gate 16.
  • a new charge storage phase can then begin at the photodiode 12.
  • a the step illustrated in Figure 2D decreases the voltage ⁇ l applied to the gate 16 to a low voltage V4. The potential of the substrate 10 located below the gate 16 is thus lowered.
  • the voltages Vr j and ⁇ 2 applied, respectively, to the gates 14 and 18, are zero (reference potential).
  • the voltage ⁇ 3 applied to the gate 20 is set to a voltage V5 much higher than the voltage V4, in anticipation of the next step.
  • the voltage ⁇ 2 applied to the gate 18 increases rapidly to be of the order of the voltage V4, or slightly greater than V4. Since the voltage ⁇ 3 is equal to V5 (much higher than V4), the charges are transferred to the region of the substrate situated under the gate 20. The potential difference between the region located under the gate 18 ( ⁇ V4) and under the gate 20 (V5) is sufficiently high to allow the multiplication of charges by electronic avalanche effect.
  • the gate 22 is biased to a zero voltage to form a potential wall and block the charges at the gate 20.
  • the voltage V4 may be of the order of 1 V and the 10 V V5 voltage.
  • the charge transfer step may also participate in the amplification thereof, the voltage applied to the gate 16 during this step then being adapted to produce a multiplication (high voltage).
  • the steps of Figures 2D and 2E are repeated several times. For this, one carries out trans ⁇ ferts back and forth at the grids 14, 16, 18, 20 and 22, which limits the number of grids to form.
  • a problem arises if it occurs a long duration with a very low level of illumination, for example in the case where the image sensor is intended to detect images in an envi ronment ⁇ dark (night images for example).
  • the transfer of the charges during the step of FIG. 2B may be incomplete or be falsified.
  • the signal from the detector then has very degraded performance, in particular ⁇ in terms of signal to noise ratio.
  • An object of an embodiment of the present invention is to provide an image sensor allowing good detection during low illumination.
  • one embodiment of the present invention provides a unit device of an image sensor include an ⁇ ing a photogenerating region and charge collection area formed in a semiconductor substrate of a first conductivity type adapted to be biased to a reference voltage, the photogeneration region being associated with a device for transferring, multiplying and isolating charges.
  • the photogeneration region is surmounted by an insulated gate adapted to be biased alternately to a first voltage and to a second voltage, the insulated gate being made of a low-absorbency material.
  • the transfer device comprises an insulated transfer gate adapted to be biased to a fixed voltage and in which the first voltage is greater, in absolute value, than the fixed voltage to allow the collection of charges and the second voltage is lower, in absolute value, than the fixed voltage to allow the transfer of accumulated charges.
  • the device for multiplying and isolating charges is consisting of a plurality of isolated grids adapted to be polarized to fix the potential of the underlying substrate and allow the transfer of charges and the multiplication thereof by electronic avalanche effect.
  • the device for transferring, multiplying and isolating charges comprises at least five isolated grids.
  • the reference voltage is the mass.
  • the first type of conductivity is the type P.
  • the device further comprises an optical mask formed on the device for transferring, multiplying and isolating charges.
  • the substrate is thinned and is intended to be illuminated by the face opposite to that on which is formed the device for transferring, multiplying and isolating charges.
  • the present invention also provides an image sensor comprising a plurality of elementary devices as mentioned above. Brief description of the drawings
  • FIG. 1 illustrates a sensor image with conventional charge amplification
  • FIGS. 2A to 2E are potential curves illustrating the operation of the device of FIG. 1 when it is subjected to a large illumination
  • FIG. 3 shows the structure of FIG. 1
  • FIGS. 4A to 4C are potential curves illustrating a problem likely to be posed by this structure in the absence or at a very low level of illumination
  • Fig. 5 illustrates an image sensor according to an embodiment of the present invention
  • Figs. 6A and 6B are potential curves illustrating the operation of the device of Fig. 5
  • Figure 7 illustrates a variant of a device according to an embodiment of the present invention.
  • FIG. 3 shows the structure of FIG. 1, in a case of almost zero illumination (no light beam 13).
  • the device comprises a photodiode 12 consisting of a strongly doped N-type region (N +) formed on the surface of a P-type substrate 10, an insulated transfer gate 14 formed on the surface of the substrate 10 and controlled by a signal V 1 and isolated charge multiplication gates 16, 18, 20, 22 controlled respectively by signals ⁇ 1, ⁇ 2, ⁇ 3, ⁇ 4.
  • FIGS. 4A to 4C are curves of the potential in the substrate 10, along lines of maximum potential, during different stages of operation of the device of FIG. 3.
  • Figure 4A illustrates the potential in the substrate 10 at a succession of stages of storage and charge transfer (the potential V L of the gate 14 varies between zero and V] _).
  • V L of the gate 14 varies between zero and V] _.
  • the inventors propose forming an insulated gate over a substrate and applying a potential on this gate to create a charge of space in the substrate and to collect electrons from the electron / photogenerated-hole pairs in this region.
  • FIG. 5 illustrates such a device.
  • the device comprises a substrate 30, for example of the P type, biased at a reference voltage (for example ground) by its rear face.
  • a reference voltage for example ground
  • grid 32 will be called "accumulation grid”.
  • Grid 32 is not very absorbent, for example transparent, so that a light beam 34 arriving at the surface of the substrate passes through grid 32 and penetrates into substrate 30. to form electron pairs / holes.
  • an insulated transfer gate 36, charge multiplication gates 38, 40, 42 and a charge isolation grid 44 are formed on the surface of the substrate 30, formed an insulated transfer gate 36, charge multiplication gates 38, 40, 42 and a charge isolation grid 44.
  • the gates 36, 38, 40, 42, 44 are isolated grids and are respectively controlled by control signals V 1, ⁇ 1, ⁇ 2, ⁇ 3, ⁇ 4. Contrary to what is repre ⁇ sented in Figure 5, in an actual device, most part of the surface of each pixel is devoted to the accumulation grid 32 which represents the detection area of the dispo ⁇ operative part.
  • a protective layer (not shown), or optical mask, above the transfer gate 36, the amplification grids 38, 40, 42 and the isolation gate 44 so that beams bright incidents do not generate charges in the substrate located under these grids.
  • FIG. 6A is a curve of the potential in the substrate 30 of FIG. 5, along a potential line maximum, during a charge accumulation phase, before their injection into the multiplier stage.
  • the voltage V applied to the transfer gate 36 is equal to a voltage V] _ and the fixed voltage V applied to the gate accumulator 32 is equal to a voltage V a] _ higher than the voltage V ] _.
  • V a] _ higher than the voltage V ] _.
  • the voltage V ] _ is provided sufficiently low to be less than V a 2, so that the electrons accumulate Under the gate 32.
  • FIG. 6A Before the injection of the charges into the multiplier stage, the situation is that represented in FIG. 6A, the poten ⁇ tiel applied to the gate 38 being high, at a voltage V2, and the potential applied to the gate 40 being at a low level, close to zero.
  • the potential V2 is greater than Vl to allow the reception of the charges during the injection.
  • Figure 6B is a plot of potential in the subs ⁇ trat 30 of Figure 4, along a line of maximum potential during a charge transfer phase.
  • the voltage V a applied to the accumulation gate 32 passes to a voltage V 3, less than V] _. This allows the transfer of the accumulated charges on the surface of the substrate 30 under the gate 32 to the formed potential well, on the surface of this substrate, under the first multiplication grid 38.
  • the reference voltage (close to zero) applied to the gate 40 makes it possible to prevent the transferred charges from coming out of the potential well formed under the gate 38. Since the potential of the gate 32 is imposed on alternative ⁇ V] _ and V 3 avoids the aforementioned problems of increasing the surface potential of the substrate 30 under the gate 32 in a low light. This gives a complete transfer of the charges in the multiplier stage. Thus, the proposed device is effective even in case of illumination ⁇ zero or virtually zero.
  • a thin N-type doped layer 46 may be formed, on the surface of the substrate 30, facing the accumulation gates 32, transfer 36, multiplication 38, 40, 42 and isolation 44.
  • This thin layer 46 allows the maximum potential point of the substrate surface to be slightly removed to avoid parasitic phenomena (noises) often present at the interfaces between the gate insulator and the semiconductor substrate.
  • a cycle amp ⁇ cation fillers in conventional manner. For this, we can take advantage of the electronic avalanche effect by forcing the loads back and forth under the grids 38, 40 and 42 to obtain significant amplification. The gain of the amplification is adjusted by controlling the number of round trips.
  • the transfer gate 36 and the isolation gate 44 then serve as potential walls to prevent charges from coming out of the device during the amplification of the charges.
  • the gates 38 and 42 are alternately polarized to potential distant to permit amplification by avalanche effect electro ⁇ nic. Note that it will also be possible to form the charge transfer and amplification device by combining more than five neighboring grids in a suitable manner.
  • FIG. 7 illustrates a variant of the device of FIG. 5 in which the image sensor is illuminated by the rear face of the substrate 30.
  • the device of FIG. 7 differs from that of FIG. 5 in that the substrate 30 is thinned and is illuminated by the opposite side to that on which the accumulator 32, the transfer 36, the multiplication gates 38, 40, 42 and the isolation girders 44 are formed.
  • a light beam 46 reaching the substrate generates electron / hole pairs and the electrons of these pairs are collected in the potential well formed under the gate 32.
  • a beam arriving through the rear face of a substrate encounters fewer obstacles and is more easily detectable than a beam arriving on the front face of the substrate.
  • the operation of this device is then similar to that described in connection with FIGS. 6A and 6B.
  • the reference voltage applied to the P-type substrate 30 may be different from the mass.
  • the substrate 30 will be N-type doped and the voltages applied to the different grids for transfers will be of opposite sign to those presented here (the absolute values of the different voltages applied to the different isolated grids being in the same ratios as those presented in FIG. relationship with Figs. 6A and 6B).
  • the devices of Figures 5 and 7 may also be used in the case of high levels of illumination. In this case, it is possible to adapt the integration time, or accumulation of charges in the accumulation zone, according to the illumination, using a suitable electronic circuit, to avoid the saturation of the pixel.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

The invention relates to a basic device for an image sensor, including a photogeneration and charge-collecting region formed at the surface of a semiconductor substrate having a first type of conductivity (30), adapted to be biased at a reference voltage, the photogeneration region being associated with a device for the transfer (36), multiplication (38, 40, 42) and insulation (44) of charges. The photogeneration region has an insulated gate (32) mounted thereon, which is adapted to be alternately biased at a first voltage and at a second voltage, the insulated gate being made of a low-absorption material.

Description

CAPTEUR D'IMAGE POUR IMAGERIE A TRES BAS NIVEAU DE LUMIERE IMAGE SENSOR FOR IMAGING WITH LOW LEVEL OF LIGHT
Domaine de 1 ' inventionField of the invention
La présente invention concerne le domaine des capteurs d'image intégrés et, plus particulièrement, des capteurs permet¬ tant une bonne détection à faible éclairement. Exposé de l ' art antérieurThe present invention relates to the field of integrated image sensors and, more particularly, sensors allows ¬ a good detection at low illumination. Presentation of the prior art
De nombreux dispositifs de capture d'image intégrés sont connus . La structure la plus courante de ces capteurs comprend une pluralité de dispositifs élémentaires de détection ou pixels, chacun comprenant une photodiode formée dans un substrat semiconducteur, associée à un dispositif de transfert de charges et à un circuit de lecture des charges qui ont été transférées. On cherche généralement à minimiser le nombre d'éléments des capteurs en utilisant un circuit de lecture pour plusieurs photodiodes. Lorsqu'un capteur d'image reçoit un faisceau lumineux, les photons incidents pénètrent dans le substrat semiconducteur et forment, dans ce substrat, des paires électrons/trous. Les électrons de ces paires sont ensuite capturés par la photodiode puis transférés par le transistor de transfert de charges vers le circuit de lecture associé.Many built-in image capture devices are known. The most common structure of these sensors comprises a plurality of elementary detection devices or pixels, each comprising a photodiode formed in a semiconductor substrate, associated with a charge transfer device and a charge reading circuit that has been transferred. It is generally sought to minimize the number of sensor elements by using a read circuit for several photodiodes. When an image sensor receives a light beam, incident photons penetrate the semiconductor substrate and form electron-hole pairs in the substrate. The electrons of these pairs are then captured by the photodiode and then transferred by the charge transfer transistor to the associated readout circuit.
La demande de brevet US 2007/0176216 décrit une structure comprenant, en plus des éléments susmentionnés, des dispositifs, associés à chaque pixel, permettant l'amplification des électrons photogénérés dans ce pixel pour améliorer la sensibilité des capteurs. Pour réaliser cette amplification, ou multiplication de charges, il est connu d'utiliser les techniques associées aux registres CCD (dispositif à transfert de charge), c'est-à-dire de former, en surface du substrat, un ensemble de grilles métalliques polarisées en alternance. Cette polarisation alternée des grilles permet, par un effet dit d'avalanche électronique, la multiplication des électrons photo- générés.The patent application US 2007/0176216 describes a structure comprising, in addition to the aforementioned elements, devices, associated with each pixel, allowing the amplification of photogenerated electrons in this pixel to improve the sensitivity of the sensors. To achieve this amplification, or multiplication of charges, it is known to use the techniques associated with CCD registers (charge transfer device), that is to say, to form, on the surface of the substrate, a set of metal grids polarized alternately. This alternating polarization of the grids allows, by an effect called electronic avalanche, the multiplication of the photo-generated electrons.
La figure 1 illustre un pixel d'un capteur d'image comprenant un étage de multiplication des charges et les figures 2A à 2E sont des courbes de potentiel illustrant le fonctionne¬ ment de ce pixel lors de différentes étapes de la détection. Le pixel de la figure 1 est formé dans et sur un substrat 10 de type P polarisé à une tension de référence, par exemple la masse. Dans le substrat 10, en surface de celui-ci, est formée une photodiode constituée d'une région 12 fortement dopée de type N (N+) . La photodiode est éclairée par un faisceau lumineux 13. Au voisinage de la photodiode est placée une grille de transfert 14 isolée commandée par un signal de transfert V^. A côté de la grille de transfert 14 sont formées plusieurs grilles isolées permettant la multiplication des charges par effet d'avalanche. Dans l'exemple représenté, quatre grilles 16, 18, 20, 22 sont commandées, respectivement, par des signaux de commande Φl, Φ2, Φ3 et Φ4. La représentation de la figure 1 est extrêmement schématique ; en particulier, on notera que dans un dispositif réel, la plus grande partie de la surface de chaque pixel est dévolue à la photodiode. Les figures 2A à 2E illustrent le potentiel dans le substrat 10, dans le plan de la figure 1, lors de différentes étapes de la capture d'image. Dans ces figures, un unique cycle de stockage, de transfert et de multiplication des électrons est décrit. Le potentiel illustré, dans chacune de ces figures, est le potentiel dans le substrat 10 en suivant une ligne que l'on appellera par la suite "ligne de potentiel maximum". Cette ligne passe, en profondeur dans le substrat, par les points de plus forte polarisation en regard des grilles isolées et dans la photodiode. On notera que, en fonction de la tension appliquée sur les différentes grilles isolées, la ligne de polarisation maximum passe par des points plus ou moins profonds dans le substrat. On notera que, dans la suite de la description, on appellera la grille 16 "grille de multiplication" bien que cette grille joue également un rôle lors de l'étape initiale de transfert.Figure 1 illustrates a pixel of an image sensor comprising a charge multiplication stage and 2A to 2E are potential curves illustrating the functioning ¬ that pixel during different steps of the detection. The pixel of FIG. 1 is formed in and on a P-type substrate 10 biased to a reference voltage, for example ground. In the substrate 10, on the surface thereof, is formed a photodiode consisting of a heavily doped N-type region (N +). The photodiode is illuminated by a light beam 13. In the vicinity of the photodiode is placed an isolated transfer gate 14 controlled by a transfer signal V ^. Next to the transfer gate 14 are formed several isolated grids for the multiplication of charges by avalanche effect. In the example shown, four gates 16, 18, 20, 22 are controlled, respectively, by control signals Φl, Φ2, Φ3 and Φ4. The representation of Figure 1 is extremely schematic; in particular, it will be noted that in a real device, most of the surface of each pixel is devolved to the photodiode. FIGS. 2A to 2E illustrate the potential in the substrate 10, in the plane of FIG. 1, during different stages of the image capture. In these figures, a single cycle of storage, transfer and multiplication of electrons is described. The potential illustrated in each of these figures is the potential in the substrate 10 along a line that is will call later "line of maximum potential". This line passes, deep in the substrate, by the points of strongest polarization opposite isolated grids and in the photodiode. It will be noted that, as a function of the voltage applied to the different isolated grids, the maximum polarization line passes through more or less deep points in the substrate. Note that, in the following description, we will call the grid 16 "multiplication grid" although this grid also plays a role during the initial stage of transfer.
En figure 2A est représentée la courbe du potentiel dans la photodiode 12 et dans le substrat 10, lors d'une phase initiale de stockage des charges dans la photodiode 12. L'éclai- rement du capteur de la figure 1 provoque le stockage d'élec- trons dans la région 12 et le potentiel de cette région, initialement égal à V]_, diminue pour atteindre une valeur V2 qui est fonction du nombre d'électrons stockés et donc du nombre de photons incidents. Pendant la phase de stockage, la tension V^ appliquée à la grille de transfert est nulle pour former un mur de potentiel et éviter que des électrons ne sortent de la photo¬ diode 12. Le potentiel Φl, associé à la première grille de multiplication de charges 16 est, de préférence juste avant l'étape de transfert, fixé à une tension V3, supérieure à V]_, en prévision de l'étape suivante. A l'étape de la figure 2B, une tension de transfertFIG. 2A shows the potential curve in the photodiode 12 and in the substrate 10 during an initial charge storage phase in the photodiode 12. The illumination of the sensor of FIG. 1 causes the storage of electrons in the region 12 and the potential of this region, initially equal to V ] _, decreases to reach a value V2 which is a function of the number of electrons stored and therefore the number of incident photons. During the storage phase, the voltage V ^ applied to the transfer gate is zero to form a potential wall and to prevent electrons from coming out of the photo ¬ diode 12. The potential Φl, associated with the first multiplication grid of Charges 16 is, preferably just before the transfer step, set at a voltage V3, greater than V ] _, in anticipation of the next step. In the step of FIG. 2B, a transfer voltage
Vrj, sensiblement égale ou légèrement supérieure à V]_, est appli¬ quée sur la grille de transfert 14, tandis que la tension Φl appliquée à la première grille de multiplication de charges 16 est égale à V3 (supérieure à V]_) et que la tension Φ2 appliquée à la deuxième grille de multiplication 18 est nulle. Les charges stockées dans la photodiode 12 sont ainsi transférées dans le puits de potentiel formé, dans le substrat 10, en dessous de la première grille de multiplication 16.Vr j , substantially equal to or slightly greater than V ] _, is applied ¬ on the transfer gate 14, while the voltage Φl applied to the first charge multiplication gate 16 is equal to V3 (greater than V ] _) and that the voltage Φ2 applied to the second multiplication gate 18 is zero. The charges stored in the photodiode 12 are thus transferred into the potential well formed in the substrate 10, below the first multiplication grid 16.
A l'étape de la figure 2C, la tension V^ (grille de transfert) repasse à un potentiel de référence tandis que la tension Φ2 reste à ce potentiel de référence, par exemple égal à zéro, ce qui bloque les électrons dans la région du substrat 10 située sous la grille 16. Une nouvelle phase de stockage de charges peut alors commencer au niveau de la photodiode 12. A l'étape illustrée en figure 2D, on diminue la tension Φl appliquée sur la grille 16 jusqu'à une tension V4 faible. Le potentiel du substrat 10 situé en dessous de la grille 16 est ainsi abaissé. Pendant cette étape, les tensions Vrj et Φ2 appliquées, respectivement, aux grilles 14 et 18, sont nulles (potentiel de référence) . De préférence, juste avant l'étape suivante, la tension Φ3 appliquée à la grille 20 est fixée à une tension V5 très supérieure à la tension V4, en prévision de l'étape suivante.In the step of FIG. 2C, the voltage V ^ (transfer gate) returns to a reference potential while the voltage Φ2 remains at this reference potential, for example equal to zero, which blocks the electrons in the region of the substrate 10 located under the gate 16. A new charge storage phase can then begin at the photodiode 12. A the step illustrated in Figure 2D, decreases the voltage Φl applied to the gate 16 to a low voltage V4. The potential of the substrate 10 located below the gate 16 is thus lowered. During this step, the voltages Vr j and Φ2 applied, respectively, to the gates 14 and 18, are zero (reference potential). Preferably, just before the next step, the voltage Φ3 applied to the gate 20 is set to a voltage V5 much higher than the voltage V4, in anticipation of the next step.
A l'étape illustrée en figure 2E, la tension Φ2 appli- quée à la grille 18 augmente rapidement pour être de l'ordre de la tension V4, ou légèrement supérieure à V4. La tension Φ3 étant égale à V5 (très supérieure à V4), les charges sont transférées vers la région du substrat située sous la grille 20. La différence de potentiel entre la région située sous la grille 18 (≈ V4) et sous la grille 20 (V5) est suffisamment élevée pour permettre la multiplication des charges par effet d'avalanche électronique. Pendant cette étape, la grille 22 est polarisée à une tension nulle pour former un mur de potentiel et bloquer les charges au niveau de la grille 20. A titre d'exemple, la tension V4 peut être de l'ordre de 1 V et la tension V5 de 10 V. On notera que l'étape de transfert de charges (figure 2B) pourra également participer à l'amplification de celles-ci, la tension appliquée à la grille 16 lors de cette étape étant alors adaptée à produire une multiplication (tension élevée) . Pour que la multiplication des charges par effet d'avalanche soit significative, les étapes des figures 2D et 2E sont répétées plusieurs fois. Pour cela, on réalise des trans¬ ferts en allers-retours au niveau des grilles 14, 16, 18, 20 et 22, ce qui permet de limiter le nombre de grilles à former. Un problème se pose s ' il survient une durée longue à très faible niveau d'éclairement, par exemple dans le cas où le capteur d'image est destiné à détecter des images dans un envi¬ ronnement sombre (images nocturnes par exemple) . Dans ce cas, on montrera que le transfert des charges lors de l'étape de la figure 2B peut être incomplet ou être faussé. Le signal issu du détecteur présente alors des performances très dégradées, notam¬ ment en terme de rapport signal sur bruit.In the step illustrated in FIG. 2E, the voltage φ2 applied to the gate 18 increases rapidly to be of the order of the voltage V4, or slightly greater than V4. Since the voltage Φ3 is equal to V5 (much higher than V4), the charges are transferred to the region of the substrate situated under the gate 20. The potential difference between the region located under the gate 18 (≈ V4) and under the gate 20 (V5) is sufficiently high to allow the multiplication of charges by electronic avalanche effect. During this step, the gate 22 is biased to a zero voltage to form a potential wall and block the charges at the gate 20. By way of example, the voltage V4 may be of the order of 1 V and the 10 V V5 voltage. Note that the charge transfer step (Figure 2B) may also participate in the amplification thereof, the voltage applied to the gate 16 during this step then being adapted to produce a multiplication (high voltage). For the multiplication of charges by avalanche effect is significant, the steps of Figures 2D and 2E are repeated several times. For this, one carries out trans ¬ ferts back and forth at the grids 14, 16, 18, 20 and 22, which limits the number of grids to form. A problem arises if it occurs a long duration with a very low level of illumination, for example in the case where the image sensor is intended to detect images in an envi ronment ¬ dark (night images for example). In this case, it will be shown that the transfer of the charges during the step of FIG. 2B may be incomplete or be falsified. The signal from the detector then has very degraded performance, in particular ¬ in terms of signal to noise ratio.
Ainsi, il existe un besoin d'un dispositif permettant une détection et une transmission du signal de qualité, même à faible éclairement. RésuméThus, there is a need for a device for detection and transmission of the quality signal, even at low illumination. summary
Un objet d'un mode de réalisation de la présente invention est de prévoir un capteur d'image permettant une bonne détection lors d'un éclairement faible.An object of an embodiment of the present invention is to provide an image sensor allowing good detection during low illumination.
Ainsi, un mode de réalisation de la présente invention prévoit un dispositif élémentaire d'un capteur d'image, compre¬ nant une région de photogénération et de collecte de charges formée en surface d'un substrat semiconducteur d'un premier type de conductivité adapté à être polarisé à une tension de référence, la région de photogénération étant associée à un dispositif de transfert, de multiplication et d'isolement de charges. La région de photogénération est surmontée d'une grille isolée adaptée à être polarisée alternativement à une première tension et à une seconde tension, la grille isolée étant en un matériau peu absorbant .Thus, one embodiment of the present invention provides a unit device of an image sensor include an ¬ ing a photogenerating region and charge collection area formed in a semiconductor substrate of a first conductivity type adapted to be biased to a reference voltage, the photogeneration region being associated with a device for transferring, multiplying and isolating charges. The photogeneration region is surmounted by an insulated gate adapted to be biased alternately to a first voltage and to a second voltage, the insulated gate being made of a low-absorbency material.
Selon un mode de réalisation de la présente invention, le dispositif de transfert comprend une grille de transfert isolée adaptée à être polarisée à une tension fixe et dans lequel la première tension est supérieure, en valeur absolue, à la tension fixe pour permettre la collecte des charges et la seconde tension est inférieure, en valeur absolue, à la tension fixe pour permettre le transfert des charges accumulées .According to one embodiment of the present invention, the transfer device comprises an insulated transfer gate adapted to be biased to a fixed voltage and in which the first voltage is greater, in absolute value, than the fixed voltage to allow the collection of charges and the second voltage is lower, in absolute value, than the fixed voltage to allow the transfer of accumulated charges.
Selon un mode de réalisation de la présente invention, le dispositif de multiplication et d'isolement de charges est constitué d'une pluralité de grilles isolées adaptées à être polarisées pour fixer le potentiel du substrat sous-jacent et permettre le transfert des charges et la multiplication de celles-ci par effet d'avalanche électronique. Selon un mode de réalisation de la présente invention, le dispositif de transfert, de multiplication et d'isolement de charges comprend au moins cinq grilles isolées.According to one embodiment of the present invention, the device for multiplying and isolating charges is consisting of a plurality of isolated grids adapted to be polarized to fix the potential of the underlying substrate and allow the transfer of charges and the multiplication thereof by electronic avalanche effect. According to one embodiment of the present invention, the device for transferring, multiplying and isolating charges comprises at least five isolated grids.
Selon un mode de réalisation de la présente invention, la tension de référence est la masse. Selon un mode de réalisation de la présente invention, le premier type de conductivité est le type P.According to one embodiment of the present invention, the reference voltage is the mass. According to one embodiment of the present invention, the first type of conductivity is the type P.
Selon un mode de réalisation de la présente invention, le dispositif comprend en outre un masque optique formé sur le dispositif de transfert, de multiplication et d'isolement de charges.According to one embodiment of the present invention, the device further comprises an optical mask formed on the device for transferring, multiplying and isolating charges.
Selon un mode de réalisation de la présente invention, le substrat est aminci et est destiné à être éclairé par la face opposée à celle sur laquelle est formé le dispositif de transfert, de multiplication et d'isolement de charges. La présente invention prévoit aussi un capteur d'image comprenant une pluralité de dispositifs élémentaires tels que susmentionnés . Brève description des dessinsAccording to one embodiment of the present invention, the substrate is thinned and is intended to be illuminated by the face opposite to that on which is formed the device for transferring, multiplying and isolating charges. The present invention also provides an image sensor comprising a plurality of elementary devices as mentioned above. Brief description of the drawings
Ces objets, caractéristiques et avantages, ainsi que d'autres seront exposés en détail dans la description suivante de modes de réalisation particuliers faite à titre non-limitatif en relation avec les figures jointes parmi lesquelles : la figure 1, précédemment décrite, illustre un capteur d'image à amplification de charge classique ; les figures 2A à 2E sont des courbes de potentiel illustrant le fonctionnement du dispositif de la figure 1 lorsqu'il est soumis à un éclairement important ; la figure 3 reprend la structure de la figure 1 et les figures 4A à 4C sont des courbes de potentiel illustrant un problème susceptible d'être posé par cette structure en l'absence ou à très faible niveau d'éclairement ; la figure 5 illustre un capteur d'image selon un mode de réalisation de la présente invention ; et les figures 6A et 6B sont des courbes de potentiel illustrant le fonctionnement du dispositif de la figure 5 ; et la figure 7 illustre une variante d'un dispositif selon un mode de réalisation de la présente invention.These and other objects, features, and advantages will be set forth in detail in the following description of particular embodiments made in a non-limiting manner in relation to the accompanying drawings in which: FIG. 1, previously described, illustrates a sensor image with conventional charge amplification; FIGS. 2A to 2E are potential curves illustrating the operation of the device of FIG. 1 when it is subjected to a large illumination; FIG. 3 shows the structure of FIG. 1 and FIGS. 4A to 4C are potential curves illustrating a problem likely to be posed by this structure in the absence or at a very low level of illumination; Fig. 5 illustrates an image sensor according to an embodiment of the present invention; and Figs. 6A and 6B are potential curves illustrating the operation of the device of Fig. 5; and Figure 7 illustrates a variant of a device according to an embodiment of the present invention.
Par souci de clarté, de mêmes éléments ont été dési- gnés par de mêmes références aux différentes figures et, de plus, comme cela est habituel dans la représentation des circuits intégrés, les diverses figures ne sont pas tracées à l'échelle.For the sake of clarity, the same elements have been designated by the same references in the various figures and, moreover, as is customary in the representation of the integrated circuits, the various figures are not drawn to scale.
Description détaillée La figure 3 reprend la structure de la figure 1, dans un cas d'un éclairement quasi-nul (pas de faisceau lumineux 13) . Le dispositif comprend une photodiode 12 constituée d'une région fortement dopée de type N (N+) formée en surface d'un substrat 10 de type P, une grille de transfert 14 isolée formée en sur- face du substrat 10 et commandée par un signal de transfert V^ et des grilles isolées de multiplication de charges 16, 18, 20, 22 commandées, respectivement, par des signaux Φl, Φ2, Φ3, Φ4.DETAILED DESCRIPTION FIG. 3 shows the structure of FIG. 1, in a case of almost zero illumination (no light beam 13). The device comprises a photodiode 12 consisting of a strongly doped N-type region (N +) formed on the surface of a P-type substrate 10, an insulated transfer gate 14 formed on the surface of the substrate 10 and controlled by a signal V 1 and isolated charge multiplication gates 16, 18, 20, 22 controlled respectively by signals Φ1, Φ2, Φ3, Φ4.
Les figures 4A à 4C sont des courbes du potentiel dans le substrat 10, en suivant des lignes de potentiel maximum, pendant différentes étapes de fonctionnement du dispositif de la figure 3.FIGS. 4A to 4C are curves of the potential in the substrate 10, along lines of maximum potential, during different stages of operation of the device of FIG. 3.
La figure 4A illustre le potentiel dans le substrat 10 lors d'une succession d'étapes de stockage et de transfert de charges (le potentiel V^ de la grille 14 variant entre zéro et V]_) . Lorsque l 'éclairement de la photodiode est nul, aucune paire électron/trou n'est créée et le potentiel de la photodiode devrait théoriquement rester constant. Cependant, il s'avère que celui-ci augmente progressivement au fil des cycles de stockage/transfert, jusqu'à, dans l'exemple représenté, une tension V]_ ' (figure 4B). L'augmentation du potentiel dans la photodiode, lors d'une succession de cycles en l'absence ou à très faible niveau d'éclairement, est due à un courant de fuite entre la photodiode 12 fortement dopée de type N et le substrat situé en regard de la grille 16. Pendant les phases de transfert (V^ = V]_) , les potentiels de la photodiode et du canal formé sous la grille 14 sont très proches et les charges de la région 12 fuient par le canal situé sous la grille 14 en direction du puits de potentiel formé sous la grille 16, selon une loi en courant de faible in- version dont l'expression est en exp(-qV/kT), q étant la charge élémentaire, V la différence de potentiel entre le potentiel de la grille 14 et de la photodiode 12, k la constante de Boltzmann et T la température. Ainsi, le potentiel de la région 12 devient supérieur au potentiel en regard de la grille 14. On notera que, en cas d'éclairement important, ce problème ne se pose pas puisque le courant de fuite est alors négligeable par rapport au courant issu de 1 'éclairement . Par contre, à faible niveau d'éclairement, ce phénomène vient perturber l'injection des charges dans l'étage multiplicateur, annulant l'intérêt de cet étage dans les cas les plus critiques où celui-ci est essentiel. Une fois le potentiel V]_ ' atteint, si un faible éclai¬ rement intervient et qu'une faible quantité d'électrons se trouve stockée dans la photodiode 12 (figure 4C), l'efficacité de lecture de ces charges sera très mauvaise, une quantité réduite d'électrons réussissant à passer la barrière de poten¬ tiel formée par la région située sous la grille 14 lors d'un transfert. En effet, puisque le potentiel dans la photodiode est passé de V]_ à V]_ ' , on a V]_ ' > V^ lors du transfert, ce qui forme un mur de potentiel ne permettant pas le transfert des électrons stockés dans la photodiode ou permettant seulement un transfert partiel. De plus, si une quantité d'électrons suffisante pour le transfert est stockée dans la photodiode 12, le transfert est faussé du fait de la variation du potentiel pendant la période sans éclairement de la photodiode (on transfère moins de charges qu'il n'y en a eu de réellement stockées dans la photodiode 12) . Ainsi, dans le cas d'un très faible éclairement ou d'un éclairement nul, la lecture des charges réalisée par le dispositif de la figure 3 n'est pas bonne.Figure 4A illustrates the potential in the substrate 10 at a succession of stages of storage and charge transfer (the potential V L of the gate 14 varies between zero and V] _). When the illumination of the photodiode is zero, no electron / hole pair is created and the potential of the photodiode should theoretically remain constant. However, it turns out that it increases gradually over the storage / transfer cycles, until, in the example shown, a voltage V ] _ '(Figure 4B). The increase of the potential in the photodiode, during a succession of cycles in the absence or at a very low level of illumination, is due to a leakage current between the strongly doped N-type photodiode 12 and the substrate located in opposite the gate 16. During the transfer phases (V = V ^] _), the potential of the photodiode and the channel formed under the gate 14 are very close and the charge region 12 leaking through the channel located in the gate 14 towards the potential well formed under the gate 16, according to a current law of low version whose expression is exp (-qV / kT), q being the elementary charge, V the potential difference between the potential of the gate 14 and the photodiode 12, k the Boltzmann constant and T the temperature. Thus, the potential of the region 12 becomes greater than the potential with respect to the gate 14. It will be noted that, in case of significant illumination, this problem does not arise since the leakage current is then negligible compared to the current coming from 1 illumination. On the other hand, at low level of illumination, this phenomenon disturbs the injection of the charges in the multiplier stage, canceling the interest of this stage in the most critical cases where this one is essential. Once the potential V] _ 'reached, if a low illuminance ¬ surely occurs and a small amount of electrons is stored in the photodiode 12 (Figure 4C), the reading efficiency of these loads will be very bad, a reduced amount of electrons succeeding to pass the barrier poten ¬ tiel formed by the region located under the gate 14 during a transfer. Indeed, since the potential in the photodiode is increased from V] _ to V] _ ', V] _'> V ^ during the transfer, which forms a potential wall does not allow the transfer of electrons stored in the photodiode or allowing only a partial transfer. Moreover, if a sufficient quantity of electrons for the transfer is stored in the photodiode 12, the transfer is distorted due to the variation of the potential during the period without illumination of the photodiode (less charge is transferred than it there have been some actually stored in photodiode 12). Thus, in the case of very low illumination or zero illumination, the reading of the charges carried out by the device of FIG. 3 is not good.
Pour résoudre ce problème, les inventeurs proposent de former une grille isolée au-dessus d'un substrat et d'appliquer un potentiel sur cette grille pour créer une charge d'espace dans le substrat et collecter des électrons des paires électrons/trous photogénérées dans cette région.To solve this problem, the inventors propose forming an insulated gate over a substrate and applying a potential on this gate to create a charge of space in the substrate and to collect electrons from the electron / photogenerated-hole pairs in this region.
La figure 5 illustre un tel dispositif. Le dispositif comprend un substrat 30, par exemple de type P, polarisé à une tension de référence (par exemple la masse) par sa face arrière. Sur ce substrat est formée une grille 32 isolée, commandée par un signal Va. Par la suite, on appellera "grille d'accumulation" la grille 32. La grille 32 est peu absorbante, par exemple transparente, de sorte qu'un faisceau lumineux 34 arrivant en surface du substrat traverse la grille 32 et pénètre dans le substrat 30 pour y former des paires électrons/trous. A côté de la grille d'accumulation 32, en surface du substrat 30, sont formées une grille isolée de transfert 36, des grilles de multi- plication de charges 38, 40, 42 et une grille d'isolement des charges 44. Les grilles 36, 38, 40, 42, 44 sont des grilles isolées et sont commandées, respectivement, par des signaux de commande V^, Φl, Φ2, Φ3, Φ4. Contrairement à ce qui est repré¬ senté en figure 5, dans un dispositif réel, la plus grande partie de la surface de chaque pixel est dévolue à la grille d'accumulation 32 qui représente la zone de détection du dispo¬ sitif. De préférence, on prévoit une couche de protection (non représentée) , ou masque optique, au-dessus de la grille de transfert 36, des grilles d'amplification 38, 40, 42 et de la grille d'isolement 44 pour que des faisceaux lumineux incidents ne génèrent pas de charges dans le substrat situé sous ces grilles.Figure 5 illustrates such a device. The device comprises a substrate 30, for example of the P type, biased at a reference voltage (for example ground) by its rear face. On this substrate is formed an isolated gate 32, controlled by a signal V a . Subsequently, grid 32 will be called "accumulation grid". Grid 32 is not very absorbent, for example transparent, so that a light beam 34 arriving at the surface of the substrate passes through grid 32 and penetrates into substrate 30. to form electron pairs / holes. Next to the accumulation grid 32, on the surface of the substrate 30, are formed an insulated transfer gate 36, charge multiplication gates 38, 40, 42 and a charge isolation grid 44. The gates 36, 38, 40, 42, 44 are isolated grids and are respectively controlled by control signals V 1, Φ 1, Φ 2, Φ 3, Φ 4. Contrary to what is repre ¬ sented in Figure 5, in an actual device, most part of the surface of each pixel is devoted to the accumulation grid 32 which represents the detection area of the dispo ¬ operative part. Preferably, there is provided a protective layer (not shown), or optical mask, above the transfer gate 36, the amplification grids 38, 40, 42 and the isolation gate 44 so that beams bright incidents do not generate charges in the substrate located under these grids.
La figure 6A est une courbe du potentiel dans le substrat 30 de la figure 5, en suivant une ligne de potentiel maximum, lors d'une phase d'accumulation de charges, avant leur injection dans l'étage multiplicateur.FIG. 6A is a curve of the potential in the substrate 30 of FIG. 5, along a potential line maximum, during a charge accumulation phase, before their injection into the multiplier stage.
Pendant la phase de détection, la tension V^ appliquée à la grille de transfert 36 est égale à une tension V]_ fixe et la tension Va appliquée à la grille d'accumulation 32 est égale à une tension Va]_ supérieure à la tension V]_ . On forme ainsi un puits de potentiel sous la grille d'accumulation 32. Lorsque des paires électrons/trous sont photogénérées dans le substrat 30, les électrons sont collectés dans le substrat 30 par la grille d'accumulation 32. Alors, le potentiel de surface sous la grille 32 diminue proportionnellement au nombre d'électrons photo- générés pour atteindre une tension Va2. On notera que la tension V]_ est prévue suffisamment basse pour être inférieure à Va2, de sorte que les électrons s'accumulent sous la grille 32. Lorsque l'étage multiplicateur est vide, on applique de préférence un potentiel bas, proche de zéro, sur les grilles 38, 40 et 42, afin de minimiser la collecte directe des porteurs libres par l'étage multiplicateur.During the detection phase, the voltage V applied to the transfer gate 36 is equal to a voltage V] _ and the fixed voltage V applied to the gate accumulator 32 is equal to a voltage V a] _ higher than the voltage V ] _. Thus, a potential well is formed under the accumulation grid 32. When electron / hole pairs are photogenerated in the substrate 30, the electrons are collected in the substrate 30 by the accumulation grid 32. Then, the surface potential under the gate 32 decreases proportionally to the number of electrons photo-generated to reach a voltage V to 2. Note that the voltage V ] _ is provided sufficiently low to be less than V a 2, so that the electrons accumulate Under the gate 32. When the multiplier stage is empty, a low potential, close to zero, is preferably applied to the gates 38, 40 and 42, in order to minimize the direct collection of the free carriers by the multiplier stage.
Avant l'injection des charges dans l'étage multiplica- teur, la situation est celle représentée en figure 6A, le poten¬ tiel appliqué à la grille 38 étant élevé, à une tension V2, et le potentiel appliqué sur la grille 40 étant à un niveau bas, proche de zéro. Le potentiel V2 est supérieur à Vl pour permettre l'accueil des charges lors de l'injection. La figure 6B est une courbe du potentiel dans le subs¬ trat 30 de la figure 4, en suivant une ligne de potentiel maximum, lors d'une phase de transfert de charges. La tension Va appliquée à la grille d'accumulation 32 passe à une tension Va3, inférieure à V]_ . Ceci permet le transfert des charges accumulées en surface du substrat 30 sous la grille 32 vers le puits de potentiel formé, en surface de ce substrat, sous la première grille de multiplication 38. Pendant le transfert des charges, la tension de référence (proche de zéro) appliquée à la grille 40 permet d'éviter que les charges transférées ne sortent du puits de potentiel formé sous la grille 38. Puisque le potentiel de la grille 32 est alternative¬ ment imposé à Va]_ et à Va3, on évite les problèmes susmentionnés d'augmentation du potentiel en surface du substrat 30 sous la grille 32 lors d'un faible éclairement. On obtient ainsi un transfert complet des charges dans l'étage multiplicateur. Ainsi, le dispositif proposé est efficace même en cas d' éclaire¬ ment nul ou quasi-nul.Before the injection of the charges into the multiplier stage, the situation is that represented in FIG. 6A, the poten ¬ tiel applied to the gate 38 being high, at a voltage V2, and the potential applied to the gate 40 being at a low level, close to zero. The potential V2 is greater than Vl to allow the reception of the charges during the injection. Figure 6B is a plot of potential in the subs ¬ trat 30 of Figure 4, along a line of maximum potential during a charge transfer phase. The voltage V a applied to the accumulation gate 32 passes to a voltage V 3, less than V] _. This allows the transfer of the accumulated charges on the surface of the substrate 30 under the gate 32 to the formed potential well, on the surface of this substrate, under the first multiplication grid 38. During the transfer of the charges, the reference voltage (close to zero) applied to the gate 40 makes it possible to prevent the transferred charges from coming out of the potential well formed under the gate 38. Since the potential of the gate 32 is imposed on alternative ¬ V] _ and V 3 avoids the aforementioned problems of increasing the surface potential of the substrate 30 under the gate 32 in a low light. This gives a complete transfer of the charges in the multiplier stage. Thus, the proposed device is effective even in case of illumination ¬ zero or virtually zero.
Optionnellement, une fine couche 46 dopée de type N pourra être formée, en surface du substrat 30, en regard des grilles d'accumulation 32, de transfert 36, de multiplication 38, 40, 42 et d'isolement 44. Cette fine couche 46 permet d'éloigner légèrement le point de potentiel maximum de la surface du substrat pour éviter des phénomènes parasites (bruits) souvent présents aux interfaces entre isolant de grille et substrat semiconducteur.Optionally, a thin N-type doped layer 46 may be formed, on the surface of the substrate 30, facing the accumulation gates 32, transfer 36, multiplication 38, 40, 42 and isolation 44. This thin layer 46 allows the maximum potential point of the substrate surface to be slightly removed to avoid parasitic phenomena (noises) often present at the interfaces between the gate insulator and the semiconductor substrate.
Une fois que le transfert des électrons est effectué de la grille 32 vers la grille 38, on réalise un cycle d'ampli¬ fication des charges de façon classique. Pour cela, on peut tirer profit de l'effet d'avalanche électronique en forçant les charges à des allers-retours sous les grilles 38, 40 et 42 afin d'obtenir une amplification significative. Le gain de l'amplification est ajusté en contrôlant le nombre d'allers-retours. La grille de transfert 36 et la grille d'isolement 44 servent alors de murs de potentiels pour éviter que des charges ne sortent du dispositif lors de l'amplification des charges. Les grilles 38 et 42 sont alternativement polarisées à des potentiels éloignés pour permettre l'amplification par effet d'avalanche électro¬ nique. On notera que l'on pourra également former le dispositif de transfert et d'amplification de charge en combinant plus de cinq grilles voisines de façon adaptée.Once the transfer of electrons is performed in the gate 32 toward the gate 38, there is provided a cycle amp ¬ cation fillers in conventional manner. For this, we can take advantage of the electronic avalanche effect by forcing the loads back and forth under the grids 38, 40 and 42 to obtain significant amplification. The gain of the amplification is adjusted by controlling the number of round trips. The transfer gate 36 and the isolation gate 44 then serve as potential walls to prevent charges from coming out of the device during the amplification of the charges. The gates 38 and 42 are alternately polarized to potential distant to permit amplification by avalanche effect electro ¬ nic. Note that it will also be possible to form the charge transfer and amplification device by combining more than five neighboring grids in a suitable manner.
La figure 7 illustre une variante du dispositif de la figure 5 dans laquelle le capteur d'image est éclairé par la face arrière du substrat 30. Le dispositif de la figure 7 diffère de celui de la figure 5 en ce que le substrat 30 est aminci et est éclairé par la face opposée à celle sur laquelle sont formées les grilles d'accumulation 32, de transfert 36, de multiplication des charges 38, 40, 42 et d'isolement 44. Pendant la phase d'accumulation, un faisceau lumineux 46 atteignant le substrat y génère des paires électrons/trous et les électrons de ces paires sont collectés dans le puits de potentiel formé sous la grille 32. Avantageusement, et de façon classique, un faisceau arrivant par la face arrière d'un substrat rencontre moins d'obstacles et est plus facilement détectable qu'un faisceau arrivant sur la face avant du substrat. Le fonctionne- ment de ce dispositif est ensuite similaire à celui décrit en relation avec les figures 6A et 6B.FIG. 7 illustrates a variant of the device of FIG. 5 in which the image sensor is illuminated by the rear face of the substrate 30. The device of FIG. 7 differs from that of FIG. 5 in that the substrate 30 is thinned and is illuminated by the opposite side to that on which the accumulator 32, the transfer 36, the multiplication gates 38, 40, 42 and the isolation girders 44 are formed. During the accumulation phase, a light beam 46 reaching the substrate generates electron / hole pairs and the electrons of these pairs are collected in the potential well formed under the gate 32. Advantageously, and conventionally, a beam arriving through the rear face of a substrate encounters fewer obstacles and is more easily detectable than a beam arriving on the front face of the substrate. The operation of this device is then similar to that described in connection with FIGS. 6A and 6B.
Des modes de réalisation particuliers de la présente invention ont été décrits. Diverses variantes et modifications apparaîtront à l'homme de l'art. En particulier, on notera que la tension de référence appliquée au substrat 30 de type P pourra être différente de la masse. De plus, bien que l'on ait décrit ici un dispositif dans lequel les charges photogénérées utiles sont les électrons, on notera que l'on pourra également prévoir des dispositifs similaires dans lesquels les charges utiles sont les trous. Pour cela, le substrat 30 sera dopé de type N et les tensions appliquées aux différentes grilles pour les transferts seront de signe opposé à celles présentées ici (les valeurs absolues des différentes tensions appliquées aux différentes grilles isolées étant dans de mêmes rapports que celles présentées en relation avec les figures 6A et 6B) .Particular embodiments of the present invention have been described. Various variations and modifications will be apparent to those skilled in the art. In particular, it will be noted that the reference voltage applied to the P-type substrate 30 may be different from the mass. In addition, although there has been described here a device in which the useful photogenerated charges are electrons, it will be appreciated that similar devices may also be provided in which the payloads are the holes. For this, the substrate 30 will be N-type doped and the voltages applied to the different grids for transfers will be of opposite sign to those presented here (the absolute values of the different voltages applied to the different isolated grids being in the same ratios as those presented in FIG. relationship with Figs. 6A and 6B).
Les dispositifs des figures 5 et 7 pourront également être utilisés dans le cas de forts niveaux d'éclairement . Dans ce cas, on peut prévoir d'adapter le temps d'intégration, ou d'accumulation de charges dans la zone d'accumulation, en fonction de 1 'éclairement, à l'aide d'un circuit électronique adapté, pour éviter la saturation du pixel. The devices of Figures 5 and 7 may also be used in the case of high levels of illumination. In this case, it is possible to adapt the integration time, or accumulation of charges in the accumulation zone, according to the illumination, using a suitable electronic circuit, to avoid the saturation of the pixel.

Claims

REVENDICATIONS
1. Dispositif élémentaire d'un capteur d'image, comprenant une région de photogénération et de collecte de charges formée en surface d'un substrat semiconducteur d'un premier type de conductivité (30) adapté à être polarisé à une tension de référence, la région de photogénération étant associée à un dispositif de transfert (36) , de multiplication (38, 40, 42) et d'isolement (44) de charges, caractérisé en ce que la région de photogénération est surmontée d'une grille isolée (32) adaptée à être polarisée alternativement à une première tension (Va]_) et à une seconde tension (Va3) , la grille isolée étant en un matériau peu absorbant.An elementary device of an image sensor, comprising a photogeneration and charge collection region formed on the surface of a semiconductor substrate of a first conductivity type (30) adapted to be biased to a reference voltage, the photogeneration region being associated with a device for transferring (36), multiplying (38, 40, 42) and isolating (44) charges, characterized in that the photogeneration region is surmounted by an insulated gate ( 32) adapted to be alternately biased to a first voltage (V a ] _) and a second voltage (V a 3), the insulated gate being of a low-absorbency material.
2. Dispositif élémentaire selon la revendication 1, dans lequel le dispositif de transfert comprend une grille de transfert isolée (36) adaptée à être polarisée à une tension fixe (V]_) et dans lequel la première tension (Va]_) est supérieure, en valeur absolue, à la tension fixe (V]_) pour permettre la collecte des charges et la seconde tension (Va3) est inférieure, en valeur absolue, à la tension fixe pour permettre le transfert des charges accumulées. 2. Elementary device according to claim 1, wherein the transfer device comprises an insulated transfer gate (36) adapted to be biased to a fixed voltage (V] _) and in which the first voltage (V a ] _) is higher, in absolute value, at the fixed voltage (V] _) to allow the collection of charges and the second voltage (V a 3) is lower, in absolute value, than the fixed voltage to allow the transfer of accumulated charges.
3. Dispositif élémentaire selon la revendication 1 ouElementary device according to claim 1 or
2, dans lequel le dispositif de multiplication et d'isolement de charges est constitué d'une pluralité de grilles isolées (38, 40, 42) adaptées à être polarisées pour fixer le potentiel du substrat (30) sous-jacent et permettre le transfert des charges et la multiplication de celles-ci par effet d'avalanche électronique.2, wherein the charge multiplication and isolation device is comprised of a plurality of insulated gates (38, 40, 42) adapted to be biased to secure the potential of the underlying substrate (30) and enable the transfer loads and the multiplication of these by electronic avalanche effect.
4. Dispositif élémentaire selon la revendication 3, dans lequel le dispositif de transfert, de multiplication et d'isolement de charges comprend au moins cinq grilles isolées (36, 38, 40, 42, 44) .An elementary device according to claim 3, wherein the charge transfer, multiplication and isolation device comprises at least five isolated gates (36, 38, 40, 42, 44).
5. Dispositif élémentaire selon l'une quelconque des revendications 1 à 4, dans lequel la tension de référence est la masse. 5. Elementary device according to any one of claims 1 to 4, wherein the reference voltage is the ground.
6. Dispositif élémentaire selon l'une quelconque des revendications 1 à 5, dans lequel le premier type de conducti- vité est le type P.6. Elementary device according to any one of claims 1 to 5, wherein the first type of conductivity is the type P.
7. Dispositif élémentaire selon l'une quelconque des revendications 1 à 6, comprenant en outre un masque optique formé sur le dispositif de transfert (36) , de multiplication (38, 40, 42) et d'isolement (44) de charges.7. Elementary device according to any one of claims 1 to 6, further comprising an optical mask formed on the transfer device (36) for multiplying (38, 40, 42) and isolating (44) charges.
8. Dispositif élémentaire selon l'une quelconque des revendications 1 à 7, dans lequel le substrat (30) est aminci et est destiné à être éclairé par la face opposée à celle sur laquelle est formé le dispositif de transfert, de multiplication et d'isolement de charges.8. Elementary device according to any one of claims 1 to 7, wherein the substrate (30) is thinned and is intended to be illuminated by the face opposite to that on which is formed the transfer device, multiplication and isolation of charges.
9. Capteur d'image comprenant une pluralité de dispo¬ sitifs élémentaires selon l'une quelconque des revendications 1 à 8. 9. An image sensor comprising a plurality of elementary dispensing devices according to any one of claims 1 to 8.
EP10731768A 2009-05-14 2010-05-11 Image sensor for imaging at a very low level of light Withdrawn EP2430660A1 (en)

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FR0953194A FR2945668B1 (en) 2009-05-14 2009-05-14 IMAGE SENSOR FOR IMAGING AT VERY LIGHT LEVEL.
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