Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
  • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
  • H03F1/34—Negative-feedback-circuit arrangements with or without positive feedback
  • H03F1/345—Negative-feedback-circuit arrangements with or without positive feedback using hybrid or directional couplers
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
  • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
  • H04L27/36—Modulator circuits; Transmitter circuits
  • H04L27/362—Modulation using more than one carrier, e.g. with quadrature carriers, separately amplitude modulated
  • H04L27/364—Arrangements for overcoming imperfections in the modulator, e.g. quadrature error or unbalanced I and Q levels
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/204—A hybrid coupler being used at the output of an amplifier circuit
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/336—A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/57—Separate feedback of real and complex signals being present

Definitions

• This application is related to radio transmitters and, in particular, radio transmitters that employ linearization feedback paths with dual phase shifters to correct for IQ phase imbalance.
• Wireless communication systems typically provide for radio telecommunication links to be arranged between a plurality of subscriber units (or mobile stations (MSs)) via a system infrastructure having fixed installations including one or more base transceiver stations (BTSs).
• BTSs base transceiver stations
• Radio frequency (RF) transmitters are located in both BTSs and MSs in order to facilitate wireless communication between the communication units.
• TETRA TErrestrial Trunked Radio
• ETSI European Telecommunications Standards Institute
• a system that operates according to TETRA standards is known as a TETRA system.
• TETRA systems are primarily designed for use by professional radio users, such as the emergency services.
• spectrally efficient linear modulation schemes By using spectrally efficient linear modulation schemes, more communication devices are able to share the allocated spectrum within a defined geographical coverage area (cell).
• Cartesian feedback loop based linearizers are commonly used in linear digital cellular portable transmitters (TETRA, iDEN, etc.) Cartesian feedback linearizer allows an improvement in adjacent and alternative channels ACP (Adjacent Channel Power) while still allowing RFPA to work close to its saturation point thus maintaining good efficiency.
• ACP Adjacent Channel Power
• Cartesian feedback is a 'closed loop' negative feedback technique having a forward path and a feedback path, in which the baseband feedback signal in the feedback path is summed in its digital in- phase (I channel) and quadrature phase (Q channel) formats with the corresponding generated I and Q input signals in the forward path.
• the linearizing of the power amplifier output requires the accurate setting and on-going control of the phase and amplitude of a feedback signal.
• the linearizer circuit optimizes the performance of the transmitter, for example to comply with linearity or output power specifications of the communication system, or to optimize the operating efficiency of the transmitter power amplifier.
• Operational parameters of the transmitter are adjusted to optimize CMl 1 944 the transmitter performance and include as an example, one or more of the following: amplifier bias voltage level, input power level, phase shift of the signal around the feedback path.
• Such adjustments are performed by say, a microprocessor. Due to the sensitivity of such transmitter circuits, a range of control and adjustment circuits and/or components are needed so that a linear and stable output signal can be achieved under all operating circumstances.
• All linearization techniques require a finite amount of time in which to linearize the performance of a given amplifier.
• the amplifier may be linearized by initially applying a training sequence to the linearizer circuit and the amplifier to determine the levels of phase and gain distortion introduced by the linearization loop and the amplifying device. Once the phase and gain distortion levels have been determined, they can be compensated for, generally by adjusting feedback components/parameters .
• the TETRA standard includes a time frame, termed a Common Linearization Channel (CLCH) as is described in UK Patent Application No. 9222922.8, to provide a full-training period approximately once every second.
• CLCH Common Linearization Channel
• the CLCH frame allows a radio to train prior to gaining access to the system. However, a radio having to wait up to one second before training and then accessing the system is undesirable.
• a reduced training sequence has been inserted at the beginning of each TETRA traffic time slot for the radio allocated that slot to perform a minimal amount of training or fine tuning. This period may be used for phase training.
• Phase training is used in Cartesian feedback loop to correctly adjust the loop phase to ensure stability using negative feedback.
• the Cartesian feedback loop is configured to be 'open loop', i.e. a switch is used to prevent the fed-back signal from being combined with the signal routed through the transmitter circuit.
• a positive signal is applied to the I-channel input.
• the phase shift of the feedback path is measured and, in response to the measured I-channel phase shift, the phase around the loop on both the I-channel and the Q-channel is adjusted by a phase shifter.
• FIG. 1 illustrates a block diagram of a transmitter 100 containing a typical set of Cartesian feedback loops 100.
• the transmitter 100 is in phase training mode, as the switches 132, 134 for the I and Q channels are open.
• Each of the analog baseband I and Q signals are respectively supplied to a summer 102, 112.
• the signals from the summers 102, 112 are amplified by an amplifier 104, 114 of predetermined gain and then passed through a low-pass filter 106, 116.
• the resulting low-pass filtered signals are then upconverted by a mixer 108, 118 supplied with signal at the desired frequency by a local oscillator (LO) 140 and phase shifted by a 90° phase shifter 110.
• LO local oscillator
• the upconverted signals are then combined at a summer 122, amplified by a power amplifier 124 of predetermined gain and supplied to an antenna 136.
• a coupler 138 samples the transmitted signal and feeds it to down-converting mixers 124, 126 again supplied with a signal that is phase shifted by a 90° phase shifter 128.
• the signals from the mixers 124, 126 are fed to phase training control 130, which using a successive approximation register (SAR) algorithm adjusts the phase of the phase shifter 150.
• SAR successive approximation register
• Phase training is described below.
• the Cartesian loop is open (switches 132 and 134 open) and a positive baseband signal applied to the input of the I- channel.
• Phase training control circuitry 130 monitors the signal before switch on the Q-channel - indicated as Vfq 140.
• a SAR phase training algorithm controls the phase shifter 150 and minimizes the Vfq voltage.
• a voltage value measured on the Q- channel prior to the switch 134 is then reduced to a level close to zero.
• the same process is repeated for a negative baseband signal input to the I-channel.
• the CMl 1 944 calculated results from both the positive and negative training applied to the I-channel are then further processed by averaging the results and using the averages to adjust the phase around both the I-channel loop and the Q-channel loop.
• Figure 1 illustrates a block diagram of a known transmitter.
• Figure 2 illustrates a block diagram of one embodiment of a wireless communication device.
• Figure 3 illustrates a communication system incorporating the device of Fig. 2.
• Figure 4 illustrates a block diagram of one embodiment of phase shifter architecture in a transmitter.
• Figure 5 illustrates a block diagram of one embodiment of a transmitter.
• Figure 6 is a flowchart of one embodiment of a linearization training process.
• Figure 7 is a flowchart of another embodiment of a linearization training process.
• a communication system contains a communication device, itself having a transmitter using in-phase and quadrature signals.
• the transmitter has a Cartesian feedback loop containing a forward path and, for each of the in-phase and quadrature signals, a feedback path.
• Each feedback path contains a phase shifter supplied with a different output from a phase training module such that in-phase and quadrature phase rotations provided by the phase shifters are separate and independent of each other.
• Each phase shifter is supplied with a local oscillator signal and a phase shifted local oscillator signal as well as a control signal from the phase training module.
• a first or second phase training signal is applied to the phase shifters respectively during a first or second training session. The second training session is shorter than the first training session.
• the phase shift at the output of each respective feedback path is repeatedly compared (during the appropriate phase training session) to the midpoint phase shift in a range of phase shifts, with the range being halved in each successive repetition.
• the initial range at the start of the second training session is smaller than that at the start of the first training session as the phase CMl 1 944 rotation applied at the end of the first training session is used as the initial phase rotation applied at the start of the second training session.
• FIG. 2 illustrates a block diagram of an exemplary communication device 200.
• the communication device 200 is a handheld mobile device such as a Professional Mobile radio (PMR), cellular telephone, personal digital assistant (PDA), push-to-talk (PTT) radio, or wireless laptop computer, however, in other embodiments the communication device can be vehicle mounted or fixed to a particular geographic location, such as a base station.
• PMR Professional Mobile radio
• PDA personal digital assistant
• PTT push-to-talk
• the device 200 contains, among other components, a processor 202, a transceiver 204 including transmitter circuitry 206 and receiver circuitry 208, an antenna 222, a display 210, an input device(s) 212, a program memory 214 for storing operating instructions that are executed by the processor 202, a buffer memory 216, one or more communication interfaces 218, and a removable storage 220, all connected by a bus 230.
• the device 200 also preferably includes an antenna switch, duplexer, circulator, or other highly isolative means for intermittently providing information packets from the transmitter circuitry 206 to the antenna 222 and from the antenna 222 to the receiver circuitry 208.
• the device 200 is preferably an integrated unit containing at least all the elements depicted in Fig. 2, as well as any other elements necessary for the device 200 to perform its particular electronic function.
• the device 200 may comprise a collection of appropriately interconnected units or devices, wherein such units or devices perform functions that are equivalent to the functions performed by the elements of the device 200.
• the device 200 may comprise a laptop computer and a Wireless Local Area Network (WLAN) card.
• WLAN Wireless Local Area Network
• the processor 202 preferably includes one or more microprocessors, microcontrollers, DSPs, state machines, logic circuitry, or any other device or devices that process information based on operational or programming instructions. Such operational or programming instructions are preferably stored in the program memory 214.
• the program memory 214 may be an IC memory chip containing any form of random access memory (RAM) or read only memory (ROM), a floppy disk, a compact disk (CD) ROM, a hard disk drive, a digital video disk (DVD), a flash memory card or any other medium for storing digital information.
• CMl 1 944 skill in the art will recognize that when the processor 202 has one or more of its functions performed by a state machine or logic circuitry, the memory 214 containing the corresponding operational instructions may be embedded within the state machine or logic circuitry. The operations performed by the processor 202 and the rest of the device 200 are described in detail below.
• the transmitter circuitry 206 and the receiver circuitry 208 enable the device 200 to communicate information packets to and acquire information packets from the other nodes.
• the transmitter circuitry 206 and the receiver circuitry 208 include appropriate, conventional circuitry to enable digital or analog transmissions over a wireless communication channel.
• the transmitter circuitry 206 and the receiver circuitry 208 are designed to operate over an ad hoc networking air interface (e.g., BLUETOOTH, 802.11 WLAN, Wi-Fi, WiMAX, . . . , etc.).
• an ad hoc networking air interface e.g., BLUETOOTH, 802.11 WLAN, Wi-Fi, WiMAX, . . . , etc.
• the implementations of the transmitter circuitry 206 and the receiver circuitry 208 depend on the implementation of the device 200.
• the transmitter circuitry 206 and the receiver circuitry 208 may be implemented as an appropriate wireless modem, or as conventional transmitting and receiving components of two- way wireless communication devices.
• the modem can be internal to the device 200 or insertable into the device 200 (e.g., embodied in a wireless RF modem implemented on a Personal Computer Memory Card International Association (PCMCIA) card).
• PCMCIA Personal Computer Memory Card International Association
• the transmitter circuitry 206 and the receiver circuitry 208 are preferably implemented as part of the wireless device hardware and software architecture in accordance with known techniques.
• the transmitter circuitry 206 and/or the receiver circuitry 208 may be implemented in a processor, such as the processor 202.
• the processor 202, the transmitter circuitry 206, and the receiver circuitry 208 have been artificially partitioned herein to facilitate a better understanding.
• the receiver circuitry 208 is capable of receiving RF signals from at least one band and optionally more bands, if the communications with the proximate device are in a frequency band other than that of the network communications.
• the receiver circuitry 208 may optionally comprise a first receiver and a second receiver, or one CMl 1 944 receiver capable of receiving in two or more bandwidths.
• the receiver 208 depending on the mode of operation, may be attuned to receive, for example, Bluetooth or WLAN, such as 102.11, communication signals.
• the transceiver 204 includes at least one set of transmitter circuitry 206.
• the transmitter circuitry 206 may be capable of transmitting to multiple devices potentially in multiple frequency bands.
• the receiver circuitry 208 includes, for example, receiver front-end circuitry (effectively providing reception, filtering and intermediate or base-band frequency conversion), a signal processor (generally realized by at least one digital signal processor (DSP)) serially coupled to the front-end circuitry, a controller to calculate receive bit-error-rate (BER) or frame-error-rate (FER) or similar link-quality measurement data from recovered information via a received signal strength indication (RSSI) function, a memory to store data such as decoding/encoding functions, amplitude and phase settings to ensure a linear and stable output, and a timer to control the timing of operations, namely the transmission or reception of time-dependent signals.
• the signal processor and controller may be provided by the processor 202 and the receiver memory may be provided in the program memory 214.
• the antenna 222 comprises any known or developed structure for radiating and receiving electromagnetic energy in the frequency range containing the wireless carrier frequencies.
• the antenna 222 may be coupled to a switch that provides signal routing control of radio frequency (RF) signals in the device 200, as well as isolation between the transmitter circuitry 206 and the receiver circuitry 208.
• the switch could be replaced with a duplex filter, for frequency duplex devices as known to those skilled in the art.
• the buffer memory 216 may be any form of volatile memory, such as RAM, and is used for temporarily storing received information packets.
• the display 210 may be an LCD, OLED, or any other known display.
• the Input Device 212 may be one or more of: an alpha-numeric keyboard, isolated buttons, soft and/or hard keys, touch screen, jog wheel, or any other known input device.
• FIG. 3 A block diagram of a system using the device of Fig. 2 is shown in Fig. 3.
• the system 300 contains multiple communication devices 302, 304, 306, 308, 310.
• One of the devices 302 transmits to at least one of the other devices 302, 304, CMl 1 944
• This communication may be direct, i.e., device-to-device, or indirect, employing base stations 320 and other infrastructure 330.
• the devices 302, 304, 306, 308, 310 may be the same type of device (as shown, e.g., 302, 304, 306, 310) or different (as shown, e.g., 304 and 308).
• the receiving devices 304, 306, 308 receive the communication either directly (204, 308) or using one of the receiving devices 304 as an intermediary to forward the data to other of the receiving devices 306.
• the transmitter 206 of the device 200 employs a training algorithm to determine appropriate gain and phase adjustment parameters to ensure a stable, linear output from the transmitter during transmission of the real data.
• the transmitter employs a phase shifter architecture that is based on separate and independent in-phase (I channel) and quadrature (Q channel) phase rotation.
• I channel in-phase
• Q channel quadrature phase rotation
• I and Q signals are provided to a low pass filter 406, 408 and the low pass filtered I and Q signals are supplied to pairs of I and Q mixers 410, 412 and 414, 416 and to an up mixer 422 that converts the I and Q signals to transmission signals.
• the I and Q mixers 410, 412 and 414, 416 are also supplied with phase shift signals sin( ⁇ ), cos( ⁇ ) that are 90° out of phase.
• the mixed signals from each pair of mixers 410, 412 and 414, 416 are then combined at a respective I and Q summers 418, 420.
• the I summer 418 subtracts the sin( ⁇ ) mixed I component from the cos( ⁇ ) mixed I component to form F.
• the Q summer 420 adds the sin( ⁇ ) mixed Q component to the cos( ⁇ ) mixed Q component to form Q'.
• the F and Q' signals are provided to a down mixer 424. As illustrated, F and Q' are:
• the dual phase shifter architecture 400 of Fig. 4 has a number of benefits: it is wideband, reduces the number of frequency doublers (which are inherently relatively noisy) that are used in other architectures without dual phase shifting, and solves problems of other architectures related to IQ ambiguity during phase training because there is only one divide-by-2 quadrature generator and it is driven by a constant 2/ VCO signal.
• the dual phase shifter architecture of Fig. 4 while having significant advantages over other architectures, also engenders a new problem: a not- insubstantial amount of IQ imbalance is introduced due to the fact that the I and Q quadrature signals are shifted by separate mixers.
• phase shifts of both the I and Q channels are measured, a calculation is performed to determine the proper amount of adjustment, and then the adjustment applied, in the present architecture such a calculation is avoided (one phase shift is measured and the adjustment applied before the other measurement and adjustment - calculation to determine the proper amount of adjustment for both channels after both measurements are taken is avoided).
• FIG. 5 illustrates a block diagram of a dual phase shifter architecture of a transmitter 500.
• the transmitter 500 is supplied with analog baseband signals (I and Q signals).
• Each of the I and Q signals are respectively supplied to a summer 502, 512.
• the signal from each of the summers 502, 512 is amplified by a corresponding amplifier 504, 514 of predetermined or variable gain and then respectively passed through a low-pass filter 506, 516.
• the term amplifier is used through these embodiments, the amplifier can act as, or in conjunction with, an attenuator.
• the resulting low-pass filtered signals are then up-converted by a mixer 508, 518 supplied with signals at the desired frequency ( ⁇ ) from a local oscillator (LO) 560 and phase shifted by a 90° phase shifter 510 (i.e., either sin( ⁇ t) or cos( ⁇ t)).
• the upconverted signals are then combined at a summer 520, amplified by a power amplifier 522 of predetermined (or variable) gain and supplied to an antenna 540.
• a directional coupler 538 feeds a portion of the transmitted signal back to down- converting mixers 524, 526 where the fed-back signal is mixed with a phase-shifted CMl 1 944 version of the signal from the LO 560, which includes using a 90° phase shifter 542 to phase shift the local oscillator signal.
• the shifted signal from the phase shifter 542 and the signal fed to the phase shifter 542 are provided to individual I and Q channel phase shifters ⁇ i, ⁇ Q 544, 546.
• the signals supplied from the ⁇ i, ⁇ Q phase shifters 544, 546 have a respective phase imbalance ⁇ i, (X Q 548, 550 and are respectively supplied to the mixer 524, 526.
• each mixer 524, 526 is low-pass filtered by a low pass filter 528, 532 and then this feedback signal Q ft , I & respectively fed to a summer 502, 512 through a switch 534, 536.
• the switches 534, 536 are open in training mode and closed during normal operation.
• the feedback signals Qa, Ifb are also supplied to phase training module 530, which is used for SAR phase training and IQ imbalance correction and correspondingly controls the phase shift provided by the ⁇ i, ⁇ Q phase shifters 544, 546 using control signals supplied to the ⁇ i, ⁇ Q phase shifters 544, 546.
• the phase correction is made in real-time.
• a method of correcting IQ phase imbalance in the transmitter of Fig. 5 containing dual phase shifters is shown.
• multiple (as shown, two) phase trainings are performed to correct the IQ phase imbalance.
• the switches 534, 536 are open so that Cartesian feedback loop is open.
• a first training signal is supplied to the I and Q channel summers 502, 512 during a first phase training session at step 602.
• a training signal is defined by both in-phase and quadrature inputs.
• the SAR algorithm operates using a successive halving method in which a value representing the unknown phase shift is compared to a series of values representing predetermined phase shifts in a range of phase shifts. The range is divided into halves and the midpoint used to determine whether the unknown (in this case, ⁇ Q ) phase shift is larger or smaller than the midpoint.
• the unknown phase shift is repeatedly compared with a phase shift in a particular range of phase shifts, each range of phase shifts being a member of a predetermined set of phase shifts and being reduced with each successive repetition.
• an eleven digit binary number is selected and then converted into an analog signal by a digital-to- analog converter (DAC). The analog output is then compared to a value corresponding to the unknown phase shift.
• DAC digital-to- analog converter
• the SAR algorithm operates has ten steps, with the initial midpoint being 01111111111 and the next step being x ⁇ l 11111111 (where x can be 0 or 1 depending on whether the value representing the unknown phase shift is respectively smaller than or larger than the midpoint).
• the Qa signal during first phase training 602 can be described as:
• I ⁇ LPF ⁇ sin(2 ⁇ t - 0-(Jf 1 - Cc 1 ) - sin(-# + ⁇ z + Gi 1 ) ⁇ (9)
• I fb sm(- ⁇ + ⁇ I + a I ) (10)
• the IQ phase imbalance is now compensated at step 614 before the end of the allocated phase training period (predefined by the communication system used).
• the compensation data can be stored in a memory 214 of the transmitter 500 and updated as desired. Previous compensation data can also be used as an initial starting point for each of the I and Q channels in later phase training sessions.
• Training can be performed at a convenient time period after specific event such as after a programmed amount of operation time of the transmitter or absolute (wall clock) time.
• the switches 534, 536 are closed so that Cartesian feedback loops are closed for both the I and Q channels and the transmitter 500 now transmits data to other devices at step 616.
• the time allowed for phase training is limited. This becomes increasingly problematic if multiple phase trainings are to occur in this limited amount of time. To overcome this problem, it is recognized that in general the phase shift of the I channel will be fairly close to that of the Q channel.
• the final result of the first phase training ( ⁇ Q ) can be used as an initial condition for the second phase training. This permits the second phase training to perform only last few steps of the SAR algorithm, thus reducing total training time.
• the modified method of correcting IQ phase imbalance in the transmitter of Fig. 5 containing dual phase shifters is illustrated in Fig. 7.
• the switches 534, 536 are opened and a first input is supplied to the I and Q channel summers 502, 512 at step 702.
• the phase of the I channel ⁇ i is already somewhat close, only the last five steps of the SAR algorithm are used.
• the first six known digits of the eleven digit binary number determined during phase training of the Q channel are known and used, leaving the last five digits to be determined when training the I channel (e.g., taking about half the time as for the first training session for the second training session).
• phase training time so that phase training is able to be accomplished in, for example, the amount of time allotted by the TETRA standard. If further reduction is desired, fewer digits can be used during the second phase training, although this also limits the range of phase correction values able to be provided.
• the second phase training session is shorter than the first phase training session.
• the initial range of phase shifts at the start of the first training session is smaller than the initial range of phase shifts at the start of the second training session.
• the IQ phase imbalance is now compensated at step 716.
• This data can be stored in a memory 214 of the transmitter 500 and updated.
• the switches 534, 536 are closed so that Cartesian feedback loops are closed for both the I and Q channels and the transmitter 500 now transmits data to other devices at step 718.
• quadrature phase imbalance compensation has been applied in the down-mixed feedback path
• the compensation may be applied to in the up- mixed direct path as the phase imbalance is actually the sum of the up and down-mix I-Q generator imbalance.
• quadrature amplitude imbalance between the I-channel and Q-channels may be performed to ensure that there is minimal I-Q leakage.
• the disclosed methods may be implemented as a computer program product for use with a computer system.
• Such implementations may include a series of computer instructions fixed either on a tangible medium, such as a computer readable medium (e.g., a diskette, CD-ROM, ROM, or fixed disk) or transmittable to a computer system, via a modem or other interface device, such as a CMl 1 944 communications adapter connected to a network over a medium.
• the medium may be either a tangible medium (e.g., optical or analog communications lines) or a medium implemented with wireless techniques (e.g., microwave, infrared or other transmission techniques).
• the series of computer instructions embodies all or part of the functionality previously described herein with respect to the system.
• Such computer instructions can be written in a number of programming languages for use with many computer architectures or operating systems.
• such instructions may be stored in any memory device, such as semiconductor, magnetic, optical or other memory devices, and may be transmitted using any communications technology, such as optical, infrared, microwave, or other transmission technologies.
• a computer program product may be distributed as a removable medium with accompanying printed or electronic documentation (e.g., shrink wrapped software), preloaded with a computer system (e.g., on system ROM or fixed disk), or distributed from a server or electronic bulletin board over the network (e.g., the Internet or World Wide Web).
• some embodiments of the invention may be implemented as a combination of both software (e.g., a computer program product) and hardware. Still other embodiments are implemented as entirely hardware, or entirely software (e.g., a computer program product).

Landscapes

• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Physics & Mathematics (AREA)
• Nonlinear Science (AREA)
• Transmitters (AREA)
• Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Applications Claiming Priority (2)

Publications (2)

Family

ID=40672064

Family Applications (1)

Country Status (3)

Families Citing this family (3)

Family Cites Families (8)

• 2009
  • 2009-03-31 GB GB0905576A patent/GB2469076B/en active Active
• 2010
  • 2010-03-18 WO PCT/US2010/027744 patent/WO2010117582A2/en active Application Filing
  • 2010-03-18 EP EP10762078.3A patent/EP2415175A4/de not_active Withdrawn

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events