EP2405357A3 - Methods systems and apparatus for determining whether built-in-test fault codes are indicative of an actual fault condition or a false alarm - Google Patents

Methods systems and apparatus for determining whether built-in-test fault codes are indicative of an actual fault condition or a false alarm Download PDF

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Publication number
EP2405357A3
EP2405357A3 EP11172029.8A EP11172029A EP2405357A3 EP 2405357 A3 EP2405357 A3 EP 2405357A3 EP 11172029 A EP11172029 A EP 11172029A EP 2405357 A3 EP2405357 A3 EP 2405357A3
Authority
EP
European Patent Office
Prior art keywords
indicative
bitfc
fault condition
data sequence
determining whether
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP11172029.8A
Other languages
German (de)
French (fr)
Other versions
EP2405357A2 (en
Inventor
Joel Bock
Phil Scandura
Raj Mohan Bharadwaj
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honeywell International Inc
Original Assignee
Honeywell International Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell International Inc filed Critical Honeywell International Inc
Publication of EP2405357A2 publication Critical patent/EP2405357A2/en
Publication of EP2405357A3 publication Critical patent/EP2405357A3/en
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2215—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

Methods and apparatus are provided for determining whether a built-in-test fault code (BITFC) data sequence generated by a built-in-test (BIT) of a particular module of a complex system is indicative of an actual fault condition. A regression function is generated for the particular module based on stored BITFC data sequences generated by the BIT and stored repair data for that module from a fault history database. Later, during operation of the particular module, the BIT generates a new BITFC data sequence. A processor can then load the new BITFC data sequence and execute the regression function with respect to the new BITFC data sequence to determine whether the new BITFC data sequence is indicative of an actual fault condition at the particular module or is indicative of a false fault condition at the particular module.
EP11172029.8A 2010-07-08 2011-06-29 Methods systems and apparatus for determining whether built-in-test fault codes are indicative of an actual fault condition or a false alarm Withdrawn EP2405357A3 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/832,827 US8621305B2 (en) 2010-07-08 2010-07-08 Methods systems and apparatus for determining whether built-in-test fault codes are indicative of an actual fault condition or a false alarm

Publications (2)

Publication Number Publication Date
EP2405357A2 EP2405357A2 (en) 2012-01-11
EP2405357A3 true EP2405357A3 (en) 2015-10-21

Family

ID=44582147

Family Applications (1)

Application Number Title Priority Date Filing Date
EP11172029.8A Withdrawn EP2405357A3 (en) 2010-07-08 2011-06-29 Methods systems and apparatus for determining whether built-in-test fault codes are indicative of an actual fault condition or a false alarm

Country Status (2)

Country Link
US (1) US8621305B2 (en)
EP (1) EP2405357A3 (en)

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US8543870B2 (en) * 2011-02-14 2013-09-24 Nanya Technology Corporation Circuit for detecting and recording chip fails and the method thereof
US8797842B2 (en) 2011-03-10 2014-08-05 The Boeing Company Aircraft communication bus fault isolator apparatus and method
KR102650154B1 (en) 2016-12-08 2024-03-22 삼성전자주식회사 Memory device comprising virtual fail generator and memory cell repair method thereof
US10643187B2 (en) * 2017-06-09 2020-05-05 Kidde Technologies, Inc. Reporting and prioritizing faults for aircraft downtime reduction
US11195343B2 (en) * 2019-05-30 2021-12-07 The Boeing Company Maintenance systems enhancement
CN113127528A (en) * 2019-12-30 2021-07-16 中移信息技术有限公司 System root cause positioning method, device, equipment and computer storage medium
CN112630475B (en) * 2020-12-08 2023-11-07 湖南炬神电子有限公司 Ageing cabinet of electron cigarette and ageing system
US11281521B1 (en) * 2021-03-10 2022-03-22 Keysight Technologies, Inc. Methods, systems and computer readable media for troubleshooting test environments using automated analysis of log file data

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US20080215921A1 (en) * 2006-12-21 2008-09-04 Salvatore Branca Method, System and Computer Program for Performing Regression Tests Based on Test Case Effectiveness

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US5463768A (en) 1994-03-17 1995-10-31 General Electric Company Method and system for analyzing error logs for diagnostics
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Publication number Priority date Publication date Assignee Title
WO2001031449A1 (en) * 1999-10-28 2001-05-03 General Electric Company A method and system for estimating time of occurrence of machine-disabling failures
US20080215921A1 (en) * 2006-12-21 2008-09-04 Salvatore Branca Method, System and Computer Program for Performing Regression Tests Based on Test Case Effectiveness

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SATNAM SINGH ET AL: "Trends in the development of system-level fault Dependency matrices", AEROSPACE CONFERENCE, 2010 IEEE, IEEE, PISCATAWAY, NJ, USA, 6 March 2010 (2010-03-06), pages 1 - 9, XP031657191, ISBN: 978-1-4244-3887-7 *

Also Published As

Publication number Publication date
US20120011403A1 (en) 2012-01-12
US8621305B2 (en) 2013-12-31
EP2405357A2 (en) 2012-01-11

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