EP2404224A1 - Analog computation using numerical representations with uncertainty - Google Patents
Analog computation using numerical representations with uncertaintyInfo
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- EP2404224A1 EP2404224A1 EP10749214A EP10749214A EP2404224A1 EP 2404224 A1 EP2404224 A1 EP 2404224A1 EP 10749214 A EP10749214 A EP 10749214A EP 10749214 A EP10749214 A EP 10749214A EP 2404224 A1 EP2404224 A1 EP 2404224A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
- G06N3/065—Analogue means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N7/00—Computing arrangements based on specific mathematical models
- G06N7/01—Probabilistic graphical models, e.g. probabilistic networks
Definitions
- This application relates to analog computation using numerical representations with uncertainty, for example, as represented by soft bytes.
- Statistical inference can involve manipulation of quantities that represent uncertainty in numerical values. Statistical inference can make use of statistics to draw inferences based on incomplete or inaccurate information. Statistical inference problems can be found in many application areas — from opinion polling to medical research to telecommunications systems. The field of statistical inference encompasses a wide variety of techniques for performing this task.
- statistical inference problems involve extracting information from a measurement of data that has been corrupted in some way.
- a wireless receiver typically receives one or more radio signals that have been corrupted by noise, interference, and/or reflections.
- Statistical inference techniques can be used to attempt to extract the original transmitted information from the corrupted signal that was received.
- probability In statistical inference, the language of probability is often used to quantitatively describe the likelihood that a particular condition is true. The meaning of these probabilities can be interpreted in different ways, although these interpretations are sometimes interchangeable. For example, very generally, a probability can be interpreted either as the degree of confidence that a condition is true, or alternatively as the fraction of times the condition will be true among a large number of identical experiments. Probabilities can be represented in the linear domain, for example, as real numbers from 0 to 1 , where 1 is interpreted as complete confidence that the condition is true, and 0 is interpreted as complete confident that the condition will not occur.
- Probabilities can also be represented in the logarithmic domain, for example, using log likelihood ratios (or LLRs) representing the log of the ratio of the linear probabilities (the log odds).
- LLRs log likelihood ratios
- the LLR of a binary variable x is defined as the logarithm of the ratio of the probability of x being 1 and the
- LLR probability of x being 0, i.e., LLR(x) .
- complete certainty of a condition being true is represented by + ⁇
- complete certainty of a condition being false is represented by - ⁇
- complete uncertainty is represented by a value of 0.
- Some forms of belief propagation operate by passing messages between nodes in a factor graph that represents the system model, where each message represents a summary of the information known by that node through its connections to other nodes.
- One general aspect of the invention relates to a method of computation using numerical representation with uncertainty.
- the method includes accepting a specification of a group of variables, each variable having a set of at least N possible values.
- the group of variables satisfies a set of one or more constraints, and each variable is specified as a decomposition into a group of constituents, with each constituent having a set of M (e.g., M ⁇ N) possible constituent values that can be determined based on the variable values.
- the method also includes forming a specification for configuring a computing device that implements a network representation of the constraints based on the specification of the group of variables.
- the network representation includes a first set of nodes corresponding to the groups of constituents, a second set of nodes corresponding to the set of constraints, and interconnections between the first and the second sets of nodes for passing continuous-valued data.
- the computing device configured according to said specification is operable to accept a first set of quantities each characterizing a degree of association of one constituent of one of the group of variables with one of the M possible constituent values; and determine a second set of quantities each characterizing a degree of association of one constituent of one of the group of variables with one of the M possible constituent values by passing the first set of quantities and intermediate data along the interconnections in the network representation.
- Embodiments may include one or more of the following features.
- the specification for the computing device may include an analog circuit specification.
- the analog circuit specification may include a discrete-time analog circuit specification.
- the specification for the computing device includes software instructions for execution on a processor.
- the set of constraints on the group of variables may include a set of arithmetic constraints, a set of logical constraints, or a combination of both.
- the specification of the group of variables represents a compressed representation of a first specification of the variables.
- the specification of the group of variables may be formed based on the first specification of the variables.
- This first specification may include a probability distribution representation of the variables, which may be a continuous or a discrete probability distribution, or a probability distribution function of the variables.
- the specification of the variables is formed by applying binary decomposition to the probability distribution representation of the variables. In some other embodiments, it is formed by applying the Fourier transform to the probability distribution representation of the variables. [016] In some embodiments, the probability distribution representation of the variables includes quantities characterizing a degree of association of each one of at least some of the variables with the one or more of the at least N possible values. [017] The degree of association of one constituent of a variable with one of the M possible constituent values may be represented in the probability domain, or alternatively, be represented in the logarithmic domain.
- Another general aspect of the invention relates to a method including accepting a first set of quantities, each quantity being associated with one of M possible constituent values of a constituent of one of a group of input variables, each variable having a set of at least N possible values.
- Signals representing the first set of quantities are provided to computing circuitry implementing a network representation of a set of constraints on the input variables.
- the network representation includes a first set of nodes each corresponding to one of a group of constituents of a respective input variable, a second set of nodes corresponding to the set of constraints, and interconnections between the first and the second sets of nodes for passing continuous-valued data.
- the method also includes accepting, from the computing circuitry, signals representing a second set of quantities, each associated with one of M possible constituent values of a constituent of one input variable.
- Embodiments of this aspect may include one or more of the following features.
- the method also includes determining the first set of quantities from a first specification of the group of input variables, wherein the first specification includes quantities characterizing a degree of association of each of at least some input variables with a different one of the at least N possible values.
- the signals representing the second quantities a set of output is generated, with each output signal representing a degree of association of one of the group of input variables with a corresponding one of the at least N possible values.
- the computing circuitry includes analog circuits, which may include a clocked analog circuit.
- the clocked analog circuit includes soft logic gates for processing continuous-valued signals.
- the soft logic gates include one or more of soft Equal gates, soft XOR gates, soft AND gates, soft OR gates.
- the computing circuitry includes a processor configured by software instructions.
- Another general aspect of the invention includes a computing device having computing circuitry for applying a network representation of a set of constraints on a group of input variables, each input variable having a set of at least N possible values.
- the network representation includes a first set of nodes each corresponding to one of a group of constituents of a respective input variable, a second set of nodes corresponding to the set of constraints, and interconnections between the first and the second sets of nodes for passing data.
- the computing device also includes an input processor for forming signals representing a first set of quantities, each quantity being associated with one of M possible constituent values of a constituent of one input variable, and for providing the formed signals to the computing circuitry.
- the computing device further includes an output processor for accepting signals generated by the computing circuitry representing a second set of quantities, each quantity being associated with one of the M possible constituent values of a constituent of one input variable.
- Embodiments may include one or more of the following features.
- the interconnections between the first and the second sets of nodes may pass continuous-valued data, or alternatively, quantized and/or digitized data.
- the computing circuitry is configured according to the network representation. In some other embodiments, the computing circuitry is configurable according to the network representation.
- the computing circuitry is operable to accept a specification of the network representation of the set of constraints; and configure the circuitry to implement the network representation of the set of constraints according to the specification of the network representation.
- Some embodiments of the various aspects may include one or more of the following advantages.
- signals representing "a degree of an association” include signals that can represent a non-absolute measure, or a measure that is different from a mere binary decision of absolute association (true) or absolute non-association (false).
- Such signals may be continuous-valued signals, for instance, that can have levels corresponding to numerical values within the range of (0, 1) (non-inclusive) as well as extreme values 0 or 1, or be signals that have levels corresponding to a gradation of a range of numerical values that results in multiple quantized progressions.
- the degree of an association is presented by the signal as a probability representation in a linear domain (e.g., linear probabilities), a probability representations in a logarithmic domain (e.g., log odds, log likelihood ratios), or representations of certainty or likelihood that are not strictly probabilistic.
- a probability representation in a linear domain e.g., linear probabilities
- a probability representations in a logarithmic domain e.g., log odds, log likelihood ratios
- FIGs. IA- 1C illustrate a technique for constructing a soft processor that is configured to process the probabilistic information of a set of multi-state variables.
- FIG. 2 illustrates an example of forming a compressed representation of the original probability distribution of a 256-state variable.
- FIG. 3 illustrates an example of building a network of variable and check nodes that satisfies a set of two constraints.
- FIG. 4 illustrates an example of implementing belief propagation in the network of FIG. 3.
- FIG. 5 is a block diagram of an exemplary soft processor for solving magic square problems.
- Statistical inference problems are commonly found in a wide range of application areas, including telecommunications, speech and language processing, image processing, and data analysis.
- Some traditional approaches to solving statistical inference problems use a network of digital circuit components (e.g., logic gates) to implement belief propagation algorithms that operate by passing messages along the connections of those components.
- "Soft" information i.e., information representing uncertainty
- each message is represented by a digital signal that represents multiple bit numbers, with each bit number being transmitted, for example, via a separate bit line.
- An alternative approach to implementing belief propagation algorithms uses analog electrical circuits, in which case soft information representing a single value with uncertainty can be represented by a single analog signal (e.g., a voltage or a current-encoded signal).
- Some designs of analog circuits of soft logical functions e.g., soft Equals, soft XOR, and soft AND gates have been shown to be able to achieve a substantial reduction in power consumption and silicon area when compared with their digital counterparts.
- analog circuits that operate on probabilities of binary variables are described, for example, in U.S. Provisional Application No. 61/156,794, titled “Circuits for Soft Logical Functions,” filed March 2, 2009.
- each variable assumes two possible states, "0" and "1,” and the probabilities of one or more variables being at state “0” or “1” can be processed to infer the state of other variables.
- Exemplary use of such analog circuits in constructing analog belief propagation processor is discussed, for example, in U.S. Provisional Application No. 61/156,792, titled “Belief Propagation Processor,” filed March 2, 2009.
- a system includes at least two variables x and y , with x having N number of possible states and y having M number of possible states, where both N and M are greater than or equal to 2.
- An analogy in the digital domain would be to use a small number of binary bits to represent a variable with a very wide range of discrete values, and then perform bit operations on the binary bits which, in some examples, will only use log 2 as many resources as required in representing the original variable.
- FIGs. IA- 1C illustrate one general approach for designing a soft processor that processes the soft information of a set of variables having a finite number of possible states.
- each variable has 2 N number of states (this number is selected only for the purpose of illustration).
- N the number of states (this number is selected only for the purpose of illustration).
- one process to form the compressed representation of the probability distributions of these multi-state variables and to configure the corresponding circuit components operating on these compressed representations proceeds by adapting the general framework of a digital processor that operates on the same variables, as described in detail below.
- each operation OP k on three variables x, y, z can be described as:
- each operation OP k can then be translated into a corresponding binary- value operation BOP k that operates on the transformed variables, defined as: BOP k : T(x) x T(y) — > T(z) , where each transformed variable such as T(x) is defined as r(x) e ⁇ 0,l ⁇ .
- T(x) can be processed in the system as a string of M bits b o ,t ⁇ ,...,b M _ ⁇ , where M is typically smaller than 2 .
- the resulting T(x) has a length M equal to N .
- M can be either greater or smaller than
- T(x), T(y), T(z) providing a transformed representation of the original variables x, j, z .
- the "soft" values e.g., the probabilistic information
- T(x), T ⁇ y), T ⁇ z) provide a transformed (and possibly compressed) representation of the original probability distribution (continuous or discrete) or the probability distribution function of the variables x, y, z .
- the set of Boolean constraints B ⁇ 4 Ms transformed into a network of inter-connected nodes (e.g., based on a factor graph representation), where each node corresponds to a soft logical function of the information received at the node.
- the soft processor can be formed based on a network of variable nodes and check nodes where continuous-valued data is passed between the nodes.
- a circuit representing such a network can be formed using analog circuit components (e.g., soft logic gates), as described in the above-mentioned patent applications. Accordingly, soft values of the transformed
- T(z) T(x)
- each element of the T(x) vector can be referred to as a moment.
- a soft processor capable of operating on the soft information associated with variables of any number of possible states (not necessarily 2 ) can be constructed by identifying a set of constraints that the variables (or a transformed version of the variables) satisfy, and by subsequently turning the constraints into a network of soft logical components (or in some examples, a network of soft and hard logical components).
- Such an approach can be applied to construct belief propagation processors that pass soft information of binary or m-ary variables between its structural elements.
- the above approach can be used to construct a "soft" version of a digital processor whose operations are representable as a set of Boolean constraints.
- FIG. 2 shows one example of forming a compressed representation T(x) to represent the probability distribution of a 256-state variable x .
- each state of the variable x can be first represented by a corresponding 8-bit binary string of [ ⁇ o , ⁇ 1 ,...,& 7 ] by applying a binary transformation T .
- the probabilities of each bit of the binary string being 1 together constitute a set of 8 moments, each generated by applying a corresponding row M 1 of a mask matrix M to the original probability distribution of x , as shown below:
- the term "soft bit" is associated with the marginal probability that a bit is 1 (or 0).
- the binary string [O 05 O 1 ,..., ⁇ ] representing the variable x can be termed as a byte
- the resulting set of 8 moments [P(B 0 ), P(B 1 ), ..., P(B 7 )] can be termed as a soft byte.
- a byte generally refers to a sequence of bits (not necessarily a sequence of 8 bits)
- a soft byte generally refers to a sequence of soft bits (or moments).
- a soft processor that operates on various soft bytes can be constructed using soft logic components representing the corresponding Boolean constraints, where each moment (or each soft bit) can be processed as a continuous-valued signal.
- the mask matrix M used in the above example is not the only matrix that can be used to derive a set of moments representing the original probability distribution. For instance, one may use a similar set of periodic functions where the period of each successive function in the set is twice that of the previous function. Another example is a Fourier-based transformation. Other examples include a wavelet-based transformation, a transformation formed by a set of vectors from the rows or columns of a Hadamard matrix of suitable size, etc. In some examples, the application of the lowest frequency component of a mask function leads to the most significant bit (MSB) of a variable, whereas the application of the highest frequency component of a mask function leads to the least significant bit (LSB) of the variable.
- MSB most significant bit
- LSB least significant bit
- the mask function can be designed to have a mix of frequency components each with a different weight, thereby preventing the noise associated with a particular frequency component from dominating the outcome of the processing.
- the general approach to forming compressed representations described above is applicable to probability distributions that are sufficiently "sparse.” For certain sparse functions, a random mask may be sufficient to capture all of the information present in the function. In other words, the compressed representation, regardless of how it is derived, may provide a sufficient set of statistical information for the random variable in question.
- the choice of the representation described in FIG. 2 may be particularly useful, as it resembles a digital data structure but instead of using bits, now uses soft bits. Using soft bytes and soft words, one can build arrays of soft logic roughly analogous to digital logic with good performance. This approach can be further extended to form a soft version of any digital representation.
- the first type includes logical constraints — each entry need to be distinct (i.e., no repeated entries).
- the second type includes numerical constraints — various collections of entries (each row, each column, and each main diagonal) all sum to the same value.
- Table 2 shows a 4x4 magic square filled with variables X 0 through X 15 . Since the valid states of each variable lie in the range of 0 to 15, each entry can be represented by a string of 4 binary bits. All the rows, columns, and main diagonals need to sum to 30.
- variables X 0 ,...,X 15 will form a magic square if and only if they satisfy the constraints above.
- each variable can be represented as a string of 4 binary bits, these equality and non-equality constraints can be further expressed as restrictions on the individual bits of the variable using Boolean Logic.
- operator "+” represents addition over integers
- operator " ® " represents mod-2 addition (which corresponds to an XOR operation)
- operator " ⁇ " represents AND (logical conjuction)
- operator " v " represents OR (logical disjuction).
- Constraint #1 x p ⁇ x q for all p ⁇ q .
- each variable can be first denoted as a sequence of 4 individual bits: where a p ,b p ,c p , d p are all binary bits.
- X PqrS W where each one ofx p ,x q ,x r ,x s is a 4-bit string, each one of x pq ,x rs is a 5 -bit string, and x pqrs is a 6-bit string.
- each four-term summation can be reduced to a set of summations of pairs of variables.
- ripple adder it is possible to add the bit representations of two variables using only v , ⁇ and ⁇ operations (i.e., OR, AND and XOR).
- constraints #2-5 can also be expressed using a set of Boolean logic functions.
- FIG. 5 provides one example of a soft processor 500 configured for solving 4x4 magic square problems using some of the above-discussed techniques.
- the soft processor 500 is an integrated circuit including three components: an input transformation circuit 510, a belief propagation processor 520, and an output transformation circuit 530.
- the initial data specifying the variables are transformed by the input transformation circuit 510, which implements a transformation T to generate a transformed (possibly compressed) representation further specifying the variables.
- the network is configured using graph-based techniques and includes variable nodes and check nodes through which continuous-valued data (beliefs) are combined and updated iteratively according to the corresponding rules, for example, until the final beliefs converge. Further discussions of the belief propagation processor 520 is provided at a later section of this document.
- Those measures are provided to the output transformation circuit 530, which applies inverse of transformation T (or approximate inverse of transformation T) to determine measures of a degree of association of each original variable x ⁇ with its possible values 0 through 15.
- x 0 can be represented by a 4-bit string of (1, 0, 0, 1) (because a probability of less than 0.5 indicates that the bit is more likely to be a 0, and a probability of greater than 0.5 indicates that the bit is more likely to be a 1). Consequently, the 4-bit string is converted to a variable value of 9, which will be used as the final solution for x 0 .
- Sudoku is another example where the problem can be restated as a set of Boolean constraints.
- Sudoku consists of determining the values in a Nx N grid.
- each entry takes a number from 1 to 9.
- each one of the 9 numbers appears exactly once.
- the 9x 9 grid is partitioned into nine disjoint 3x 3 sub-grids, and each of the 9 numbers appears exactly once in each sub-grid.
- Sudoku problems can be viewed as easier than magic square problems in the sense that there is no numerical constraint involved. In fact, only logical constraints exist: the entries in each row, each column, and each sub-grid are distinct.
- each of the 81 variables of a 9x 9 Sudoku can be represented as a string of 4 binary bits.
- each variable in a Sudoku grid is represented as a string of 2 trinary (base-3) bits.
- base-3 the base-3 component-wise sum of two trinary variables, i.e.,
- each entry of the row can be represented by a string of 2 trinary digits, for example, (0, 0), (0, 1), (0, 2), (1, 0), (1, 1), (1, 2), (2, 0), (2, 1), (2, X).
- the constraint on these two entires can be expressed in analogy with the binary case (as illustrated in the magic square problem), except for the use of a minus sign:
- belief propagation relates to a message passing technique (or, more properly, a family of message passing techniques) that attempts to estimate, for instance, the marginal probabilities of the states of variables, by passing messages on a graph (e.g., a factor graph).
- a factor graph provides a network of nodes and edges that can encode the probabilistic and/or deterministic constraints of a system of equations.
- each variable is represented by a variable node and each constraint is represented by a check node (also referred to as a constraint node). Additionally, there exists an edge between a variable node and a check node if the variable appears in that constraint.
- One example of a factor graph representing this system includes a network of 5 variable nodes and 2 check nodes, as shown in FIG. 3.
- solving a belief propagation problem starts with the knowledge of prior information about the probability of a bit being a zero or a one.
- knowledge can be represented in the factor graph by adding a "half-edge," i.e., an edge attached to only one node.
- a message entering on the half-edge conveys the prior information.
- the first constraint can be implemented by a 3 -terminal soft XOR gate:
- bit is not necessarily limited to a binary digit. In some examples, it can be used to generally refer to a m-ary digit, where m ⁇ 2 .
- soft bit is not necessarily limited to the probabilistic information of a binary digit, but more generally, can be used to refer to the probabilistic information of a m-ary digit, where m ⁇ 2 .
- two or more analog signals are used to pass the belief that the m-ary bit takes on various of the m values. For example, m - ⁇ analog signals may be used to represent the soft information for an m-ary bit.
- an alternative approach is to transform the variables first to string of m-ary bits (e.g., trinary bits as illustrated in the above Sudoku example), and to subsequently determine the soft trinary bits to be processed in the soft processor.
- m-ary bits e.g., trinary bits as illustrated in the above Sudoku example
- Another application relates to using a small set of moments representing the original probability distribution of a multi-state variable to reconstruct quantities like the mean and variance of the original probability distribution, as discussed below.
- N moments of M(i) are sufficient.
- an additional set of 2N moments of V(J) is used.
- N moments where the value of each moment falls in the range of [0,1] .
- Some of the moments used above may be redundant.
- the redundancy can be found, for example, by examining the bit structure of the perfect squares. For instance, the parity of the low order bit alternates, hence
- V(I) M(I) [0117] Also, based on the nature of modular arithmetics, the second lowest order bit of a perfect square is always zero, so
- V (2) 0
- variables being processed by a soft processor appear to have the same number of variable levels (e.g., x, y, z all having 2 N possible levels as shown in FIGs. 1 A-IC), this need not to be the case in other examples.
- a soft processor may operate on a set of variables having different numbers of variable levels and for each variable, still form a transformed representation of its original probability distribution.
- the transformed representations of different variables may not necessarily include the same number of soft bits. For instance, one may have 3 soft bits whereas another may have 5 soft bits.
- the input variables to the belief propagation processor 520 shown in FIG. 5 may not have the same number of soft bits as the output variables.
- the belief propagation processor 520 may include intermediate variables that are computed based on its input variables but having different number of soft bits. For instance, it may be useful to compute an intermediate variable corresponding to the summation of two 3 -bit variables, in which case the intermediate variables may be a 4-bit variable and therefore need an additional soft bit as compared with the input variables.
- various techniques are provided for implementing statistical inference techniques in the analog domain to operate on variables having any finite number of states. Soft information can be represented using continuous-valued signals (e.g., current or voltage signals) and be processed in a soft processor. It should be noted in some other implementations of the statistical inference techniques, soft information may be represented and processed in alternative forms.
- One example makes use of stochastic computing techniques, in which case soft information, or sometimes continuous-valued quantities, can be represented by a stochastic bit stream. For instance, by introducing random (or pseudo random) dithering between two levels of 0 and 1, a quantity of 0.8 can be represented by a string of bits that overall has 80% of 1 's and 20% of O's. Accordingly, a soft bit or moment having a value between 0 and 1 can be represented by a "dithered" signal having a duty cycle (the percentage of times that the signal is 1) equal to the value of the soft bit.
- the belief propagation processor 520 can be modified to process dithered signals rather than continuous-valued voltage or current signals as described in the early sections of this document.
- ISI Inter-symbol Interference
- ISI inter-symbol interference
- the transmitted signals X 1 are either +1 or -1 (i.e. BPSK-encoded bits).
- a soft multiplier may be used. This can be built analogously with the soft adder. As with the soft adder, there are various ways of handling negative numbers; a similar technique of padding extra high bits works, although more extra bits may be needed. As with the soft subtractor, one can produce a soft divider by using a soft multiplier backwards.
- the input stream X 15 X 2 ,... is treated as unencoded.
- the input stream may be encoded, for example, with a convolutional code. Adding the constraints of a convolutional code to the factor graph can be implemented, for example, by adding another check node for each check equation and connecting it to equals node for each corresponding X 1 .
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TW201037529A (en) | 2009-03-02 | 2010-10-16 | David Reynolds | Belief propagation processor |
WO2011085355A1 (en) | 2010-01-11 | 2011-07-14 | David Reynolds | Belief propagation processor |
WO2011142840A2 (en) | 2010-01-13 | 2011-11-17 | Shawn Hershey | Design and implementation of factor graphs |
US8713414B2 (en) * | 2012-01-26 | 2014-04-29 | Telefonaktiebolager L M Ericsson (Publ) | Method and apparatus for soft information transfer between constituent processor circuits in a soft-value processing apparatus |
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US7877333B2 (en) * | 2006-09-06 | 2011-01-25 | D-Wave Systems Inc. | Method and system for solving integer programming and discrete optimization problems using analog processors |
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2010
- 2010-03-01 TW TW099105804A patent/TW201042549A/en unknown
- 2010-03-02 EP EP10749214A patent/EP2404224A4/en not_active Withdrawn
- 2010-03-02 CN CN2010800186890A patent/CN102362231A/en active Pending
- 2010-03-02 WO PCT/US2010/025940 patent/WO2010101933A1/en active Application Filing
Non-Patent Citations (3)
Title |
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PUXUAN DONG ET AL: "Implementation of Artificial Neural Network for Real Time Applications Using Field Programmable Analog Arrays", INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS, 2006. IJCNN '06, PISCATAWAY, NJ : IEEE OPERATIONS CENTER, PISCATAWAY, NJ, USA, 16 July 2006 (2006-07-16), pages 1518-1524, XP010948200, DOI: 10.1109/IJCNN.2006.1716286 ISBN: 978-0-7803-9490-2 * |
See also references of WO2010101933A1 * |
VIGODA B: "Analog Logic: Continuous-Time Analog Circuits for Statistical Signal Processing", INTERNET CITATION, 1 September 2003 (2003-09-01), page 209pp, XP007904886, Retrieved from the Internet: URL:http://media.mit.edu/physics/publications/theses/03.07.vigoda.pdf [retrieved on 2008-06-04] * |
Also Published As
Publication number | Publication date |
---|---|
WO2010101933A1 (en) | 2010-09-10 |
TW201042549A (en) | 2010-12-01 |
CN102362231A (en) | 2012-02-22 |
EP2404224A4 (en) | 2012-11-14 |
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