EP2382570A4 - REALIZING LOGIC OPTIMIZATION AND STATE SPACE REDUCTION FOR HYBRID VERIFICATION - Google Patents

REALIZING LOGIC OPTIMIZATION AND STATE SPACE REDUCTION FOR HYBRID VERIFICATION

Info

Publication number
EP2382570A4
EP2382570A4 EP10736234.5A EP10736234A EP2382570A4 EP 2382570 A4 EP2382570 A4 EP 2382570A4 EP 10736234 A EP10736234 A EP 10736234A EP 2382570 A4 EP2382570 A4 EP 2382570A4
Authority
EP
European Patent Office
Prior art keywords
state
performing logic
space reduction
logic optimization
hybrid verification
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP10736234.5A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP2382570A2 (en
Inventor
Ashvin M Dsouza
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Synopsys Inc
Original Assignee
Synopsys Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Synopsys Inc filed Critical Synopsys Inc
Publication of EP2382570A2 publication Critical patent/EP2382570A2/en
Publication of EP2382570A4 publication Critical patent/EP2382570A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3323—Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
EP10736234.5A 2009-01-28 2010-01-19 REALIZING LOGIC OPTIMIZATION AND STATE SPACE REDUCTION FOR HYBRID VERIFICATION Withdrawn EP2382570A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/361,282 US8104002B2 (en) 2009-01-28 2009-01-28 Performing logic optimization and state-space reduction for hybrid verification
PCT/US2010/021429 WO2010088102A2 (en) 2009-01-28 2010-01-19 Performing logic optimization and state-space reduction for hybrid verification

Publications (2)

Publication Number Publication Date
EP2382570A2 EP2382570A2 (en) 2011-11-02
EP2382570A4 true EP2382570A4 (en) 2013-11-27

Family

ID=42355198

Family Applications (1)

Application Number Title Priority Date Filing Date
EP10736234.5A Withdrawn EP2382570A4 (en) 2009-01-28 2010-01-19 REALIZING LOGIC OPTIMIZATION AND STATE SPACE REDUCTION FOR HYBRID VERIFICATION

Country Status (5)

Country Link
US (1) US8104002B2 (zh)
EP (1) EP2382570A4 (zh)
CN (1) CN101789035B (zh)
TW (1) TWI488063B (zh)
WO (1) WO2010088102A2 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9569574B1 (en) * 2014-03-07 2017-02-14 Altera Corporation Method and apparatus for performing fast incremental physical design optimization
CN109753714B (zh) * 2018-12-28 2023-03-21 中国人民解放军国防科技大学 基于知识库的覆盖数据通路边界情况的测试向量生成方法及系统
CN110688821B (zh) * 2019-09-27 2023-10-13 北京中电华大电子设计有限责任公司 一种复杂算法的测试激励生成器及其控制方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6975976B1 (en) * 2000-03-20 2005-12-13 Nec Corporation Property specific testbench generation framework for circuit design validation by guided simulation

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6182258B1 (en) * 1997-06-03 2001-01-30 Verisity Ltd. Method and apparatus for test generation during circuit design
AU3754100A (en) * 1999-03-19 2000-10-09 Moscape, Inc. System and method for performing assertion-based analysis of circuit designs
US6931611B2 (en) * 2001-12-19 2005-08-16 Freescale Semiconductor, Inc. Design verification system for avoiding false failures and method therefor
US6567971B1 (en) * 2001-12-20 2003-05-20 Logicvision, Inc. Circuit synthesis method using technology parameters extracting circuit
US20070299648A1 (en) * 2003-01-10 2007-12-27 Levitt Jeremy R Reuse of learned information to simplify functional verification of a digital circuit
US7711536B2 (en) * 2005-12-30 2010-05-04 Cadence Design Systems, Inc. System and method for verification aware synthesis
US7882473B2 (en) * 2007-11-27 2011-02-01 International Business Machines Corporation Sequential equivalence checking for asynchronous verification

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6975976B1 (en) * 2000-03-20 2005-12-13 Nec Corporation Property specific testbench generation framework for circuit design validation by guided simulation

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
See also references of WO2010088102A2 *
YUNSHAN ZHU ET AL: "Generator-based verification", IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN. ICCAD 2003. IEEE/ACM DIGEST OF TECHNICAL PAPERS. SAN JOSE, CA, NOV. 9 - 13, 2003; [IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN], NEW YORK, NY : ACM, US, 9 November 2003 (2003-11-09), pages 146 - 153, XP010677145, ISBN: 978-1-58113-762-0 *

Also Published As

Publication number Publication date
CN101789035B (zh) 2014-01-15
US8104002B2 (en) 2012-01-24
TW201040766A (en) 2010-11-16
EP2382570A2 (en) 2011-11-02
WO2010088102A2 (en) 2010-08-05
US20100192111A1 (en) 2010-07-29
CN101789035A (zh) 2010-07-28
TWI488063B (zh) 2015-06-11
WO2010088102A3 (en) 2010-11-25

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Effective date: 20131029

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