EP2374159A2

EP2374159A2 - Method for producing a dopant profile

Info

Publication number: EP2374159A2
Application number: EP09763962A
Authority: EP
Inventors: Jörg Horzel; Dieter Franke; Gabriele Blendin; Marco Jahn; Wilfried Schmidt
Original assignee: Schott Solar AG
Current assignee: Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Priority date: 2008-12-12
Filing date: 2009-12-03
Publication date: 2011-10-12
Also published as: CN102318086A; US9385263B2; US20110278702A1; WO2010066626A2; DE102008055515A1; TW201029056A; JP2012511819A; CN102318086B; JP5677973B2; WO2010066626A3

Abstract

The invention relates to a method for producing a dopant profile, which is based on a surface of a wafer-like semiconductor component (10), by introducing dopant atoms into the semiconductor component. In order to be able to manufacture semiconductor components with a desired dopant depth profile inexpensively, it is proposed that a dopant-containing layer be produced on or in a region of the surface first of all in order to produce a provisional first dopant profile and then a plurality of semiconductor components (10) which have a corresponding layer be subjected to heat treatment on top of one another in the form of a stack (26) in order to produce a second dopant profile which has a greater depth in comparison with the first dopant profile.

Description

Method for forming a dopant profile

The invention relates to a method for forming a dopant profile emanating from a surface of a plate-shaped or wafer-shaped semiconductor component by driving in dopant atoms in a thermal process. The invention also relates to a semiconductor component such as, for example, semiconductor components for the conversion of electromagnetic radiation or of light into electrical energy. The invention also provides a method for producing a planar plate-shaped or wafer-shaped semiconductor component having a dopant profile emanating from at least one surface.

It has long been known that with semiconducting materials it is possible to absorb photons - for example from the spectrum of sunlight arriving at the earth's surface - into semiconductor materials - such as silicon - and thus to create pairs of charge carriers that are in the presence of a semiconductor junction differently doped semiconductor regions, be it contiguous different semiconductor materials - can build a voltage between the differently doped semiconductor regions or semiconductor materials. If metallic contacts are suitably attached to the different semiconductor regions, an external circuit can be connected to these contacts and a continuous current flow through the external circuit can be maintained in the presence of sufficient photon flux to the semiconductor device. Crucial for the industrial production of such light in electric current converting semiconductor devices are the conversion efficiency of light energy into electrical energy and associated with the processing of semiconductor devices manufacturing costs.

It is known, silicon semiconductor plates with dimensions of z. B. 100-300 mm in the x and y direction and a thickness preferably between 50 microns and 500 microns as a starting material for the production to use. These semiconductor plates - also called wafers - are usually doped substantially homogeneously with a dopant for silicon. To make a semiconductor junction, a second dopant is applied to or transported to portions of the semiconductor plate surfaces or all semiconductor plate surfaces. For this purpose, various chemical substances, chemical and thermal methods and sputtering and ion implantation method in question to bring the dopant to the semiconductor plate surface and there to let penetrate into the semiconductor.

Usually, the dopant is driven from a dopant source in a single thermal process step into the silicon. It is crucial in the manufacture of semiconductor devices that are suitable for the conversion of photon energy into electrical energy, that a large number of devices per unit time can be made to keep the process costs per component low. Furthermore, it is customary to select the process for driving in dopants such that the volume of the semiconductor component is not heated beyond a certain limit temperature, since in silicon materials which are not monocrystalline and in silicon materials containing impurities and crystal lattice defects, high process temperatures are involved result in the lifetime of photon-generated minority mobile carriers being trapped in silicon by active interference centers caused by the temperature treatment, and recombining them in the initial energetic state without contributing to electrical energy production. Typically, the limit temperatures in the temperature treatment, above which the probability of recombination significantly increases, for monocrystalline silicon devices in the range between 950 ⁰ C and 1100 ⁰ C and non-monocrystalline silicon devices above 900 ⁰ C - 950 ⁰ C. The targeted Thermal drive-in of dopants is further controlled by the process time, the dopant concentration in the dopant source, and the atmosphere in the reaction space in which the process is performed.

For reasons of economy is in typical industrially manufactured semiconductor devices, which are suitable for the energy conversion of photons into electrical energy, with a single temperature treatment step, the z. B. over 5 min. up to 60 min. can persist, produced by the surface supplied with doping ago in the silicon interior down sloping dopant profile. Penetration depths for the dopant of up to 0.5 μm depth below the surface are customary. Up to this range, the dopant concentration drops very sharply until the dopant concentration is lower than the dopant concentration of the starting silicon material.

During the thermal treatment, dopant atoms of the dopant source have, on the one hand, a probability of penetrating into the silicon and, on the other hand, a probability of advancing a certain distance in the silicon by statistical processes within a certain time. The total penetration depth of the dopant atoms from the interface between the semiconductor component and the dopant source is thus determined by the factors time, temperature, dopant concentration in the dopant source, probability of penetration into the semiconductor component - in a corresponding atmosphere - and the mobility of the dopant atoms within the semiconductor component in the corresponding process conditions and Limited of the dopant source determined.

The starting concentration in the dopant source is chosen very high for industrially applicable processes. There are two main reasons for this. On the one hand, so far is a very high surface dopant concentration in the semiconductor device required in order to produce economically viable manufacturing processes conductive contacts with low contact resistance to the semiconductor material can. In most cases, metal pastes or electroless metal deposition processes are used to make contact with the semiconductor material through dielectric layers. On the other hand, a high dopant concentration in the dopant source and on the semiconductor surface is required in order to allow penetration of dopant by at least 0.2 .mu.m to 0.3 .mu.m penetration into the semiconductor in a single thermal process step and for reasons of economy of limited process time and parallel to it a doping film layer having a resistance <100 ohms / sq. to achieve without having to go to process temperatures of well above 900 ⁰ C. The minimum penetration depth is required in order to prevent impurities such as metal atoms from penetrating into the semiconductor junction during the burning in of the metal contacts, where they adversely affect the diode properties of the semiconductor junction (no recombination and leakage currents desired). The sheet resistance of the doped layer resulting from the penetration of dopant atoms should be small enough so as not to lead to significant series resistance losses during the transport of charge carriers in these layers.

In both cases, a relatively simple and economically interesting process sequence is possible, however, which requires the high surface concentration of dopants to allow low contact contact resistance and thus high conversion efficiency of the semiconductor device when converting light into electrical energy due to low resistance losses during transport To allow charge carriers.

At low output dopant concentrations such as <10 ¹⁹ dopant atoms / cm ³ z. B. a temperature of 1000 ⁰ C and a process time of 60 minutes when driving the dopant atoms is not sufficient to achieve these goals. However, a minimum conductivity of the doping layer and a minimum penetration depth of this doping layer is necessary in order to ensure that the following loss mechanisms are kept small when using conventional contacting methods for industrial semiconductor components of the type described: Losses due to series resistances in the area doped by thermal treatment (transport of the charge carriers towards the metal contacts), series resistance losses in the semiconductor-metal contact junction Shading losses due to metal contacts - these are limited in their minimum width and thus also in their optimal distance from each other -, Parallel resistive or Recombination losses due to impurities that can penetrate into the region of the semiconductor junction due to the metallization process used.

Losses due to recombination of minority carriers within the formed doping layer (in particular short wavelength portions of the spectrum of electromagnetic radiation that can be converted by the semiconductor device into electrical energy).

If it is not possible to minimize these losses sufficiently, basically no economically advantageous or competitive semiconductor components for the conversion of light into electrical energy can be produced.

According to the prior art, it has hitherto not been possible to produce semiconductor components for the conversion of light into electrical energy and at the same time to fulfill the following criteria:

To provide production processes and production equipment suitable for high throughput (averaged 1 wafer / s), surface doping of semiconductor plates having substantially homogeneous first doped output doping - n-type or p-type semiconductor - with one second dopant of opposite doping and at the same time achieving deep penetration depths for dopant atoms (at these deep penetration depths, the pn junction to the second dopant of opposite polarity is at least 0.3 μm, but better> 1 μm or even deeper below the surface), Achieve comparatively low surface concentration ("10 ²⁰ dopant atoms / cm ³ ), without having to go to very high process temperatures (> 900 ⁰ C),

Use of long process times to drive the dopants of several hours, without significantly increasing the production costs compared to typically much shorter processes, effective use of dielectric layers, at the same time for the passivation of defects in the surface and to significantly reduce the reflection at the Surface, effectively removing or rendering harmless of metallic impurities from the semiconductor device by accumulating these impurities during the high temperature treatment for driving the dopant atoms into the semiconductor plates from the surface and optionally subsequent removal (such as by etching away or oxidizing very highly doped regions of the doping layer ) from there accumulated metallic impurities.

There is hitherto no economically feasible method for driving in dopant atoms, which makes it possible to produce large-area semiconductor components for the conversion of light into electrical energy with a throughput of well over 1000 components per hour and for process times for driving the dopants of well over one hour allows. There are also no commercially available semiconductor components for the conversion of light into electrical energy available that have large areas diffused areas with a penetration depth of 1 micron and deeper. Furthermore, no semiconductor devices for converting light into electrical energy are currently available on the market, which use an emitter region on the light-receiving side, which has a P-surface concentration of well below 10 ²⁰ P atoms / cm ³ and with economic metallization processes (metal oxide ⁾ . Pastes) is contacted.

Commercially available semiconductor devices for converting light into electrical energy are subject to the requirement of economic and competitive These are manufactured at a cost that makes these products attractive to potential buyers when comparing the cost per performance of those products. At the same time, it is necessary to use methods which allow very large quantities of these large-area semiconductor devices to be manufactured per unit of time in order to survive in the market.

Under these conditions, almost all products available on the market currently make compromises that leave the efficiency potentials of the said semiconductor components for converting light into electrical energy unused in order to achieve cost advantages.

The vast majority of semiconductor devices currently used to convert light into electrical energy are fabricated on multicrystalline Si wafers with intrinsic defects and impurities. In particular, all crystalline silicon devices of this type with metal contacts on both surfaces (light-facing and lichtab facing side) have the following vulnerabilities: o High recombination losses in the emitter region of the light-facing side lead to loss of efficiency due to insufficient yield of sunlight in the blue region of the spectrum, o high Shading losses due to front side contacts, which lead to significant

Degradation of efficiency losses, o series resistance losses in the emitter, in the contact transition of the metal contacts to the emitter and in the line conductivity of the contacts, which lead to efficiency losses, o Lack of passivation of surface defects, which lead to efficiency losses, since a very high P - (= phosphorus) surface concentration is used o Inadequate process-related elimination or passivation of intrinsic impurities and impurities introduced externally during processing in silicon must be achieved in order to achieve acceptable contact resistance. This leads to recombination losses in the semiconductor device interior and the associated loss of efficiency, which in particular In the case of multicrystalline silicon materials, this can have a very drastic effect and severely limit the achievable efficiencies. The thinner the crystalline silicon semiconductor components are, the more achievable is the maximum achievable efficiency for thinner and thus less expensive semiconductor components by surface passivation. Significant losses in the coupling of Light in the crystalline silicon semiconductor device due to deficiencies in the surface structures or increased recombination losses in the emitter and pn junction in the case of very heavily doped emitters on a textured surface.

US Pat. No. 4,029,518 discloses a solar cell whose emitter consists of regions of different thicknesses. On the areas of greater thickness contacts are arranged.

The reference Szlufcik J. et al: "Low Cost Industrial Technologies Crystalline Silicon Solar Cells", Proceedings of the IEEE, Vol. 85, No. 5, May 1997, pages 711-730, describes methods for the cost-effective production of crystalline silicon These cells can have emitters of different thicknesses, whereby the thicknesses in the areas where contact fingers run are greater than in the adjacent areas.

From US-A-2007/0215596 a heating arrangement for treating silicon wafers arranged in a stack is known. Each individual wafer is positioned in a receptacle. The recordings are arranged one above the other and exposed to temperatures between 300 ⁰ C and 800 ⁰ C.

The present invention has the object, a method of the type mentioned in such a way that the inherent disadvantages of the prior art are avoided. In particular, it should be achieved that semiconductor components having a desired dopant depth profile can be produced cost-effectively and, in particular when using known systems, a higher throughput can be achieved, or, at a comparable throughput, a longer process time for driving the nozzle. Tierstoffatome is made possible to allow deeper penetration of the dopants in the semiconductor material.

It is also desirable to be able to easily contact the surface regions having the dopant profile without the regions not shaded by the contacts having a dopant concentration containing high levels of recombination-active impurities.

According to a further aspect of the invention, in the production of preferably a dopant depth profile having semiconductor devices to ensure that they are extremely flat after the heat treatment.

According to the invention, the problem is procedurally solved essentially by first forming a dopant-containing layer on or in a region of the surface and then subjecting a plurality of semiconductor components having a corresponding layer to one another in the form of a stack for forming the respective dopant profile of the heat treatment. In particular, it is provided that the layer is produced by forming an oxide film layer containing the dopant atoms or by ion implantation or sputtering of the dopant atoms.

Consequently, according to the invention, to form a provisional first dopant profile on or in a region of the surface of the semiconductor component, a dopant-containing layer is formed, in order then to subject a plurality of corresponding semiconductor devices to one another in the form of a stack to a temperature treatment step for driving the dopant atoms into the semiconductor , If a dopant depth profile has already been formed on the semiconductor component during the formation of the doping layer, then a second dopant profile having a greater depth than the first dopant profile is formed by the heat treatment in the stack. In other words, a first dopant profile is first formed in the individual semiconductor components. Then, corresponding semiconductor components each having a first dopant profile are stacked and stacked. A stack thus formed is then heat treated as a unit to produce in the respective semiconductor device a second dopant profile having a greater depth than the first dopant profile.

The second dopant profile may also be referred to as the final dopant profile. However, this also includes changes in the formed after the heat treatment in the stack dopant profile, if further temperature treatments or etching steps z. B. to remove impurities in the semiconductor material. In particular, under this aspect, there is also the possibility that in opposite sides, ie surfaces of the plate- or wafer-shaped semiconductor device layers are formed, which contain dopants. These not only cause the accumulation and collection of impurities from the inside of the semiconductor device during the temperature treatment, but protect the semiconductor material from the penetration of external impurities during the heat treatment.

In particular, it is envisaged that prior to arranging the semiconductor devices in a stack, each semiconductor device is heat treated such that volatile constituents present in the oxide film layer, in particular organic constituents, are removed or converted so that the subsequent heat treatment process performed in the stack ensures that the semiconductor devices do not adhere to each other and thus can easily be separated, so that damage is excluded. In a further development of the invention, it is provided that for forming the oxide film layer on the semiconductor device, for example, a liquid dopant source is applied or dopant is sputtered. In this case, the liquid dopant source can be applied to the semiconductor component by sputtering, spraying, atomization, evaporation, transfer printing, nip rolls with subsequent condensation or by dipping. However, it is also possible to apply the dopant source by a wetting process. Thus, the liquid dopant source can be applied to the semiconductor device via a transfer agent such as a roller.

In the case of a p-type silicon starting material, a phosphorus-containing solution, converted phosphoric acid solution and / or a phosphorus-containing sol-gel solution can be used as the liquid dopant source. It is also possible to apply a phosphorus-containing paste or sputter dopant such as, for example, P ₂ O ₅ . Thus, when the semiconductor substrate is made of silicon, a phosphosilicate glass film is formed as an oxide film layer.

On the other hand, if an n-type substrate of silicon is used as the base substance, boron-containing solutions may be used as liquid dopant sources, for example, so that a borosilicate glass film results as the oxide film layer.

Of course, the invention is not limited to silicon as the basic substance. Rather, all other semiconductor materials and dopants come into question, which are suitable for the production of semiconductor devices, in particular of semiconductor devices for the conversion of light into electrical energy.

According to the invention, a two-stage thermal process is proposed in which a first method step is characterized in that a temporally preliminary dopant depth profile at high process temperatures such as 500 ⁰ C to 1100 ⁰ C, preferably to 1000 ⁰ C is generated, and the near-surface substrate layer typical Features. According to the invention, a liquid dopant source on the Surface of the semiconductor device applied and dried in a first thermal step so that adjusts a preliminary dopant depth profile and the surface of the dopant source insensitive to damage by mechanical influences such. As scratching, rubbing and chemical influences such. B. moisture makes. In particular, the set property of the near-surface layer is characterized by the fact that sticking of this layer to other components is avoided as far as possible.

The preliminary or first dopant depth profile is characterized in that the preliminary profile enabling a separation of charge carriers has a depth T _v of preferably T _v ≦ 0.2 μm emanating from the surface of the semiconductor component.

During the first treatment stage, the semiconductor devices are isolated. In contrast, the semiconductor devices are coupled during the second heat treatment stage.

Even if the first treatment stage is preferably a heat treatment stage of the type described above, the preliminary profile can optionally also be produced at room temperature.

The drying of the dopant source of the plate-shaped semiconductor components such as components of multicrystalline silicon is carried out at temperatures above 500 ⁰ C, in particular in the range between 800 ⁰ C and 920 ⁰ C. Because of this first step, it is possible according to the invention to carry out the subsequent process steps, without that damage to the semiconductor devices or a hindrance of the penetration of the dopant atoms takes place. Thus, according to the invention in the subsequent process step, the corresponding heat-treated semiconductor components stacked to perform a further thermal treatment. By stacking there is the advantage that a particularly low-contamination production of Dotierstoff- depth profiles is given, with simultaneous economic method of operation; because of the stacking, it is possible to use process plants to achieve a higher throughput at the same residence time. In particular, however, the advantage is given to achieve a longer heat treatment at a comparable throughput, resulting in a higher penetration depth of the dopants. Alternatively, process systems can be used, which have a shorter overall length than those used previously used to achieve compared to the previous method, a same throughput at the same process time for driving the dopants. This also results in economic benefits.

In particular, it is provided that in a semiconductor component made of a multicrystalline silicon material as the basic substance, the oxide film layer formation at a temperature T ₁ with 500 ⁰ C <T ₁ <920 ⁰ C is performed. Furthermore, the semiconductor components in the stack are arranged relative to one another such that the semiconductor components lie substantially flat on one another. Irrespective of this, it is provided that in order to achieve a simple stack, the semiconductor components can be introduced into a centering housing.

In order to largely avoid or exclude damage, the particular semiconductor device to be deposited should, if possible, be deposited with its own weight on the already stacked semiconductor components when stacking the semiconductor components.

According to a variant of the teaching according to the invention, the stacking of the semiconductor components can take place in such a way that the stack forming runs inclined to the horizontal and the semiconductor components to be stacked are guided along the positioning aids to the stack.

A heat treatment of the semiconductor components present in the stack can take place in batches. A continuous procedure for forming the desired dopant profile is also possible.

In order to avoid contamination, the means by which the semiconductor devices come in contact during the heat treatment should be made of high-purity semiconductor materials. materials such as silicon, high-purity quartz and / or ceramic. About appropriate tools, the semiconductor components or the stack are supported or guided.

Regardless, the semiconductor devices should be stacked such that the density of the stack is substantially equal to the density of the semiconductor devices. This ensures that the semiconductor components lie flat against each other, so that the relevant heat treatment of semiconductor components taking place in a stack is used in order to avoid distortion of the individual semiconductor components, ie smooth or flat or at least less undulating after the heat treatment Semiconductor devices available to have.

The heat treatment in the stack is also distinguished by the fact that, in semiconductor components made of silicon, the number of crystal defects, in particular the number of dislocation lines, is significantly reduced by the heat treatment at a temperature T ₄ at 800 ° C. <T ₄ <1380 ° C. Furthermore, there is the advantage that in wavy semiconductor components made of silicon, which may have stresses and mechanical stress, the waviness or the stress in the silicon material is significantly reduced by the heat treatment at a temperature T ₄ at 800 ° C. <T ₄ <1380 ° C. ,

Furthermore, it is advantageous that the contact properties of the metal contacts of the semiconductor components are improved by the heat treatment in the stack arrangement in a Formiergasatmosphäre or other hydrogen-containing atmosphere.

When stacking semiconductor devices manufactured by the EFG method, the density of the stack should preferably be 0.5 to 0.2 times the density of the semiconductor device material.

The process according to the invention for the production of semiconductor components and the associated process engineering are in the context of a complete integral manufacturing process. process for industrial semiconductor devices to convert light into electrical energy.

The focus is on temperature treatment processes for driving in dopant atoms and subsequent treatment steps for the production of n-doped regions in p-doped semiconductor devices. However, the invention is in no way limited thereto. Other semiconductor devices or other dopants can be advantageously prepared with the described procedures and methods.

Among other things, semiconductor devices produced according to this invention are distinguished by the fact that they have comparatively deeply diffused regions at least on parts of the surface, which regions are produced in a comparatively large-scale industrial temperature-production process for driving dopant atoms.

The described method for driving dopant atoms in temperature processes for semiconductor devices allows two advantageous applications:

• On the one hand, the production throughput in existing production lines can be drastically increased without having to shorten the process time or to increase the plant size for the thermal processes for driving in the dopant atoms. At the same time, improved process purity and a larger process window can be achieved.

• On the other hand, it is possible to use significantly longer process times for driving in the dopant atoms while maintaining or even increasing the throughput of the production lines, without having to increase the length of process plants significantly or significantly increasing the process costs.

An essential feature of the invention is a temperature treatment method for driving dopant atoms into semiconductor components, which first of all preferably applies a dopant source to the surface or parts of the surface of semiconductor components in a first partial process step. For this purpose, various methods and dopant sources come into question, as these are known in principle from the prior art. These include, but are not limited to, phosphorus dopant sources such as phosphoric acid, converted phosphoric acids, sol-gel phosphorus compounds, POCl ₃ , P-containing pastes, sputtered P compounds such as P ₂ O _5, and other phosphorus compounds which are deposited via various deposition methods such as condensation, evaporation, Nebulization, drop-shaped spray coating, dipping method, sputtering method, printing method, writing method or sputtering on the surfaces or parts of the surfaces of the semiconductor device can be applied.

Instead of applying a dopant source to produce the dopant atoms containing layer, these may also be z. B. be introduced or driven by ion implantation of the dopant.

In a second partial process step, the dopant source thus applied is converted in a suitable temperature treatment step. In this case, under the effect of temperature-up to the process temperatures for driving in dopant atoms-volatile constituents of the dopant source are removed from the dopant source to an extent and a doping film is produced on the semiconductor component. The temperature-time profile in the conversion of the dopant source and the process atmosphere are chosen so that the resulting dopant layers meet the following process requirements and are optimized for it. Furthermore, this process is carried out in a process plant, which introduces no impurities, and in particular no metallic impurities, into the semiconductor components or contaminates the surfaces thereof apart from the dopants. When converting the dopant source into a suitable doping film, heating ramps, maximum temperature, cooling ramps, process gas atmosphere, process gas routing and exhaust air routing are to be designed so that the resulting doping films are sufficiently homogeneous, contain no impurities and are selectively removed from the process space under the influence of temperature of the dopant source without causing undesirable condensation or condensation drops on the semiconductor devices. In this sub-process, the surfaces occupied by the dopant source during the process are preferably not in contact with a transport system or carrier materials for the semiconductor devices.

In a third part-process step, the large-area semiconductor components are arranged in a stack one above the other or side by side. Thus, a very large number of semiconductor components are arranged on a comparatively small volume and with a small footprint (support surface). Consequently, the sum of the surfaces of the semiconductor surfaces is a multiple of the footprint of the stacked array. Thus, in a suitable thermal treatment furnace for driving dopant atoms (diffusion) on a comparatively small process footprint, very large numbers of semiconductor components per time unit can be processed. This can be implemented both in continuous processes for driving in dopant atoms and in (closed) process chambers therefor, which are charged and discharged.

In this case, the stack can be covered at its ends, ie end faces of cover plates, to prevent contaminants from penetrating. The cover plates can also serve to stabilize the stack.

The voluminally compacted arrangement of the semiconductor devices - rather than the prior art requiring large discrete distances of these semiconductor devices - very long process times and high throughput with acceptable process costs and acceptable production space requirements and acceptable process equipment costs are compatible.

With a suitable conversion of the dopant source in the preceding partial process step, the method additionally effects contamination protection for the semiconductor components and their surfaces. Due to the fact that the surfaces of the components lie directly on top of one another, these surfaces are largely protected from contamination by contact with furnace materials or from the transport of impurities through the gas phase to these surfaces. Additional protection is provided by the dopant layers on the surfaces, the impurities from inside the Collect semiconductor devices during the driving of dopant atoms and prevent contamination from the outside to penetrate into the semiconductor devices.

Thus, it is possible to adjust the process time and the process temperature for driving in dopant atoms as well as the corresponding heating and cooling ramps of the respective semiconductor material in very wide areas so that defects and impurities in the semiconductor material can be minimized by this thermal treatment step.

In particular, it is provided that in the method step previously referred to as the third sub-process step, which is in the actual sense the second essential process step of the present invention, the second dopant profile is formed, which should also be referred to as the final dopant profile, if one changes the dopant profile by subsequent optionally disregards required further temperature treatment steps or etching steps, in particular for removing impurities. A temperature treatment of the stacked semiconductor devices is preferably carried out over a period of at least 10 to 20 minutes to 24 hours, during which the semiconductor devices are maintained at a temperature which is preferably in the range between 800 ⁰ C and 1000 ⁰ C in multicrystalline silicon , The time means holding time. In general, however, it can be said that the second main process step, ie the heat treatment of the semiconductor components in the stack in a temperature range between T = 800 ⁰ C and T <T _s with T _s = melting temperature of the material of the semiconductor devices over a period t with 0 <t <24 h is performed.

In its own inventive embodiment to be emphasized, it is provided that, after the desired second doping profile has been formed, partially doped surface regions of the semiconductor component are removed. This is done in particular by etching or oxidation. This measure can ensure that a high dopant concentration is present in the areas not removed with the consequence that that in the required extent a good electrical contact can be made in conjunction with a front contact.

However, removal does not necessarily have to be physical. Equally effective is a conversion in the surface area such as oxidation.

The superficially reduced in the dopant concentration areas that are exposed directly to a to be converted into electrical energy radiation, have a low impurity concentration, since impurities such as metallic impurities store substantially only in highly concentrated areas during the entry of dopants by temperature treatment. Furthermore, the removal of doped regions also leads to a lower dopant concentration, since dopants can also be seen as impurities in the semiconductor. Due to the low impurity concentration and the unwanted recombination is reduced.

In other words, in a semiconductor device for converting light into electrical energy, the emitter layer is selectively removed or etched back, with the areas where the semiconductor material is removed usually serving for energy conversion and those remaining where the surface has not been removed is, a contact can be made with the front contacts. As mentioned, a high density of doping atoms is desirable for this purpose.

Furthermore, there is the advantage that in the areas in which the radiation to be converted by the semiconductor component is incident, impurities are removed by the selective removal of the surface.

Irrespective of the removal of the surface area, the effect of a corresponding semiconductor component for converting light into electrical energy is not adversely affected, since the dopant profile, ie the area with dopant atoms driven in from the surface, extends sufficiently deep into the semiconductor material due to the teaching according to the invention. Thus, it is possible to selectively remove regions of the previously diffused zones in a fourth sub-process step or in several necessary sub-process steps. Suitable for this purpose are etching processes or oxidation processes or ablation processes or combinations of these which specifically oxidize and / or etch and / or scavenge regions of the previously doped regions of the semiconductor components. These areas are areas with very high dopant concentration in the semiconductor and thus areas in which contaminants have preferably accumulated. These regions, together with the dopant source, are reproducibly etched away homogeneously or selectively so that emitter regions remain which have a comparatively low dopant concentration at least predominantly at locations which receive light.

To remove the doped surface regions, evaporation, in particular laser ablation, is also possible.

The dopant surface concentration c in the emitter should be in the range of 5-10 ¹⁶ to 10 ²⁰ P atoms / cm ³ , preferably between 10 ¹⁸ and 5-10 ¹⁹ P atoms / cm ³ , for example when driving in phosphorus after completion of the process chain , The depth of penetration of the emitter, ie the depth of the pn junction at a distance from the surface, then runs relatively deep and is then preferably larger than in typical industrial semiconductor devices for the conversion of light into electrical energy, in which the emitter depth in the range 0.3 to 0 , 5 microns is. According to the invention emitter depths are given in the range of between 1 .mu.m and 10 .mu.m, which allow a sufficient conductivity of the emitter regardless of the significantly lower P-surface concentration in the emitter. The depth of at least 1 micron refers to the surface of the semiconductor device, without any selective removal of the emitter, either by physical removal, be it by z. B. oxidation. In the regions in which regions of the emitter layer were previously removed, the effective depth of the emitter layer preferably extends to a range between 0.3 μm and 9.7 μm, in particular in the case of a semiconductor component which consists of silicon as the base material. For this information, it is assumed that the thickness of the emitter layer should be at least 0.3 μm. The thickness d of the respective removed layer is preferably 0 <d <0.3 .mu.m, regardless of the other parameters mentioned above. The remaining emitter thickness should preferably be> 0.3 μm.

Obviously, the invention is not limited to semiconductor devices that consist of a multicrystalline silicon substrate. Rather, a monocrystalline material such as silicon can be used. In this case, for the formation of the preliminary dopant profile, a heat treatment z. B. over a period of about 10 minutes at a temperature of about 1100 ⁰ C take place. In this case, effective penetration depths of the dopants form up to approximately 2 μm. After completion of the heat treatment of the arranged in the stack semiconductor devices, ie after the second heat treatment step, the effective depth amounts to 5 microns or more, preferably a Oberflächendotierstoffkonzentration in the range of 10 ¹⁸ to 10 ¹⁹ atoms / cm ³ as final surface concentration after completion of Semiconductor device should be sought.

Of course, all these values are exemplified, without this being intended to limit the teaching according to the Invention.

It should also be noted that the periods indicated for forming the preliminary dopant profile basically include heating and cooling.

Advantages of lower dopant concentration emitters are higher charge carrier carrier lifetime, which is produced by absorption of light in the emitter region. Together with an improved Oberflächenpas possible on such surfaces with lower dopant concentration thus semiconductor devices can be produced with improved light output for short-wave portions of the convertible solar spectrum. But also for medium- and long-wavelength light components, an improved light output is to be expected because the parasitic absorption of these portions of the solar spectrum in the emitter region is reduced by the lower dopant concentration and thus more complete these light components penetrate into the volume of the semiconductor device and there can contribute to increased generation of minority charge carriers. In addition, it is possible with the longer process for driving Dotierstoffatmomen at relatively lower temperature effective impurities from the interior of the semiconductor device initially enriched in highly doped regions of the emitter and then optionally etched away with these areas of the emitter away or convert. All these advantages are not available in the state of the art.

Alternatively, the above-described advantageous low p-surface concentration, high-penetration emitters may also be made by removing the doping layer from the semiconductor surface after the substep step of converting the dopant source, and only dopants already incorporated into the semiconductor by that time are driven deeper in the subsequent stacking process for driving in dopants.

According to the invention, it is possible to selectively remove emitter layers. The areas where partial removal of emitter regions including transformation does not occur have a high dopant surface concentration and are very deeply diffused. These areas can be contacted with low contact contact resistance. The remaining regions of the emitter, which are intended to convert sunlight into electrical energy, selectively have emitters with substantially low dopant concentration but relatively low dopant penetration depth, allowing for a better yield of short wavelength portions of the useful solar spectrum. According to the invention, a masking step for the light-receiving side of the semiconductor components for converting photons into electrical energy should be used for producing corresponding selective emitters after the actual driving in of dopants in the wafer stack, which at least partially covers the areas to be contacted later in the process sequence or completely and moreover masked and left unchanged when etching back the other emitter areas. It is basically simple to make good contacts with low contact junction resistance to emitters with very high dopant surface concentration. The problem with the contacting of selective emitters is usually to reproducibly align the areas in which the dopants were deeply driven during the heat treatment in the stack, and the metal contacts to each other in mass production processes, so that the weaker doped regions of the selective emitter, the lower Dopant surface concentration, not be contacted by the metal contacts. Usually, such areas, which are not suitably aligned with one another, entail considerable risks of drastically reducing the maximum achievable efficiency, since recombination losses due to impurities in the pn junction and possibly even short-circuit paths can occur when low-penetration emitters are contacted ,

In the case of the deep emitters provided with low dopant surface concentration according to the invention, however, this probability is significantly reduced, since in emitter regions with low dopant surface concentration still comparatively deep penetration depth of the dopant profile in the production of metal contacts with metal pastes compared to highly doped Emitterbreichen It is to contact, there is hardly any deterioration of the emitter takes place and impurities do not reach the semiconductor junction due to the low execution of the emitter. Thus, a selective emitter made in this way becomes much less sensitive to perfectly aligning emitter regions with high dopant surface concentration to the metal paste contact regions. This results in a relatively large process window that tolerates deviations and inaccuracies in the alignment of the areas to each other.

In order to be able to carry out the process sequence provided according to the invention when driving dopant atoms starting from surfaces of the semiconductor components, plant techniques described below can be used which have their own inventive content and can be used for driving in the dopant atoms dissolved from the process according to the invention. In that regard, the Plant characteristics, even if they are explained below in connection with the method according to the invention, to evaluate for themselves inventive.

For the production of semiconductor devices according to the invention, various production plants are necessary. In this case, for subprocess steps such as the application of the dopant source and the suitable conversion of the dopant source into an adequate doping film or oxide film containing the dopant or dopants, various production facilities can be used, which already belong to the prior art. Essential within the meaning of the invention, however, are systems engineering and associated process engineering for forming stacks of large-area semiconductor components which permit a very high sum of the surfaces of the large-area individual semiconductor components placed in the stack in very narrow volumes. This method and the associated plant technology are characterized in that semiconductor components are taken over without damage from a previous process and compressed into a stack, the atoms through suitable handling technology in a thermal system for driving dopant atoms in semiconductor devices bring in as possible without damage and can be removed again , Furthermore, this includes a system technology that separates the large-area semiconductor components from the stack arrangement again, without damaging the semiconductor components.

For the formation of the stack arrangements, suitable aids are used which ensure that the stack arrangement formed in this way can be produced in a reproducible manner such that the arrangement can be handled and there is no relative movement of the semiconductor components with one another. Furthermore, the shape of the stack arrangement must be such that during the actual manufacturing process for driving dopant atoms into the semiconductor components there is no significant displacement of the semiconductor elements with each other and no damage or contamination of the surfaces and that the stack arrangement can be resolved again after completion of this high-temperature process, without Damage semiconductor devices or to be able to perform this with the desired cycle time and positional loyalty again as individual components of the next production plant. For handling s systems come various automated handling systems in question, which can record wafers on low-damage gripping mechanisms and store them true to position, and transport routes that automatically align semiconductor devices via conveyor lines in the desired stack shape. It is important not to damage, scratch or contaminate the semiconductor device surfaces. It is also possible to use automated grippers or other known separation mechanisms in order to separate the large-area semiconductor components after the driving in of dopant atoms from the stack arrangement. Again, there must be no damage to the surfaces.

In order to stabilize the stack-like compacted arrangement of semiconductor devices in the transfer or loading of these structures in a suitable furnace for driving the dopant atoms, during transport through this furnace or during unloading and transfer to the next system in their shape and the respective outer large-area semiconductor devices - depending on the arrangement : top and bottom semiconductor device or foremost and rearmost semiconductor device - to protect, it is advantageous and for the purposes of this invention to use shaping or shape-stabilizing components, with the help of the stack-shaped arrangement can be transported simplified. In the simplest case, these are plates above and below a vertically stacked arrangement of large-area semiconductor components. Likewise, however, housings for the stapeiförmige arrangement (transport boxes) can be used. In this case, it is also possible, for example, to arrange the large-area, comparatively thin semiconductor components predominantly vertically resting on their edges next to one another. Decisive in the choice of transport aids, which are to stabilize the stack, is the choice of materials, which must help ensure that there are no unwanted impurities in the semiconductor devices or on their surfaces. Furthermore, the transport aids must not adversely affect the temperature homogeneity on the semiconductor components during the driving in of dopants, starting from the dopant sources on their surfaces, but should rather improve the temperature homogeneity. In particular, it must also be ensured that all large-area semiconductor components during the temperature treatment for driving in the dopant atoms have substantially the same temperature despite the transport aids. experience temperature-time courses. The selection of materials is thus limited to materials which are compatible with high-purity thermal processes at high process temperature or with processes for driving in dopant atoms in semiconductor devices of the respective genus. For this come in Si semiconductor devices pure ceramic materials such. B SiC, Al ₂ O ₃ , quartz or semiconductor materials such as silicon in question. The design must be adapted to the requirements of the temperature homogeneity and the requirements for damage-free transport of the stack arrangement. If, in particular for the transport aids, highly pure semiconductor material of the same type as the semiconductor components to be processed is used, there can be no appreciable relative movements between the stack arrangement and transport aid components due to different thermal expansion coefficients. Furthermore, the arrangement should be able to be handled by automated handling technology.

Preferably, the stack assemblies with the large area semiconductor devices should be processed in continuous high temperature processing furnaces. In arrangements of up to 100 semiconductor device plates stacked one above the other, it has been found that the temperature homogeneity in typical processes for driving dopant atoms with moderate heating ramps and a longer hold time of more than 10 minutes, in particular more than 60 minutes, at the respective maximum process temperature for driving the dopant atoms rather improved when the semiconductor devices are processed in the stack assembly instead of as individual parts. Furthermore, the process time for driving in the dopant atoms could be extended without reducing the throughput of semiconductor devices in this process step for driving in the dopant atoms. On the contrary, it has been shown that significantly higher throughput and / or significantly increased process times are possible and the efficiency of the semiconductor components produced at the end of the process chain for converting light into electrical energy can be increased. This can be attributed on the one hand to the increased process time when driving in the dopant atoms and the associated advantages in minimizing electrically active impurities in the semiconductor. On the other hand, the arrangement provides inherent protection against external contaminants in the oven. This is especially true in furnace arrangements such as continuous high-temperature furnaces for driving dopant atoms in semiconductor devices with metal mesh belts for transporting the components, but also in other types of furnaces, which can lead to contamination in semiconductor processes by the wafer transport or components in the oven.

Ideally, however, for the purposes of this invention, the stacking arrangements with their respective high-purity transport aids are transported through a continuous high-temperature furnace such that no components with contamination risk in the heated process interior of this furnace must be located to drive dopant atoms in semiconductor components. Since the choice of materials for the transport of semiconductor device stack arrangements is very limited, a preferred furnace design is a continuous furnace whose process space is delimited by a quarternary tunnel from the heating elements located around it. The transport through this process space can, for example, be carried out with a lift-and-run conveyor system which uses, for example, long rods or tubes made of highly pure materials suitable for semiconductor processes (quartz, SiC, high-purity ceramics). The rods or tubes extend through the entire heated process space and are moved synchronized outside of this process space on adequate conditions. In this case, each stack arrangement is supported with the possibly associated transport aids at any time by at least one rod or two tubes. These rods or tubes can be moved along the desired transport direction through the interior of the oven (striding) and vertically (lifting movement). If the wafer stacks are not to be discontinued in the interior of the oven on support surfaces for a short time, at least two additional rods or tubes are necessary. These should also be moved synchronized in parallel. With such an arrangement, it is thus possible to carry out in each case a forward movement for the semiconductor components in the desired transport plane. After a defined forward movement about the distance Xl, the second arrangement is raised with rods or tubes after they have previously been moved on a plane below the transport plane by the distance -Xl in the opposite direction to the transport direction. Upon reaching the transport plane through the second arrangement of rods or tubes, the respective stack arrangement is now symmetrical to the center of the Stack arrangement supported and the first arrangement with rods or tubes can be lowered again.

In the subsequent step, the stacked devices with semiconductor devices are again advanced by the distance Xl while the first array is retracted by rods or tubes on the lowered plane by -Xl. At the end of the route again takes the first arrangement with rods or tubes stack the symmetrical to its center at the level of the transport plane and the second arrangement with rods or tubes is lowered. With this stroke-stepping principle, it is possible to convey stacked arrangements of semiconductor devices at a uniform speed almost continuously through the process space.

Alternatively, the stack arrangement can be placed in the oven for a short time in the oven on suitably mounted bearing surfaces after the walking movement, while the stack supporting rod (s) or tubes are withdrawn against the transport direction again.

The transport rods or transport tubes, which are each in contact with the stacked arrangement of the semiconductor devices, do not contaminate the assembly and do not make any relative movement to the stack assembly. Because these supports are transported only a comparatively short distance in the furnace forward and then back again, these components do not have to be heated continuously, but are almost stationary at the same temperature. This promotes temperature homogeneity during transport of the stack arrangements and largely avoids parasitic heating power for the transport mechanism. By this construction, the kiln length is limited to the length of the high purity bars or tubes that pass through the interior of the kiln. However, since it is possible to transport stacks of semiconductor devices side-by-side on multiple lanes and to transport the stacking arrays of up to 200 or even more semiconductor devices on a comparatively small footprint (not or slightly larger than the single plate semiconductor device), it is possible, with a heated oven length of a few meters and a process time in the range of, for example, 1-5 hours to achieve a typical throughput of several thousand semiconductor devices per hour.

In high-temperature furnaces with metal braided belts used so far for driving dopant atoms into semiconductor components for converting light into electrical energy, even at a typical throughput of a large-area semiconductor device per second, process times (at maximum constant temperature for driving dopant atoms) of up to one day without increasing the oven length, as long as only the stack arrangement comprises a sufficient number of semiconductor devices (eg ~ 350 pieces). So far, typical process times for such throughput are about 10 minutes.

It is also possible to use so-called discontinuous high-temperature furnaces for driving the dopant atoms into semiconductor components, in which the stack arrangements are loaded, then the process is carried out in a large process chamber, and finally the furnace is discharged again. High-purity chamber furnaces are suitable for this purpose, for example.

A continuous high-temperature treatment furnace for driving dopant atoms into semiconductor components offers the advantage that, in principle, each semiconductor component passes through the same temperature profile and the heating power remains virtually constant.

Another advantage of the described method, which allows for long process times in the driving of dopant atoms in the range of hours when processing stacked arrangements of semiconductor devices, is that semiconductor materials with strains and irregular, wavy surfaces such as EFG silicon (edge defined film). Fed growth) or other so-called strip-drawn silicon materials or film silicon materials can be reduced by the long thermal treatment in the ripple, so can be smoothed and thus relaxed or reduced thermal stresses of the previous process. can be changed. Here is a self-inventive idea to see, so detached from the process steps according to the invention for driving dopant atoms in semiconductor devices.

Experiments have shown, for example, that the waviness of the individual Si substrates is reduced in stacks of wavy EFG-Si substrates. In this case also the force plays a role, with which the substrate surfaces in the stack arrangement are pressed against each other or each other. Particularly in the case of substrate stacks lying horizontally on top of one another, the number of substrates in the stack and the mass of possibly lying transport aid components are of importance. Preferably, therefore, up to 200 to 300 semiconductor elements should be stacked horizontally one above the other to form a stack and above this have a plate made of semiconductor material, which complains the stack and avoids the slippage of the components.

A further preferred application provides that after the first temperature treatment step in which a dopant-containing oxide layer is formed on the semiconductor device surfaces, this oxide layer is removed, so that in the subsequent temperature treatment step for driving dopant atoms in a stack arrangement only dopant is further driven, which was already introduced in the semiconductor device previously (first temperature treatment step). As a result, even during the driving in of the dopant profile in the stack arrangement, the surface concentration of dopants can be significantly reduced and a deep dopant penetration depth profile can be generated, as described above as being advantageous. Thus, for example, without etching processes that remove parts of the semiconductor material, it is possible to achieve dopant surface concentrations for, for example, phosphorus, which are 10 ¹⁸ - 10 ²⁰ P atoms per cm ³ , although previously a dopant source with a much higher dopant concentration was used For example, after the first temperature treatment step, dopant concentrations of »10 ²⁰ P atoms / cm ^{3 have driven} into the semiconductor device surface. The removal of the dopant source or of the so-called dopant silicate glass in the case of silicon semiconductor components is preferably carried out in hydrofluoric acid (HF) or fluorine compounds which are capable of releasing fluorine ions, containing chemical solutions or steam treatment. Hangs s procedure carried out. For this purpose, continuous flow systems with roller transports are particularly suitable for wet-chemical processing of the semiconductor components.

A further advantageous variant of the teaching described here is to apply dopant sources both on the light-receiving side of the planar semiconductor component for converting light into electrical energy (solar cell) and on the opposite side in order to subsequently drive dopants into the semiconductor component to be able to. In particular, in the case of multicrystalline semiconductor components such as, for example, multicrystalline silicon or strip-drawn silicon (EFG, string ribbon, RGS etc.), impurities in the semiconductor material can be effectively collected from all surfaces provided with diffusion sources during the driving in of the dopants and thus made harmless. The probability of removing impurities in the semiconductor material thus increases considerably. In this case, it may be helpful, after driving in the dopants from the surfaces, to partially or completely remove the area of the semiconductor component doped in one of the following process steps. This is necessary, for example, if the light-receiving side of the semiconductor device for converting light into electrical energy is ultimately to receive a different doping than the opposite side, but initially the same dopant was driven on both sides to more effectively remove contaminants from the semiconductor device ,

Irrespective of this, the density of the stack may possibly be approximately equal to the density of the semiconductor components, that is to say a flat superimposition of the semiconductor components is ensured in order to achieve the desired smoothing. In other words, the stack density may be about 2.3 g / cm ³ , as long as the plate-shaped semiconductor devices are silicon ones.

Are z. For example, if semiconductor devices manufactured by the EFG method are stacked, then the density of the stack should preferably be approximately 0.5 to 0.2 times the density of the wafer material, thereby ensuring, regardless of the waviness present. is that the wafers do not break. At the same time, however, due to the taking place in the stack temperature treatment of the wafer results in a reduction of the ripple, so a smoothing.

In addition to the applications for driving in dopant atoms and for smoothing wavy band-drawn multicrystalline silicon semiconductor devices (such as EFG-Si), other temperature treatment methods are suitable in which a stacked arrangement of the semiconductor components offers a considerable advantage since very long process times can be used and Nevertheless, with suitable temperature treatment systems and suitable number or compression of the stacked semiconductor components in the process space, very high throughput of the semiconductor components can be achieved. Thus, hitherto not economically feasible long temperature treatment steps are interesting for the industrial mass production of semiconductor devices for converting sunlight into electrical energy.

Such a temperature treatment step, for example, a method in which the semiconductor devices are subjected to the driving of dopant atoms at typical process temperatures of 800 ⁰ C - 1100 ° C a further temperature treatment at about 500 ⁰ C - 800 ⁰ C. In this temperature range, the already driven dopant atoms are not driven much further into the semiconductor devices. However, it is from the literature [M. Rinio et al., Proc. 23rd EPVSEC, pl014 (2008)]; [T. Buonassisi et al. NREL Workshop on Crystalline Si Solar Cells and Modules (2007)] discloses that such additional temperature treatment steps lead to the improvement of the material quality (higher minority carrier lifetime) of contaminated or crystalline semiconductor devices. It is also known from the literature that long process times are advantageous.

Furthermore, it is from the literature [B. Sopori; Dehli, India, November 1999, NREL / CP - 520 - 27524 "Impurities and Defects in Photovoltaic Devices ..." it is known that very long temperature treatments (up to 1-2 days) can be achieved at comparatively moderate temperatures in the semiconductor device as precipitate Cluster existing impurities are released from the precipitate cluster and become mobile as an interstitial contamination in the semiconductor and thus collected on the surfaces of the semiconductor devices by the dopant enrichments, or even in subsequent process steps such as etching can be removed. In this context, moderate temperatures are temperatures below typical temperatures which are used in the industrial production of semiconductor components for converting light into electrical energy in order to drive in dopant atoms from a dopant source applied to surface regions into the semiconductor components by means of this temperature treatment.

A further advantageous application example for high-temperature treatment steps in stack-like arrangements of the semiconductor components is likewise a method already described in the literature [K. Hartmann et al., Appl. Phys. Lett. 93, 122108 (2008)], in which semiconductor devices such as multi-crystalline Siliziumwa- fer or ribbon drawn Si wafer (ferschneiden crystallization and Wa) according to the preparation thereof are subjected to a further high-temperature treatment step (typically at temperatures between 1100 ⁰ C and the melting point for the semiconductor devices) to significantly reduce crystallographic defects such as dislocation lines. Here too, long process times and high throughput are advantageous and indispensable for developing industrially applicable processes. In parallel, thermal stresses in the semiconductor component are healed or significantly reduced in such temperature processes well above 1000 ° C. and the long process times. Parallel to this, wavy surfaces, which are common with strip-drawn multicrystalline silicon materials (eg EFG), can be made almost completely flat by the stacking treatment. This offers considerable process advantages in the further process chain for semiconductor components for the conversion of light into electrical energy. The breakage rate in subsequent processes for the semiconductor components can thereby be significantly reduced.

Yet another advantageous application example for the processing of semi-finished semiconductor components for the conversion of light into electrical energy in stacked arrangements is the execution of a so-called forming gas. Anneal (FGA). The semiconductor components already provided with sintered metal contacts are exposed to a hydrogen-containing gas atmosphere. Usually, a mixture of an inert gas such as nitrogen or argon with hydrogen is used for this purpose. The proportion of hydrogen is chosen so that at the corresponding process temperatures, an explosion of the gas mixture is excluded even if air enters the process inside. A temperature treatment of the already sintered / fired metal contacts (made of, for example, Ag, Ag / Al or Al pastes with glass components) improved (see [Gunnar Schubert, Dissertation, University of Konstanz (2006), "Thick Film Metallisation of Crystalline Silicon Solar Cells Mechanisms, Models, Applications "]) at temperatures between 250 ° C and 450 ° C for process times of about 10 to 120 minutes, the contact properties of these metal contacts.Since a longer temperature treatment is required, it is also advantageous, the solar cells The process can be carried out in closed furnaces in which the process atmosphere can be controlled more easily, but in principle also in this case continuous furnaces with correspondingly adapted gas guidance are suitable for this in the interior atmo sphere leads to a significant improvement of the filling factor in d he current-voltage characteristic of semiconductor devices for the conversion of light into electrical energy. This is accompanied by an improvement in the achievable with these semiconductor devices performance under light irradiation. In particular, metal contacts that have not been ideally fired / sintered can be improved. Thus, at the same time a larger process window for the production of these semiconductor devices for the conversion of light into electrical energy.

For more details, advantages and features of the invention will become apparent not only from the claims, the features to be taken these features - alone and / or in combination - but from the following description of the drawings to be taken preferred embodiments.

Show it:

1 is a schematic diagram of a semiconductor device, 2 shows a schematic representation of a dopant profile, and

Fig. 3: a schematic diagram of a process flow.

The method according to the invention for forming a dopant profile in a semiconductor component 10, in which incident electromagnetic radiation is converted into electrical energy, is shown purely in principle on the basis of the figures. In the exemplary embodiment, the semiconductor component 10 has a p-type substrate 12, rear-side contact 14, front-side or front-side contacts 16, and an n-type emitter 18. This forms a pn-junction that creates an electric field to separate free charge carriers generated by the incident radiation so that they can reach the contacts 14, 16.

In the region of the rear side contact 14, furthermore, a layer 20 acting as a back-surface field can be formed. In that regard, however, reference is made to well-known embodiments of semiconductor devices for converting light into electrical energy.

According to the invention, a multi-stage production process for forming the emitter 18 is carried out in such a way that preferably a dopant profile is formed which is deeper than that in the case of known corresponding semiconductor components. This is explained in principle with reference to FIG. 2. In this, the emitter depth is shown with respect to a dopant concentration for an emitter to be produced 18, wherein in the exemplary embodiment, the dopant atoms are phosphorus atoms. Curve 22 represents a phosphorus concentration, ie a dopant profile, which characterizes conventional semiconductor components for converting light radiation into electrical energy.

The curve 22 to be removed dopant depth profile is carried out in accordance with conventional prior art heat treatment of polycrystalline silicon at a temperature treatment between 870 ⁰ C and 900 ⁰ C over a period be- see achieved 10 and 15 minutes, with heating and cooling included.

By fiction, contemporary teaching, the penetration depth of the phosphorus atoms in the semiconductor substrate is increased with the result that effective penetration depths of 1.6 microns and more may be present. The corresponding concentration profile which can be achieved by the method according to the invention is represented by the curve 24 in FIG. 2. The deeper penetration occurs due to a two-stage thermal process. In a first method step, a provisional time dopant depth profile is produced at process temperatures between 500 ⁰ C and 1000 ⁰ C, which has typical properties in the near-surface substrate layer. To form the preliminary dopant depth profile, a dopant source can be applied to the substrate surface. Alternatively, the possibility is given by z. For example, ion implantation or sputtering may apply dopant atoms to the substrate or drive them into the substrate. An example of the preliminary or also first dopant profile is identified in FIG. 2 by "23".

The thermal treatment for producing the preliminary first dopant profile should be at a temperature in the range between 500 ⁰ C and 920 ⁰ C, if the substrate consists of multicrystalline silicon. In this case, the semiconductor components are individually, so separated or spaced from each other subjected to the heat treatment. The corresponding pretreated semiconductor components are then placed one on top of the other in a stack 26 as shown in FIG. 3, in order subsequently to be conveyed by a heat treatment 28. In the exemplary embodiment, this is vertical, without thereby limiting the teaching according to the Invention. During transport through the oven 28, the stack 26 and thus the semiconductor devices 10 over a period t with t of 10 min. up to 20 min. held up to 24 h at a temperature T with T above 800 ⁰ C below the melting temperature of the semiconductor material, in particular between 800 ⁰ C and 1000 ⁰ C, wherein within the furnace 28, a low-oxygen process atmosphere can prevail, in which in particular less than 100 ppm, preferably less than 10 ppm of oxygen may be contained. The heating time can be between 1 minute and 5 minutes lie. The cooling takes place up to a temperature of about 500 ^° C., preferably in a furnace with a controlled process atmosphere. Subsequently, it can be cooled in air. Then, the semiconductor devices 10 are separated.

By a corresponding two-stage heat treatment step then results in a dopant concentration, which is shown in principle in FIG. 2 and is designated by the reference numeral 24.

The curve 24 corresponds to the Dotierstoffkonzentrationsverlauf in a multicrystalline semiconductor substrate made of silicon, which has been exposed to a temperature of 900 ⁰ C over a period of 4 hours.

Due to the teaching according to the invention, it is now possible to form a so-called selective emitter 18, as can be inferred from FIG. 1 in principle. The selective emitter 18 has first and second regions 28, 30 which are offset from each other. Thus, the first regions 28 are set back to the second partial regions. The first partial regions 28 are produced by removing or evaporating away surface regions of the emitter 18 as far as possible, the distance between the upper side of the second regions 30 and those of the first regions 28 z. B. can be 0.4 microns to 1.2 microns. Regardless, the pn junction is at a sufficient distance from the surfaces of the first portions 28. Further, the emitter 18 has sufficient conductivity notwithstanding significantly lower surface concentration, as can also be seen from FIG.

The removal of surface areas of the emitter 18 to form the first portions 28 has the advantage that contaminants accumulated there are removed and thus the recombination rate is reduced. In contrast, the second portions 30 have a high dopant concentration in their surfaces, so that a simple contact with the material of the front contact 16 is possible.

In the surface of the first portions 28, the dopant concentration should ideally be about 5 * 10 ¹⁸ to 10 ¹⁹ P-atoms / cm ³ . If only a reduction of the ripple or a smoothing of semiconductor components is to take place, or a reduction of crystal defects such as dislocation lines to be achieved without mandatory dopant profiles are formed, the invention provides that semiconductor devices in the stack according to the second heat treatment step previously described a heat treatment be subjected. However, the temperatures or holding times can be adapted to the materials of the semiconductor components and their production. So z. B. provided that consisting of multicrystalline silicon, in particular produced by the EFG process semiconductor devices arranged in the stack over a time t _w with 2 h <T _w <4 h at a temperature T _w in particular 850 ⁰ C <T _w < 950 ⁰ C heat treated. However, if the driving of the dopant atoms only after this temperature treatment step, so very high process temperatures are below the melting point of the semiconductor device in an advantageous application conceivable. Then, however, adjusted cooling rates should be selected (eg 5 ⁰ K - 50 ⁰ K per hour).

Claims

Claims: Method for forming a dopant profile

A method of forming a dopant profile emanating from a surface of a plate- or wafer-shaped semiconductor device by introducing dopant atoms into the semiconductor device, characterized in that in the semiconductor device first to form a preliminary first dopant profile on or in at least a portion of the surface

Layer is formed, which contains at least one dopant, that a plurality of corresponding layer having semiconductor components are stacked and stacked to form a stack and that then the stack to form a compared to the first

Dopant profile in the respective semiconductor device is subjected to a greater depth having second dopant profile of a heat treatment.

2. The method according to claim 1, characterized in that the layer is prepared by forming an oxide film layer containing the dopant atoms or by ion implantation or sputtering of the dopant atoms.

A method according to claim 1 or 2, characterized in that prior to arranging the semiconductor devices in a stack, each semiconductor device is heat treated such that volatile constituents present in the oxide film layer are removed or substantially removed or converted or substantially converted.

4. The method according to claim 2 or 3, characterized in that for forming the oxide film layer, first a liquid dopant source is applied to the semiconductor device.

5. The method according to at least one of the preceding claims, characterized in that the liquid dopant source is applied by sputtering, spraying, nebulization, evaporation with subsequent condensation or by dipping on the semiconductor device.

6. The method according to at least one of the preceding claims, characterized in that the liquid dopant source is applied via a transfer agent such as a roll on the semiconductor device.

7. The method according to at least one of the preceding claims, characterized in that a phosphorus-containing solution, converted phosphoric acid solution and / or a phosphorus-containing solution such as sol-gel solution and / or phosphorus-containing paste is used as the liquid dopant source.

8. The method according to at least one of the preceding claims, characterized in that a boron-containing solution such as sol-gel solution or paste is used as the liquid dopant source.

9. The method according to at least one of the preceding claims, characterized in that as a substrate for the semiconductor device silicon, in particular multicrystalline silicon or in particular such produced according to the EFG method is used.

10. The method according to at least claim 9, characterized in that the formation of the oxide film layer at a temperature T ₁ and the second or final dopant profile at a temperature T ₂ with T ₁ <T ₂ , in particular T ₂ - 100 ⁰ C <T ₁ <T ₂ + 100 ⁰ C is performed.

11. The method according to at least one of the preceding claims, characterized in that the formation of the oxide film layer at a temperature T ₁ > 500 ⁰ C, in particular T ₁ > 700 ⁰ C, preferably 800 ⁰ C <T ₁ <1100 ⁰ C is performed.

12. The method according to at least one of the preceding claims, characterized in that in a semiconductor device made of multicrystalline Si material, the oxide film layer at a temperature T ₁ with 500 ⁰ C <T ₁ <920 ⁰ C, preferably with 800 ⁰ C <T ₁ < 920 ⁰ C is formed.

13. The method according to at least one of the preceding claims, characterized in that the semiconductor components are arranged in the stack to each other such that the semiconductor components lie substantially flat on each other.

14. The method according to at least one of the preceding claims, characterized in that the semiconductor components are introduced to form the stack in a centering housing.

15. The method according to at least one of the preceding claims, characterized in that when stacking the semiconductor devices to be deposited semiconductor device is deposited with its own weight on the already stacked semiconductor devices.

16. The method according to at least one of the preceding claims, characterized in that the stacking of the semiconductor components takes place in such a way that the forming stack is inclined to the horizontal and the semiconductor components to be stacked are guided along by positioning aids for stacking.

17. The method according to at least one of the preceding claims, characterized in that the semiconductor devices stacked in a stack are exposed batchwise to the heat treatment to form the final dopant profile.

18. The method according to at least one of the preceding claims, characterized in that the semiconductor devices stacked in the stack are continuously exposed to the heat treatment to form the final or second dopant profile.

19. The method according to at least one of the preceding claims, characterized in that prior to stacking of the semiconductor devices, the dopant source is removed from the semiconductor device.

20. The method according to at least one of the preceding claims, characterized in that dopants are introduced or driven on opposite surfaces of the semiconductor device.

21. The method according to at least one of the preceding claims, characterized in that for forming the first dopant profile, the semiconductor substrate over a period t with 1 min. <t <10 min. the heat treatment is suspended.

22. The method according to at least one of the preceding claims, characterized in that arranged to form the final or second dopant profile arranged in the stack and subjected to the heat treatment semiconductor components over a holding time t _h with 10 to 20 min. <t _h <24 h of the temperature T _{2 are} exposed.

23. The method according to at least one of the preceding claims, characterized in that arranged in the stack semiconductor devices in a time t _A with 1 min. <t _A ≤ 5 min. be heated from room temperature to the temperature T ₂ .

24. The method according to at least one of the preceding claims, characterized in that after formation of the final or second dopant profile arranged in the stack semiconductor devices of a temperature T ₃ with T ₃ <T ₂ , in particular 500 ⁰ C <T ₃ <800 ⁰ C are exposed ,

25. The method according to at least one of the preceding claims, characterized in that the arranged in a stack semiconductor devices are treated with forming gas.

26. The method according to at least one of the preceding claims, characterized in that the stack is received during the heat treatment of at least one of Si, high purity quartz and / or ceramic aids such as supported or guided or held or stabilized.

27. The method according to at least one of the preceding claims, characterized in that the stack is supported during the heat treatment by means of a material and / or guided and / or stabilized, which corresponds to that of the semiconductor devices.

28. The method according to at least one of the preceding claims, characterized in that the semiconductor components are stacked such that the density of the stack substantially corresponds to that of the semiconductor components.

29. The method according to at least one of the preceding claims, characterized in that after forming the final or second dopant profile partially at least partially a doped surface region of the semiconductor device physically z. B. by etching or by conversion such as oxidation is removed.

30. The method according to at least one of the preceding claims, characterized in that the removal of one or more doped surface regions by etching or evaporation or in particular by laser ablation is performed.

31. The method according to at least one of the preceding claims, characterized in that the doped surface region is at least partially converted by oxidation process and / or subsequently removed.

32. The method according to at least one of the preceding claims, characterized in that the stack of semiconductor devices is transported through a heated part of a heat treatment furnace in a continuous or substantially continuous movement.

33. The method according to at least one of the preceding claims, characterized in that the heat treatment of the stack in an oxygen-poor process atmosphere, in particular in a less than 100 ppm, in particular less than 10 ppm oxygen-containing atmosphere or oxygen-free process atmosphere is performed.

34. The method according to at least one of the preceding claims, characterized in that the stacked semiconductor components of the heat treatment over a time t _w are subjected to 0 <t _w <24 h.

35. The method according to at least one of the preceding claims, characterized in that the heat treatment of the stacked semiconductor devices at a temperature T _g with 800 ⁰ C <Tg <T _s with T _s = melting temperature of the material of the semiconductor devices is performed.

36. A semiconductor device manufactured according to at least claim 1, characterized in that the separation of charge carriers enabling final or second dopant an outgoing from the surface of the semiconductor device depth ti 0.3 micrometers <t _\ of <10 microns.

37. A semiconductor device according to claim 36, characterized in that at a distance t ₂ of the surface of the semiconductor device with 0.4 microns <t _2nd

<5 μm, the dopant concentration c 10 ¹⁸ atoms / cm ³ <c <5 ^• 10 ¹⁹ atoms / cm ³ .

38. Semiconductor component according to claim 36 or 37, characterized in that the semiconductor component has an emitter region which consists of first and second partial regions, that the first partial regions extend back to the second partial regions and have a lower surface dopant concentration than the second partial regions.

39. Semiconductor component according to one of claims 36 to 38, characterized in that the second subregions a Oberflächendotier substance concentration C ₁ with C ₁ > 5 10 ¹⁹ atoms / cm ³ , in particular C ₁ > 10 ²⁰ atoms / cm ³ and / or the first Subregions a surface dopant concentration C ₂ with 10 ¹⁸ atoms / cm ³ <C ₂

<5 10 have ¹⁹ atoms / cm ³ .

40. Semiconductor component according to one of claims 36 to 39, characterized in that the surface of the first partial regions to the surface of the second partial regions has a distance d of 0.3 microns <d <1.2 microns.

41. Semiconductor component according to one of claims 36 to 40, characterized in that emanating from the second portions of metal contacts.

42. Semiconductor component according to one of claims 36 to 41, characterized in that after formation of the preliminary first dopant profile, a pn junction at a distance a. _\ From the surface of the semiconductor component takes place with Ά _\ <0.2 microns and after formation of the second dopant profile of the pn junction at a distance a ₂ of 0.3 microns <a _2, especially 0.5 microns <a ₂ runs <10 microns ,

43. A method for producing a planar plate- or wafer-shaped semiconductor device preferably with emanating from at least one surface dopant profile, characterized in that a plurality of semiconductor devices are stacked into a stack, that the semiconductor devices in the stack surface or substantially flat superposed and that the stack is subjected to a heat treatment.

44. The method according to claim 43, characterized in that the semiconductor components are stacked such that the density of the stack is approximately equal to the material density of the semiconductor components.

45. The method of claim 43 or 44, characterized in that the density of the stack is approximately 0.5 to 0.2 times the density of the material of the semiconductor devices.

46. The method according to any one of claims 43 to 45, characterized in that consisting of multicrystalline silicon, in particular produced by the EFG process semiconductor devices stacked over a time t _w with 2 h <t _w <4 h at a temperature T _w be treated with in particular 850 ⁰ C <T _w <950 0C heat treated.

47. The method according to any one of claims 43 to 46, characterized in that consisting of silicon semiconductor devices at a temperature T ₄ with 800 ° C <T ₄ <1380 ° C are heat treated.

48. The method according to any one of claims 43 to 47, characterized in that the heat treatment in the stack arrangement is carried out in a Formiergasatmosphäre or other hydrogen-containing atmosphere.