EP2294571A4 - COMPLEX NUANCE COMPRESSOR WITH DISTRIBUTED LEVEL 1 CACHE SYSTEM AND CENTRALIZED LEVEL 2 COVER MEMORY - Google Patents

COMPLEX NUANCE COMPRESSOR WITH DISTRIBUTED LEVEL 1 CACHE SYSTEM AND CENTRALIZED LEVEL 2 COVER MEMORY

Info

Publication number
EP2294571A4
EP2294571A4 EP09755282.2A EP09755282A EP2294571A4 EP 2294571 A4 EP2294571 A4 EP 2294571A4 EP 09755282 A EP09755282 A EP 09755282A EP 2294571 A4 EP2294571 A4 EP 2294571A4
Authority
EP
European Patent Office
Prior art keywords
level
nuance
compressor
complex
cache system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP09755282.2A
Other languages
German (de)
French (fr)
Other versions
EP2294571A1 (en
Inventor
Anthony P Delaurier
Mark Leather
Robert S Hartog
Michael J Mantor
Mark C Fowler
Marcos P Zini
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of EP2294571A1 publication Critical patent/EP2294571A1/en
Publication of EP2294571A4 publication Critical patent/EP2294571A4/en
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—Three-dimensional [3D] image rendering
    • G06T15/005—General purpose rendering architectures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/30—Providing cache or TLB in specific location of a processing system
    • G06F2212/302—In image processor or graphics adapter
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/455—Image or video data
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/121—Frame memory handling using a cache memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Graphics (AREA)
  • Computer Hardware Design (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Image Generation (AREA)
  • Processing Or Creating Images (AREA)
EP09755282.2A 2008-05-30 2009-06-01 COMPLEX NUANCE COMPRESSOR WITH DISTRIBUTED LEVEL 1 CACHE SYSTEM AND CENTRALIZED LEVEL 2 COVER MEMORY Ceased EP2294571A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US5749208P 2008-05-30 2008-05-30
PCT/US2009/003317 WO2009145919A1 (en) 2008-05-30 2009-06-01 Shader complex with distributed level one cache system and centralized level two cache

Publications (2)

Publication Number Publication Date
EP2294571A1 EP2294571A1 (en) 2011-03-16
EP2294571A4 true EP2294571A4 (en) 2014-04-23

Family

ID=41377446

Family Applications (1)

Application Number Title Priority Date Filing Date
EP09755282.2A Ceased EP2294571A4 (en) 2008-05-30 2009-06-01 COMPLEX NUANCE COMPRESSOR WITH DISTRIBUTED LEVEL 1 CACHE SYSTEM AND CENTRALIZED LEVEL 2 COVER MEMORY

Country Status (5)

Country Link
EP (1) EP2294571A4 (en)
JP (1) JP5832284B2 (en)
KR (1) KR101427409B1 (en)
CN (1) CN102047316B (en)
WO (1) WO2009145919A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110471943B (en) * 2018-05-09 2024-09-20 北京京东尚科信息技术有限公司 Real-time data statistics device and method and computer-readable storage medium
US11841803B2 (en) 2019-06-28 2023-12-12 Advanced Micro Devices, Inc. GPU chiplets using high bandwidth crosslinks
US12170263B2 (en) 2019-09-27 2024-12-17 Advanced Micro Devices, Inc. Fabricating active-bridge-coupled GPU chiplets
US11507527B2 (en) * 2019-09-27 2022-11-22 Advanced Micro Devices, Inc. Active bridge chiplet with integrated cache
CN112783926B (en) * 2021-01-20 2025-01-17 银盛支付服务股份有限公司 Method for reducing time consumption of calling service

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10232825A (en) * 1997-02-20 1998-09-02 Nec Ibaraki Ltd Cache memory control system
EP1498824A2 (en) * 2003-06-30 2005-01-19 Microsoft Corporation System and method for parallel execution of data generation tasks
US20050225558A1 (en) * 2004-04-08 2005-10-13 Ati Technologies, Inc. Two level cache memory architecture
US7103720B1 (en) * 2003-10-29 2006-09-05 Nvidia Corporation Shader cache using a coherency protocol

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6629188B1 (en) * 2000-11-13 2003-09-30 Nvidia Corporation Circuit and method for prefetching data for a texture cache
JP3620473B2 (en) * 2001-06-14 2005-02-16 日本電気株式会社 Method and apparatus for controlling replacement of shared cache memory
US7248585B2 (en) * 2001-10-22 2007-07-24 Sun Microsystems, Inc. Method and apparatus for a packet classifier
JP3840966B2 (en) * 2001-12-12 2006-11-01 ソニー株式会社 Image processing apparatus and method
US6871264B2 (en) * 2002-03-06 2005-03-22 Hewlett-Packard Development Company, L.P. System and method for dynamic processor core and cache partitioning on large-scale multithreaded, multiprocessor integrated circuits
US7069387B2 (en) 2003-03-31 2006-06-27 Sun Microsystems, Inc. Optimized cache structure for multi-texturing
JP4451717B2 (en) * 2004-05-31 2010-04-14 株式会社ソニー・コンピュータエンタテインメント Information processing apparatus and information processing method
US7280107B2 (en) * 2005-06-29 2007-10-09 Microsoft Corporation Procedural graphics architectures and techniques
TWI335521B (en) * 2005-12-19 2011-01-01 Via Tech Inc Dsp system with multi-tier accelerator architecture and method for operating the same
JP4295814B2 (en) * 2006-03-03 2009-07-15 富士通株式会社 Multiprocessor system and method of operating multiprocessor system
US20070211070A1 (en) * 2006-03-13 2007-09-13 Sony Computer Entertainment Inc. Texture unit for multi processor environment
US7965296B2 (en) * 2006-06-20 2011-06-21 Via Technologies, Inc. Systems and methods for storing texture map data
US20080094408A1 (en) 2006-10-24 2008-04-24 Xiaoqin Yin System and Method for Geometry Graphics Processing

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10232825A (en) * 1997-02-20 1998-09-02 Nec Ibaraki Ltd Cache memory control system
EP1498824A2 (en) * 2003-06-30 2005-01-19 Microsoft Corporation System and method for parallel execution of data generation tasks
US7103720B1 (en) * 2003-10-29 2006-09-05 Nvidia Corporation Shader cache using a coherency protocol
US20050225558A1 (en) * 2004-04-08 2005-10-13 Ati Technologies, Inc. Two level cache memory architecture

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PARK S-J ET AL: "A RECONFIGURABLE MULTILEVEL PARALLEL GRAPHICS CACHE MEMORY WITH 75 GB/S PARALLEL CHACHE REPLACEMENT BANDWIDTH", 2001 SYMPOSIUM ON VLSI CIRCUITS. DIGEST OF TECHNICAL PAPERS. KYOTO, JAPAN, JUNE 14 - 16, 2001; [SYMPOSIUM ON VLSI CIRCUITS], TOKYO : JSAP, JP, 14 June 2001 (2001-06-14), pages 233 - 236, XP001071986, ISBN: 978-4-89114-014-4, DOI: 10.1109/VLSIC.2001.934250 *
See also references of WO2009145919A1 *

Also Published As

Publication number Publication date
WO2009145919A1 (en) 2009-12-03
CN102047316A (en) 2011-05-04
EP2294571A1 (en) 2011-03-16
CN102047316B (en) 2016-08-24
KR101427409B1 (en) 2014-08-07
JP2011523745A (en) 2011-08-18
JP5832284B2 (en) 2015-12-16
KR20110015034A (en) 2011-02-14

Similar Documents

Publication Publication Date Title
EP2225649A4 (en) MEMORY SYSTEM
EP2248024A4 (en) MEMORY SYSTEM
EP2126915A4 (en) MEMORY SYSTEM AND METHOD WITH SERIAL AND PARALLEL MODES
DE602005018560D1 (en) storage system
EP2145638A4 (en) DEVICE FOR EVALUATING CHANGES AFFECTING CARDIAC FUNCTION
EP2212887A4 (en) THREE DIMENSIONAL MEMORY MODULE ARCHITECTURES
DE602006016570D1 (en) STORAGE SYSTEM
EP2115519A4 (en) DYNAMIC OPHTHALMIC OPENING
EP1932076A4 (en) DSL SYSTEM
EP2500889A4 (en) DEVICE, METHOD, AND PROGRAM FOR EVALUATING THE ATTENTION LEVEL
DE502008000057D1 (en) Portable harvester
EP2545458A4 (en) DATA CENTER WITH MEMORY CACHE
BRPI0809902A2 (en) METHODS FOR ASSESSING CELLS AND CELL CROPS
EP2248027A4 (en) MEMORY SYSTEM
IT1392361B1 (en) DIAGNOSTIC DEVICE FOR THE STATE OF BALL BEARINGS, IN PARTICULAR BASED ON THE DETECTION OF SOUNDS
BRPI0906424A2 (en) extracted cache attribute feature and consequent statement
EP1887292A4 (en) MOISTURE REGULATOR
FR2920033B1 (en) TURBOMACHINE WITH DIFFUSER
DE602009000579D1 (en) Concave suspension for a threshing unit in a combine harvester
EP2119865A4 (en) STORAGE OPERATING DEVICE
DE602006005311D1 (en) storage system
EP2183681A4 (en) PROBABILITY STATE MODELS
EP1873487A4 (en) LEVEL
FR2905028B1 (en) ELECTROCHEMICAL MEMORY DEVICE
EP2294571A4 (en) COMPLEX NUANCE COMPRESSOR WITH DISTRIBUTED LEVEL 1 CACHE SYSTEM AND CENTRALIZED LEVEL 2 COVER MEMORY

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20101224

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL BA RS

DAX Request for extension of the european patent (deleted)
A4 Supplementary search report drawn up and despatched

Effective date: 20140325

RIC1 Information provided on ipc code assigned before grant

Ipc: G06T 15/00 20110101ALI20140319BHEP

Ipc: G06F 12/08 20060101ALI20140319BHEP

Ipc: G09G 5/36 20060101AFI20140319BHEP

Ipc: G06T 1/60 20060101ALI20140319BHEP

17Q First examination report despatched

Effective date: 20170530

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: ADVANCED MICRO DEVICES, INC.

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: ADVANCED MICRO DEVICES, INC.

REG Reference to a national code

Ref country code: DE

Ref legal event code: R003

18R Application refused

Effective date: 20180925