EP2281241A1 - Procédé pour adresser des mémoires non volatiles à pagination - Google Patents

Procédé pour adresser des mémoires non volatiles à pagination

Info

Publication number
EP2281241A1
EP2281241A1 EP08760120A EP08760120A EP2281241A1 EP 2281241 A1 EP2281241 A1 EP 2281241A1 EP 08760120 A EP08760120 A EP 08760120A EP 08760120 A EP08760120 A EP 08760120A EP 2281241 A1 EP2281241 A1 EP 2281241A1
Authority
EP
European Patent Office
Prior art keywords
memory
logbook
volatile memory
address
lbk
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP08760120A
Other languages
German (de)
English (en)
Inventor
Franz Schmidberger
Christoph Baumhof
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hyperstone GmbH
Original Assignee
Hyperstone GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyperstone GmbH filed Critical Hyperstone GmbH
Publication of EP2281241A1 publication Critical patent/EP2281241A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7201—Logical to physical mapping or translation of blocks or pages

Definitions

  • the invention relates to a method for addressing memory pages of a nonvolatile memory in a memory system with a memory controller and a further volatile memory, wherein the nonvolatile memory is organized in erasable memory blocks with a plurality of memory pages, and each
  • Memory page which contains a number of sectors, can be written individually, and in the volatile memory, an address translation table is maintained, in which an assignment of logical memory page addresses to physical memory page addresses is specified.
  • SSD solid state disks
  • the data sets in the storage system are addressed as logical sectors that can be read, written and deleted as required.
  • Flash memory has the limitation that only written to deleted memory cells and only larger blocks of sectors can be deleted together. Now, if a sector is to be written changed within a block, this is written in the previous method in a deleted sector in an alternative block. If this sector is now to be changed again, it must be written in another alternative block and all other, unchanged sectors in the new alternative block copy. Since the memory blocks can contain a large number of sectors - currently blocks with a size of 256 kbytes - a great deal of work is required for copying unchanged sectors.
  • Modern flash memories can be addressed on a page-oriented basis. Four or eight sectors are combined into a memory page and written together in a deleted area of the memory block.
  • the aforementioned method with the escape blocks could also be applied to memory pages rather than sectors, but it retains its disadvantages.
  • a large address translation table is maintained in the volatile memory of a memory system by the memory controller, which includes the current logical page address mappings to physical page addresses. This table is also used as a reconstruction table in the non-volatile
  • the log is saved in non-volatile memory.
  • Fig. 1 a typical memory system is shown.
  • Fig. 2 shows the structure of the address allocation table in the RAM.
  • Fig. 3 the structure of the log is shown in the RAM.
  • FIG. 4 shows the structure of the reconstruction table in the flash memory.
  • a memory system MS is shown, via a host bus HB with a
  • the host bus can be implemented in various ways, such as Universal Serial Bus USB or SATA BUS.
  • the memory commands with the associated logical addresses reach the host via the HB bus
  • the data sets of the memory system are stored in the non-volatile memories, here as flash memory FM with multiple chips.
  • a memory controller MC evaluates and executes the memory commands.
  • the volatile memory RAM is the address assignment table
  • the reconstruction table RT is stored. Newer address mappings from logical to physical
  • Page addresses are noted in the logbook LBK in the RAM. Likewise the usage of the logbook is written in the usage table ULT.
  • the logbook table LBK is saved in the flash memory FM.
  • a battery BAT is available, which provides the necessary energy for the backup process.
  • the battery BAT can also be designed as a rechargeable battery or as a capacitor.
  • the address assignment table AT contains the physical page addresses PPA to all the logical addresses LA.
  • the logical address LA is divided into the logical page address LPA and the sector address SA.
  • the logical page address LPA serves as an index from 0 to n in the table.
  • the physical address PA used is the current one physical page address PPA, here with the index A, and the sector address SA formed. If a new physical page address is needed to write a memory page, the entry is changed in the address mapping table.
  • the reconstruction table RT is held in a nonvolatile memory FM. Its structure is shown in FIG. It contains a copy of the address assignment table at the time of the last save.
  • the index in the table is the logical page address LPA and the entries indicate associated physical page addresses PPA. This mapping is not fully up to date because the address mapping table has changed since the last backup.
  • the address assignment table AT When the address assignment table AT is reconstructed after a deliberate or unwanted power failure, it is currently created from the reconstruction table and the saved logbook by replacing the outdated entries, in this example PPAx and PPAy, with the current assignments from the logbook. For this purpose, the logbook is read out sequentially and the respective entries in the address assignment table AT are rewritten. In this case, entries are also replaced several times, here with the example PPAx. At the end of the readout, the address assignment table AT is up to date.
  • the logbook list can be organized as a linear list or as a linked list.
  • the logbook has a certain maximum length.
  • the current address assignment table AT is newly stored as a reconstruction table RT in the non-volatile memory. Since the reconstruction table RT can be very long and thus extends over several memory blocks, only the memory block of the reconstruction table RT is rewritten, whose entries have undergone the most changes.
  • a usage table ULT is included in the volatile memory, in which the number of changes per memory block is counted. It is now in this usage table ULT after the Memory block of the reconstruction table RT searched with most changes. This memory block is rewritten with the current address assignments and chained into the reconstruction table RT.
  • the described steps allow memory operations in large flash memory systems, in particular solid state disks, to be carried out much faster than in the previously customary methods.
  • the costly copying of unaltered sectors from one memory block to another is minimized, namely to the sectors of a memory page.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

L’invention concerne un procédé pour adresser des pages de mémoire d’une mémoire non volatile dans un système de mémorisation (MS) comprenant un contrôleur de mémoire (MC) et une mémoire volatile supplémentaire (RAM), selon lequel la mémoire non volatile est organisée en blocs de mémoire effaçables avec une pluralité de pages de mémoire et chaque page de mémoire, qui contient un certain nombre de secteurs, peut être écrite individuellement, et selon lequel une table de conversion d’adresses (AT) est conservée dans la mémoire volatile, dans laquelle est indiquée une association entre les adresses logiques des pages de mémoire (LPA) et les adresses physiques des pages de mémoire (PPA). Selon l’invention, le contrôleur de mémoire (MC) enregistre une table de reconstruction (RT) sous la forme d’une copie de la table de conversion d’adresse dans un ou plusieurs blocs de mémoire dans la mémoire non volatile (FM), gère conjointement une table de journal (LBK) contenant des jeux de données relatives aux associations modifiées entre les adresses logiques des pages de mémoire (LPA) et les adresses physiques des pages de mémoire (PPA) dans la mémoire volatile (RAM), et lorsque la table de journal (LBK) dépasse une taille prédéfinie, une table de reconstruction (RT) modifiée est enregistrée dans la mémoire non volatile.
EP08760120A 2008-05-28 2008-05-28 Procédé pour adresser des mémoires non volatiles à pagination Withdrawn EP2281241A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2008/056524 WO2009143885A1 (fr) 2008-05-28 2008-05-28 Procédé pour adresser des mémoires non volatiles à pagination

Publications (1)

Publication Number Publication Date
EP2281241A1 true EP2281241A1 (fr) 2011-02-09

Family

ID=40280884

Family Applications (1)

Application Number Title Priority Date Filing Date
EP08760120A Withdrawn EP2281241A1 (fr) 2008-05-28 2008-05-28 Procédé pour adresser des mémoires non volatiles à pagination

Country Status (3)

Country Link
US (1) US20100250837A1 (fr)
EP (1) EP2281241A1 (fr)
WO (1) WO2009143885A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9104614B2 (en) 2011-09-16 2015-08-11 Apple Inc. Handling unclean shutdowns for a system having non-volatile memory
US10445229B1 (en) * 2013-01-28 2019-10-15 Radian Memory Systems, Inc. Memory controller with at least one address segment defined for which data is striped across flash memory dies, with a common address offset being used to obtain physical addresses for the data in each of the dies
US9454474B2 (en) * 2013-03-05 2016-09-27 Western Digital Technologies, Inc. Methods, devices and systems for two stage power-on map rebuild with free space accounting in a solid state drive
KR102458312B1 (ko) * 2017-06-09 2022-10-24 삼성전자주식회사 스토리지 장치 및 이의 동작 방법

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1667014A1 (fr) * 2003-09-18 2006-06-07 Matsushita Electric Industrial Co., Ltd. Carte a puce a semiconducteurs, appareil de commande de memoire a semiconducteurs, et procede de commande de memoire a semiconducteurs

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100449708B1 (ko) * 2001-11-16 2004-09-22 삼성전자주식회사 플래시 메모리 관리방법
US6707748B2 (en) * 2002-05-07 2004-03-16 Ritek Corporation Back up power embodied non-volatile memory device
DE10227255B4 (de) * 2002-06-19 2008-06-26 Hyperstone Gmbh Verfahren zur Wiederherstellung von Verwaltungsdatensätzen eines blockweise löschbaren Speichers
US6831865B2 (en) * 2002-10-28 2004-12-14 Sandisk Corporation Maintaining erase counts in non-volatile storage systems
KR100457812B1 (ko) * 2002-11-14 2004-11-18 삼성전자주식회사 플래시 메모리, 그에 따른 플래시 메모리 액세스 장치 및방법
US8244958B2 (en) * 2005-05-09 2012-08-14 Sandisk Il Ltd. Method and system for facilitating fast wake-up of a flash memory system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1667014A1 (fr) * 2003-09-18 2006-06-07 Matsushita Electric Industrial Co., Ltd. Carte a puce a semiconducteurs, appareil de commande de memoire a semiconducteurs, et procede de commande de memoire a semiconducteurs

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2009143885A1 *

Also Published As

Publication number Publication date
WO2009143885A1 (fr) 2009-12-03
US20100250837A1 (en) 2010-09-30

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