EP2267700B1 - Appareil et procédé de sélection de bandes de quantification dans des encodeurs audio - Google Patents

Appareil et procédé de sélection de bandes de quantification dans des encodeurs audio Download PDF

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EP2267700B1
EP2267700B1 EP09008170A EP09008170A EP2267700B1 EP 2267700 B1 EP2267700 B1 EP 2267700B1 EP 09008170 A EP09008170 A EP 09008170A EP 09008170 A EP09008170 A EP 09008170A EP 2267700 B1 EP2267700 B1 EP 2267700B1
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EP2267700A1 (fr
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David Trainor
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Qualcomm Technologies International Ltd
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APT Licensing Ltd
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    • G—PHYSICS
    • G10—MUSICAL INSTRUMENTS; ACOUSTICS
    • G10L—SPEECH ANALYSIS TECHNIQUES OR SPEECH SYNTHESIS; SPEECH RECOGNITION; SPEECH OR VOICE PROCESSING TECHNIQUES; SPEECH OR AUDIO CODING OR DECODING
    • G10L19/00—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis
    • G10L19/02—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis using spectral analysis, e.g. transform vocoders or subband vocoders
    • G10L19/032—Quantisation or dequantisation of spectral components

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  • the present invention relates to audio encoders, especially audio encoders for use in Bluetooth systems.
  • the invention relates particularly to selecting quantisation bands by searching quantiser tables in audio encoders.
  • Bluetooth is a short range wireless communications technology that can create personal area networks (PANs) between a variety of fixed and mobile devices, such as mobile phones, laptops, digital cameras, games consoles and media players. It is estimated that Bluetooth currently enjoys an installed base of almost two billion devices worldwide. Specifications and standards for Bluetooth operation are created and maintained by the Bluetooth Special Interest Group (SIG).
  • SIG Bluetooth Special Interest Group
  • Bluetooth is a ubiquitous wireless communications technology, there are a number of technical considerations when using it for the wireless transmission of high-quality stereo audio.
  • A2DP Advanced Audio Distribution Profile
  • SBC Sub Band Codec
  • a suitably equipped pair of Bluetooth devices may choose to communicate audio using a compression codec other than SBC.
  • the decision as to which compression codec to use is made as part of an initial exchange of messages when the communicating devices first establish the Bluetooth link. This is a process known as pairing.
  • Bluetooth communications capability is typically added to a product, e.g. a mobile device, by integrating one of many single-chip Bluetooth solutions provided by companies such as Cambridge Silicon Radio, Broadcom and others.
  • Audio compression and decompression functions are usually implemented in the form of embedded software executing on a general purpose processor or digital signal processor that is internal to the Bluetooth chip.
  • the execution of the audio compression codec requires the processor to carry out a certain amount of work. This, in turn, causes the processor to draw a corresponding level of current from the battery powering the mobile device, which has a direct effect on how long the device can operate on a single charge of the battery.
  • WO 99/62189 A2 discloses a binary search procedure for determining the optimal quantization step size.
  • a first aspect of the invention provides an apparatus for compressing an audio signal as claimed in claim 1.
  • a second aspect of the invention provides a method of selecting quantisation bands as claimed in claim 14.
  • a third aspect of the invention provides a computer program product as claimed in claim 15.
  • the present invention enables quantiser tables to be searched using relatively few processor instructions for each search iteration. Fewer processor instructions equates to reduced current consumption and better battery life. Further advantageous aspects of the invention will become apparent to those ordinarily skilled in the art upon review of the following description of a preferred embodiment and with reference to the accompanying drawings.
  • an audio compression codec comprising an audio encoder 10 and an audio decoder 50.
  • the encoder 10 and decoder 50 are suitable for use as an audio compression codec in systems that support Bluetooth.
  • the encoder 10 receives an input signal comprising audio samples, i.e. from an audio signal sampled in the time domain.
  • the encoder 10 processes the input signal to produce encoded, or compressed, output samples.
  • the processing performed by the encoder 10 compresses the input signal such that it, or more particularly a compressed representation of it, may be transmitted to the decoder 50 with lower bandwidth requirements than would be necessary for the uncompressed signal.
  • the decoder 50 receives the encoded samples and decodes them to produce time domain audio samples representing the input audio signal received by the encoder.
  • the correspondence between the audio samples produced by the decoder 50 and the audio samples received by the encoder 10 is dependent on the compression techniques used by the encoder 10.
  • the encoder 10 and decoder 50 communicate by means of a communications link (not illustrated) which may, for example, comprises a wireless link such as a Bluetooth link.
  • the encoder 10 is co-operable with a transmitter (not shown) for transmitting the compressed output samples to the decoder 50
  • the decoder 50 is co-operable with a receiver (not shown) for receiving the compressed output samples.
  • the transmitter and receiver each process the samples in accordance with the communications technology, e.g. Bluetooth, that they are configured to support.
  • the encoder 10 processes the input stream 11 of audio samples in groups of multiple, in this case 4, samples per audio channel (i.e. left and right channels).
  • Each successive group of samples is processed by an analysis filter bank 12 that splits the input audio stream into multiple, in this case 4, parallel sub-band sample streams 14, where the sample rate of each sub-band stream 14 is a fraction of, in this case 1 ⁇ 4 of, that of the input audio stream 11.
  • the respective data in each sub-band stream 14 represents a respective subset of audio content from the input stream 11 that falls into a respective frequency range covered by each sub-band.
  • each sub-band is of equal width and covers 1 ⁇ 4 of the range of audible frequencies.
  • each sub-band covers a 6 kHz range of frequencies.
  • the first sub-band passes the audio content within the 0-6 kHz, the second 6-12 kHz, the third 12-18 kHz and the final sub-band passes 18-24 kHz.
  • each sub-band stream represents a particularly frequency range. This allows the data in each sub-band to undergo lossy compression independently and with different levels of loss or distortion in each band. Since the human ear is more sensitive to audio in some frequency ranges than others, additional levels of compression can be gained by more aggressively compressing the frequency bands to which the ear is relatively insensitive.
  • lossy compression of the data in each sub-band is carried out using differential coding and quantization.
  • a respective adaptive predictor filter 16 is provided and acts as a predictor, providing a predicted value for upcoming samples from the sub-band filter bank 12.
  • a respective error calculator 18 is provided for each sub-band stream 14 and is arranged to receive, in respect of each sub-band sample of the respective sub-band stream 14, the actual sub-band value from the sub-band filter bank 12 and the corresponding predicted sub-band value from the predictive filter 16, and to calculate the difference between the predicted value and the actual value to produce a prediction error value.
  • the error calculator 18 is provided for each sub-band stream 14 and is arranged to receive, in respect of each sub-band sample of the respective sub-band stream 14, the actual sub-band value from the sub-band filter bank 12 and the corresponding predicted sub-band value from the predictive filter 16, and to calculate the difference between the predicted value and the actual value to produce a prediction error value.
  • the predictive filter 16 If the predictive filter 16 is performing well then the magnitude of this difference, or prediction error value, is small compared to the sub-band sample. Since the prediction error tends to be small, it can be communicated using fewer bits than the corresponding sub-band sample and hence transmitting prediction errors offers a form of compression.
  • the encoder 10 includes a respective quantizer 20 for each sub-band stream 14 arranged to receive the prediction error values and to produce respective quantized error values. It is the quantization operation that introduces the lossy aspect of the compression, since the quantization causes information to be discarded and is a process that can only be approximately inverted.
  • a respective inverse quantizer 22 is arranged to perform inverse quantization on the error values and the output is provided to the respective predictive filter 16. Inverse quantization is carried out to provide approximate prediction error samples to stimulate the predictive filters 16.
  • the predictor filters 16 produce predictions of future samples emerging from the sub-band filter bank 12 based on a history of previous prediction error values.
  • the same differential coding, quantization, inverse quantization and prediction techniques are applied independently to the respective data in each sub-band stream 14.
  • the sophistication and accuracy of the respective prediction filters 16 and/or the levels of approximation employed by the respective quantizers 20 may differ from one sub-band to the next, for example based on the relative sensitivity of the human ear to audio frequencies in the respective sub-band.
  • the encoder 10 further includes a data packer 24 for concatenating the respective quantized prediction error values for each sub-band to provide a concatenated quantized error value in respect of each group of input audio samples.
  • Each concatenated quantized error value provides a respective compressed output sample of the encoder 10.
  • the data from the respective audio channels is interleaved and so the encoder 10 processes the respective channels alternately, e.g. each channel being processed alternately with the other, one groups of input samples at a time.
  • the illustrated encoder 10 consumes 4 input 16-bit audio samples at a time and produces a single 16-bit compressed sample, hence compressing the input audio by a factor of 4.
  • the encoder may be in general arranged to process audio samples in groups of at least one, but typically a plurality of, samples per audio channel. Further, in alternative embodiments, the encoder may be in general arranged to split the audio signal into any practicable number of sub-band sample streams, or even not to split the audio signal into sub-band streams.
  • the configuration of the encoder, and correspondingly of the decoder, would be adapted accordingly as would be apparent to a skilled person.
  • the preferred encoder 10 of Figure 1 implements a Sub-band Adaptive Differential Pulse Code Modulation (SB-ADPCM) compression scheme employing lossy compression to reduce the required network transmission rate for an audio input signal.
  • SB-ADPCM Sub-band Adaptive Differential Pulse Code Modulation
  • the encoder 10 achieves a fixed compression ratio of 4:1, thereby requiring only 25% of the network transmission rate associated with the communication of uncompressed audio.
  • the decoder 50 must initially synchronise itself to the incoming data stream 51 that it receives from the encoder 10.
  • the encoder 10 and decoder 50 communicate via a Bluetooth link.
  • data is transmitted in groups, or packets, of 8-bit bytes that do not necessarily correspond conveniently with the compressed output samples from the encoder 10.
  • the compressed samples output from the encoder 10 are 16 bits long in the present example and, for stereo transmission, are transmitted in channel interleaved fashion and so compressed samples for the left and right channels are sent alternately.
  • the decoder 50 needs to initially deduce from the sequence of bytes in a received Bluetooth-compatible packet whether a particular byte is the most or least significant byte of a compressed output sample from the encoder 10, and whether it belongs to the output sample for the left or the right channel. This creates four possibilities that need to be resolved and the decoder 50 accomplishes this by examining the incoming data stream 51 for synchronisation data.
  • the synchronisation data is preferably added by the quantization process during encoding. Once the synchronisation data has been found with a high degree of reliability, it uniquely identifies the data from the left and right audio channels and which bytes are the most and least significant bytes of the compressed output samples.
  • the compressed samples are unpacked such that the bits of each compressed sample are split into the respective quantized prediction error value for each sub-band.
  • the synchronisation and unpacking is performed by a synchronisation and unpacking module 52.
  • the module 52 thus produces a respective data stream 53 for each sub-band, each data stream 53 comprising the respective quantized prediction error values.
  • An adaptive inverse quantizer 54 is provided for each sub-band in order to perform inverse quantization of the quantized prediction error values.
  • a respective adaptive predictor filter 56 is provided for each sub-band and is arranged to regenerate the same predicted sample values that were produced by corresponding predictor filters 16 at the encoder 10.
  • a respective adder 58 is provided for adding the inverse-quantized prediction error values produced by the inverse quantizers 54 to the respective predicted sample values produced by the predictor filters 56.
  • a close approximation to the respective original sub-band sample of the respective sub-band stream 14 is obtained.
  • the form of the inverse quantization and prediction performed by the quantizer 54 and predictor filter 56 respectively is identical to that performed for the corresponding sub-band in the encoder 10.
  • the respective sub-band samples produced by the respective inverse quantizers 56 are input to a sub-band synthesis filter bank 60 in order to produce audio samples that are representative of the input audio samples received by the encoder 10.
  • the sub-band filter bank 60 operates in the opposite sense to the filter bank 24 of the encoder 10. That is, instead of analysing an input stream and splitting it into multiple, in this case 4, lower-rate streams covering multiple, in this case 4, frequency ranges, the filter bank 60 takes the lower-rate streams and synthesises the original full-rate stream from it. Hence the consumption of a single compressed sample by the decoder 50 results in multiple, in this case 4, output audio samples being produced.
  • the structure and individual filter specification of the synthesis filter bank 60 is similar in many respects to the analysis filter bank 12 in the encoder 10, but is not identical.
  • the codec 10, 50 is adaptive in two major ways. Firstly, the predictor filter in each sub-band adapts its coefficients based on a history of its input and previous output values. The adjustments are carried out to try to drive the prediction error towards zero and minimise it.
  • the second area of adaptation is around the quantisation and inverse quantisation processes.
  • the width or spacing of the quantisation levels is dynamically adjusted to quantise the signal with minimal distortion. Hence, if the quantiser input (prediction error) is small, the quantiser will tend to reduce the quantisation level spacing, so that small values can be quantised with little additional error. Similarly, if the quantiser input starts to get big, then the quantiser will increase the quantisation level spacing. Failure to do so would result in an inaccurate quantised representations of large input values, even if the outermost quantisation level is chosen.
  • each quantizer 20 is capable of selecting from a plurality of quantization bands, each quantization band covering a respective range of values that the prediction error value could take and being represented by a respective quantization output value.
  • the respective quantization output value becomes the quantized prediction error value.
  • FIG 3 An example is shown in Figure 3 where a continuous waveform 70 is quantized using eight quantization bands 72, the quantized output value 74 associated with each quantization band being, by way of example only, a 3-bit label. Prediction error values corresponding to points A and B on the waveform will, in this example, each be assigned to the same quantization band (with label 011) even though they have different absolute values.
  • the quantization bands are not equally sized. It is noted that the quantization output values may comprise fewer or more than 3 bits. Moreover, the number of bits making up the quantization output value may differ between sub-bands. For example, the quantizer may use a higher number of bits for the quantization output value (i.e. a higher resolution) for sub-bands in respect of which the human ear is more sensitive than for sub-bands in respect of which the human ear is relatively insensitive.
  • Data defining the quantization bands is stored in memory, typically in a quantiser table (illustrated in Figures 5 to 9 ).
  • the quantizer 20 performs a search of the quantiser table in order to determine the most appropriate quantisation band for the respective prediction error value. This is described in further detail below.
  • FIG. 4 shows the pertinent features of a typical hardware structure for a digital signal processor as found on a Bluetooth chip.
  • the architecture 80 includes a processor 82 in the preferred form of a digital signal processor, although other data processors, or microprocessors, may alternatively be used.
  • the processor 82 includes a plurality of data registers, shown in Figure 4 as register bank 84. These registers may comprise general purpose registers for containing data such as input operands and computed results of various arithmetic and logical operations. Optionally, one or more dedicated registers or register banks may be provided for address generation. These are represented in Figure 4 by an address generator unit 86.
  • the processor 82 further includes an arithmetic logic unit (ALU) 88 for performing logical and/or arithmetic computations on operands.
  • a data memory interface unit 90 is also provided to allow the processor 82 to communicate with local memory device(s) 92, and in particular with data memory as is described in more detail hereinafter.
  • Signal processors typically have a set of peripherals, consisting of functions like timers, UARTs and special interfaces to get data on and off the processor in various formats. This is represented in Figure 4 by peripheral unit 85.
  • the architecture 80 typically includes a memory management unit (MMU) 93 with which the processor 82 is in communication for handling accesses to memory 92.
  • the MMU 93 can take any suitable conventional form.
  • the memory device 92 includes a plurality of data memories 94, in this example two data memories labelled as Data Memory 1 and Data Memory 2 in Figure 4 .
  • the data memory interface unit 90 supports a respective data memory interface 91 between the processor 82 and each of the data memories 94.
  • at least one program memory 96 is provided.
  • the processor 82 is in communication with the program memory 96 by means of any suitable conventional program memory interface.
  • the memory device 92 typically comprises one or more random access memory (RAM).
  • the program memory 96 stores processor executable instructions that the processor 82 is required to implement.
  • the instructions take the form of embedded executable computer software for performing one or more of the functions required to implement audio compression or decompression.
  • one of the data memories 94 e.g. Data Memory 1
  • a separate data memory e.g. Data Memory 2
  • stores data defining the quantisation bands typically in the form of one or more quantiser tables.
  • the respective parallel data memory interfaces 91 allow a data value to be read from, or written to, each data memory Data Memory 1, Data Memory 2 concurrently. In conjunction with the ALU 88, this allows an arithmetic or logical computation to be performed in parallel with up to two memory accesses. Arranging the algorithmic computations to maximally exploit this parallelism facilitates keeping the processor instruction count low.
  • the address generator unit 86 has, in respect of each data memory 94, a plurality of address generators that can address the respective data memory.
  • Each address generator comprises 3 hardware registers, namely an index (I) register, which holds the actual memory address to index the corresponding data memory 94; a modify (M) register, which contains a value by which the contents of the corresponding I register are automatically incremented by the processor architecture 80 after a memory access; and a length (L) register, which allows the set-up of modulo addressing, so that a range of addresses that are traversed by the processor hardware 80 in a circular or wrap-around fashion can be defined.
  • I index
  • M modify
  • L length
  • processors within Bluetooth chips are fixed-point processors, meaning that computation results need to be continually limited, scaled or rounded to remain compliant with a fixed numerical format adopted by the processor. This allows simpler and lower-powered processors to be created, but means that signal processing algorithms cannot be implemented in a mathematically-exact fashion.
  • Fixed-point processors often possess a small number of extended-precision registers, which allow relatively short sequences of arithmetic and logical instructions to take place at higher levels of precision, with limits and rounding only being applied when results are moved from an extended-precision register.
  • the quantised value that most closely represents the higher-precision input value i.e. the prediction error value being quantized
  • Successive bands or ranges of input values map to successive quantised values. An example of this mapping is shown in Figure 3 , where 8 bands of input values map to 8 different quantised values.
  • the predictor 16 operation creates a situation whereby small errors are statistically more likely to be fed into the quantisation process than larger errors. Therefore, in order to reduce the average distortion and loss introduced by the quantisation process, it is advantageous to quantise small input values relatively finely and large input values relatively coarsely, i.e. the quantised output values represent small inputs relatively precisely and large inputs relatively inaccurately. The inaccurate representation of large inputs is acceptable because they occur relatively infrequently in a statistical sense.
  • the quantised output values are limited to N bits, the corresponding 2 N input bands are not of equal size or range. Input bands that cover small input values are of relatively small size. As the input value increase, bands become wider.
  • FIG. 3 shows a widening of quantisation bands with increasing input size.
  • the non-linear distribution of quantisation bands means that it is non-trivial to determine which band a particular high-precision input value falls into.
  • the audio compression algorithm may adapt (i.e. change) the width of the quantisation bands dynamically, by linearly scaling the default (non-linearly distributed) input values that mark quantisation band boundaries.
  • the value used for the scaling, called ⁇ may be based on an estimate of the short-term standard deviation of the input signal to the quantisation, and adapts the width of quantisation bands to best cover the current degree of variation seen in the input signal.
  • the quantisation of the magnitude is of primary interest, which is performed on the absolute value of the high-precision input value and results in an N-1 bit output.
  • the default (non-linearly distributed) positive input values that mark quantisation band boundaries are stored in a look-up table (illustrated in Figures 5 to 9 ), or other suitable memory structure, which resides in processor memory (in this example Data Memory 2).
  • the quantisation band boundaries values are sorted according to value within the table (e.g. increasing values in the table are stored at locations with increasing table indices (addresses)). In alternative embodiments, it is possible to use an arrangement whereby increasing table values are stored in decreasing memory addresses. This would still allow the three-instruction cycle for each bisection search iteration that is described hereinafter.
  • quantisation table address offsets would be subtracted, rather than added, to the base address of the quantiser table.
  • the principal criterion for the search to work is that the quantisation table values are sorted (either ascending or descending).
  • This table is searched until the smallest table index, I min , is found for which the contents of the table at that index, when multiplied by the scaling value ⁇ (if applicable), exceeds the high-precision input value.
  • An alternative implementation would be to find the largest table index that gives a result less than or equal to the high-precision input value, assuming ascending quantisation table values are stored in ascending memory addresses.
  • the N-1 output bits for the quantised magnitude are then set to I min , i.e. the table indices serve in this example as the label, or quantized value, for the respective quantization band.
  • I min a table index
  • the base of the table may be located at any convenient memory address.
  • the table memory addresses run from 1000-1015 but the table indices run from 0 to 15. It is the table indices, not the physical memory addresses, that give the N-1 bits that form the absolute quantised value. This is concatenated with the single sign bit to give the (signed) N-bit quantised value.
  • the table searching process could be completed in a naive fashion by starting at the base of the table and incrementing the index by one until the table value multiplied by ⁇ just exceeds the high-precision input value.
  • this is inefficient, since many table entries may have to be tested incrementally before the correct one is found.
  • the search of the table is performed using a binary, or bisection, search technique, where the search procedure iteratively removes approximately half of the table indices that remain eligible as solutions. Therefore, the solution for a table containing 2 N-1 values is obtained in N-1 iterations.
  • Binary searching is not necessarily the fastest searching procedure but it is simple, easy to implement and is guaranteed to converge to the correct solution in all cases.
  • the MMU 93 and memory interface 90 are co-operable with one another to allow the two concurrent accesses to Data Memory 1 and Data Memory 2.
  • RThreshOffset A general-purpose processor register that holds an address offset such that a particular element of the table of default quantisation band boundaries can be accessed by accessing the memory address given by rThreshBase + rThreshOffset.
  • rOldThreshOffset A general-purpose processor register that holds the value of rThreshOffset from the previous iteration of the bisection search.
  • rThreshTableValue A general-purpose processor register that holds a particular value read from the table of default quantisation band boundaries residing in processor memory (Data Memory 2 in the present example).
  • rDelta A general-purpose processor register that holds the current value for the scaling factor ⁇ .
  • IbisOff A dedicated index (I) processor register that holds the memory address of an element of a "bisection offset" table.
  • I dedicated index
  • the IbisOff register may be implemented in the address generator 86, while the remaining registers identified above may be implemented in the register bank 84.
  • the bisection offset table comprises data held in processor memory 92 (for example in Data Memory 1 of Figure 4 ) and is indexed, or addressed, using the dedicated index register IbisOff.
  • the contents of the bisection offset table are descending powers of 2, with the first element containing the value 2 N-3 , where N is the number of bits in the quantised output, including the sign bit.
  • the final element of the table is a trailing value of zero, although. it could be any dummy value (it is read during the final search iteration but never used). It is desirable to keep all the search iterations the same so that the three search instructions can be repeated for the required number of iterations, without having to do a special instruction sequence for the final iteration.
  • the bisection offset table contains the following contents, listed from the first to last element: 16, 8,4, 2,1,0
  • the purpose of the bisection offset table is to generate successively lower powers of 2 by using incrementing memory accesses to a table. This could alternatively be performed by the ALU 88 of the processor 82 by taking the previous power of 2 and generating the new power of 2 by a 1-bit right shift of a binary value.
  • a problem with this approach is that the right shift is an arithmetic/logical operation and only one of these operations can be carried out by a single processor instruction.
  • up to two memory accesses can be carried out by a single processor instruction, so implementing the descending power of 2 generation using a table lookup allows the bisection search iteration to complete using fewer consecutive instructions.
  • the initialisation code causes the memory address (an address in Data Memory 1 in the example of Figure 4 ) of the absolute value of the high-precision input value to the quantisation process is calculated and stored by the processor 82.
  • this address value is stored in an index register in the address generator unit 86, because the processor does not support the particular double memory access format of instruction 1 in the 3-cycle bisection search iteration unless the high-precision input is read from memory via an index (I) register.
  • index (I) register In typical embodiments, in alternative embodiments it may be stored in any convenient location, e.g. the register bank 84.
  • the index register IbisOff is loaded with the address of the first element in the bisection offset table.
  • rT'hreshBase is loaded with the address of the first element in the table of default quantisation band boundaries, and both rThreshOffset and rOldThreshOffset are loaded with the value 2 N-2 , where N is the number of bits in the quantised output, including the sign bit.
  • the input value to the quantiser and the quantisation tables are stored in different data memories so that the first instruction in the bisection search iteration completes in a single clock cycle.
  • the bisection offset table is successively read from simple incrementing addresses.
  • the bisection search process causes the table base and table offset register values to "jump" by relatively large values from one search iteration to the next.
  • the high-precision input value and the quantisation band boundary table are stored in respective data memories (Data Memory 1 and Data Memory 2 respectively in the illustrated example).
  • the bisection offset table can be in either data memory, but is assumed to be in Data Memory 1 in the present example and the example shown in Figs 5-9 .
  • the memory addressing of the processor 82 is based on a flat memory model and so, from a software programming point of view Data Memory 1 and Data Memory 2 are addressed as 2 different regions in one larger address space. In other words, there is "continuity of addressing" of the 2 different memories.
  • the data memories 94 may be separate from one another, e.g. physically and electrically independent from one another, as shown in Figure 4 . Alternatively, they may be implemented as respective independently, or concurrently, accessible portions of the same memory (e.g. in a dual-port memory). Either arrangement allows two memory accesses to occur in the same processor clock cycle.
  • addresses below 1000 are in Data Memory 1 and addresses from 1000 up are in Data Memory 2. It is noted that the specific memory addresses shown in Figures 5-9 are given by way of illustration only and are not intended to correspond with actual memory addresses.
  • Figure 5 shows the state of the processor 82 after the initialisation steps described above.
  • the first processor instruction of the first bisection search iteration is now carried out, updating the state of the processor as shown in Figure 6 . It is noted that the values of rMAC and rThreshTableValue have been updated as a direct consequence of this instruction. The first row of Table 2 explains how the relevant operations have been performed.
  • the second processor instruction of the first bisection search iteration is now carried out, updating the state of the processor as shown in Figure 7 . It is noted that the values of rMAC and rThreshOffset have been updated as a direct consequence of this instruction. The second row of Table 2 explains how the relevant operations have been performed.
  • the third processor instruction of the first bisection search iteration is now carried out. Since this instruction behaves differently depending on whether the value in the register rMAC after the second instruction completes is positive or not, both cases are illustrated below.
  • the value in rMAC is positive. This means that the desired value in the default quantisation band boundary table is in the upper half of the table and it is this table region that should be promoted to the second search iteration.
  • the updated processor state after the third instruction is shown in Figure 8 .
  • the values of rThreshBase, IbisOff and rOldThreshOffset have been updated as a direct consequence of this instruction.
  • the third row of Table 2 explains how the relevant operations have been performed. Note also that the updated value in rThreshBase means that the second bisection search iteration will search only the table elements from address 1008 and above, i.e. the upper section of the table.

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Claims (15)

  1. Un appareil de compression d'un signal audio, l'appareil comprenant un processeur et une mémoire de données, le processeur comprenant une unité logique arithmétique et une pluralité de registres de données et étant programmable de façon à mettre en oeuvre une pluralité d'instructions de processeur, et où le processeur est capable d'exécuter, par rapport à une instruction de processeur unique, une opération arithmétique inconditionnelle et deux accès à la mémoire de données indépendants, ou une opération arithmétique conditionnelle et un accès à la mémoire de données, le processeur étant capable en outre d'amener une valeur contenue dans au moins un desdits registres de données qui est utilisé pour consulter ladite mémoire de données à être incrémentée, et où ledit appareil comprend en outre
    un premier ensemble de valeurs de données conservée en mémoire dans ladite mémoire de données, ledit premier ensemble comprenant des valeurs de données représentant chacune une limite de bande de quantification respective et étant triées dans ladite mémoire de données selon leurs valeurs respectives, et
    un deuxième ensemble de valeurs de données conservée en mémoire dans ladite mémoire de données, ledit deuxième ensemble comprenant au moins une valeur de données qui est une puissance de 2, les valeurs de données dudit deuxième ensemble étant triées dans ladite mémoire de données dans un ordre de valeur décroissante, et où
    un premier desdits registres de données (rThreshBase) possède, en utilisation, une adresse mémoire pour une première valeur de données dudit premier ensemble, un deuxième desdits registres de données (rThreshOffset) possède, en utilisation, une valeur de décalage d'adresse courante, un troisième desdits registres de données (rOldThreshOffset) possède, en utilisation, une valeur de décalage d'adresse antérieure, un quatrième desdits registres de données (rThreshTableValue) possède, en utilisation, une valeur de données obtenue par ledit processeur à partir dudit premier ensemble de données, un cinquième desdits registres de données (rMAC) possède, en utilisation, une valeur de données qui est le résultat d'un ou plusieurs calculs exécutés par ledit processeur par rapport à la valeur de données contenue dans ledit quatrième registre, et un sixième desdits registres de données (IbisOff) possède une adresse mémoire d'une valeur de données dans ledit deuxième ensemble de valeurs de données,
    et où, par rapport à chaque valeur d'une pluralité de valeurs d'entrée de recherche dérivées dudit signal audio et conservées en mémoire dans ladite mémoire de données, ledit appareil est agencé de façon à exécuter une recherche de bisection dudit premier ensemble de valeurs de données de façon à déterminer laquelle des valeurs de données dudit premier ensemble est la meilleure approximation de la valeur d'entrée respective, ladite recherche de bisection étant exécutée dans une ou plusieurs itérations où, par rapport à chaque itération de recherche, ledit processeur est agencé de façon :
    lors de l'exécution d'une première instruction de processeur, à lire la valeur d'entrée respective à partir d'une mémoire de données et à amener la valeur d'entrée à être placée en mémoire dans ledit cinquième registre de données, et à lire la valeur de données dudit premier ensemble dont l'adresse dans ladite mémoire de données correspond à l'adresse contenue dans ledit premier registre de données, décalée de la valeur de décalage d'adresse courante contenue dans ledit deuxième registre de données, et à amener ladite valeur de données à être placée en mémoire dans ledit quatrième registre de données, et
    lors de l'exécution d'une deuxième instruction de processeur, à calculer la différence entre la valeur d'entrée conservée en mémoire dans ledit cinquième registre de données et ladite valeur de données dudit premier ensemble qui est conservée en mémoire dans ledit quatrième registre de données, ou une valeur dérivée de celle-ci, et à amener la valeur résultante à être placée en mémoire dans ledit cinquième registre de données, et à lire la valeur de données dudit deuxième ensemble dont l'adresse dans ladite mémoire de données correspond à l'adresse contenue dans ledit sixième registre de données et à amener le résultat à être placé en mémoire dans ledit deuxième registre de données, et
    lors de l'exécution d'une troisième instruction de processeur, à ajuster, uniquement si ladite différence contenue dans ledit cinquième registre de données indique que l'itération suivante de la recherche de bisection devrait se dérouler dans une partie supérieure dudit premier ensemble de valeurs de données, l'adresse mémoire dans ledit premier registre de données selon le décalage conservée en mémoire dans ledit troisième registre de données et à amener l'adresse mémoire ajustée résultante à être placée en mémoire dans ledit premier registre de données (rThreshBase), à lire la valeur de données dudit deuxième ensemble dont l'adresse dans ladite mémoire de données correspond à l'adresse contenue dans ledit sixième registre de données et à amener le résultat à être placé en mémoire dans ledit troisième registre de données, et à amener l'adresse mémoire contenue dans le registre de données et à amener le résultat à être placé en mémoire dans ledit troisième registre de données [sic], et à amener l'adresse mémoire contenue dans ledit sixième registre de données à être incrémentée de façon à pointer vers la valeur de données suivante dans ledit deuxième ensemble.
  2. Un appareil selon la Revendication 1, où un septième desdits registres de données (rDelta) possède, en utilisation, une valeur courante d'un facteur d'échelle de bande de quantification, et où, lors de l'exécution de ladite deuxième instruction de processeur, ledit processeur est agencé de façon à calculer la différence entre la valeur d'entrée conservée en mémoire dans ledit cinquième registre de données et ladite valeur de données dudit premier ensemble qui est conservée en mémoire dans ledit quatrième registre de données multipliée par ledit facteur d'échelle, et à amener la valeur résultante à être placée en mémoire dans ledit cinquième registre de données.
  3. Un appareil selon la Revendication 1 ou 2, où, lors de l'exécution de ladite deuxième instruction de processeur, ledit processeur est agencé de façon à calculer ladite différence en soustrayant ladite valeur de données dudit premier ensemble qui est conservée en mémoire dans ledit quatrième registre de données, ou une valeur dérivée de celle-ci, de la valeur d'entrée conservée en mémoire dans ledit cinquième registre de données, et où, lors de l'exécution de ladite troisième instruction de processeur, le processeur est agencé de façon à ajuster l'adresse mémoire dans ledit premier registre de données uniquement si ladite différence est positive.
  4. Un appareil selon l'une quelconque des Revendications précédentes, où ledit cinquième registre de données est un registre de processeur à précision étendue qui possède le produit d'opérations de multiplication et de multiplication/accumulation sans perte de précision.
  5. Un appareil selon l'une quelconque des Revendications précédentes, où ledit premier ensemble de valeurs de données est trié dans ladite mémoire de données de sorte que des valeurs de données successives sont associées à des adresses successives dans ladite mémoire de données.
  6. Un appareil selon l'une quelconque des Revendications précédentes, où lesdites valeurs de données dans ledit premier ensemble sont triées et conservées en mémoire dans ladite mémoire de données de sorte que des valeurs de données croissantes sont conservées en mémoire dans des emplacements mémoire avec des adresses croissantes.
  7. Un appareil selon l'une quelconque des Revendications précédentes, agencé de façon à produire, par rapport à chacune desdites valeurs d'entrée de recherche, une valeur de sortie quantifiée comprenant N bits où N-1 bits représentent la valeur quantifiée et le bit restant indique si la valeur quantifiée de N-1 bits est positive ou négative.
  8. Un appareil selon la Revendication 7, où ledit deuxième ensemble de données comprend au moins N-2 valeurs de données, la première valeur de données dans ledit deuxième ensemble prenant la valeur 2N-3, les valeurs de données N-3 suivantes étant des puissances décroissantes successives de 2.
  9. Un appareil selon la Revendication 8, où ledit deuxième ensemble de données comprend N-1 valeurs de données comprenant une valeur de donnée fictive finale, par exemple définie sur zéro.
  10. Un appareil selon l'une quelconque des Revendications 7 à 9, où les deuxième et troisième registres de données sont initialisés avec la valeur 2N-2
  11. Un appareil selon l'une quelconque des Revendications précédentes, où lesdites valeurs d'entrée de recherche sont contenues dans une mémoire de données séparée, ou au moins dans une partie accessible séparément d'une mémoire de données commune, dudit premier ensemble de données.
  12. Un appareil selon l'une quelconque des Revendications 5 à 11, où chaque valeur de données dudit premier ensemble est associée à une valeur d'indice et où plusieurs itérations de ladite recherche de bisection sont exécutées jusqu'à ce que la valeur d'indice la plus petite (Imin) soit trouvée pour laquelle la valeur de données respective, lorsqu'elle est multipliée par ladite valeur d'échelle, si applicable, dépasse la valeur d'entrée de recherche, ou sinon jusqu'à ce que l'indice le plus élevé soit trouvé pour lequel la valeur de données respective est inférieure ou égale à la valeur d'entrée de recherche.
  13. Un appareil selon l'une quelconque des Revendications précédentes, où, avant une première itération de ladite recherche de bisection, l'adresse mémoire de la première valeur de données dans ledit deuxième ensemble de données est placée en mémoire dans ledit sixième registre de données.
  14. Un procédé de sélection de bandes de quantification pour un appareil selon la Revendication 1, le procédé comprenant, par rapport à chaque valeur d'une pluralité de valeurs d'entrée de recherche dérivées dudit signal audio et conservées en mémoire dans ladite mémoire de données, l'exécution d'une recherche de bisection dudit premier ensemble de valeurs de données de façon à déterminer laquelle des valeurs de données dans ledit premier ensemble est la meilleure approximation de la valeur d'entrée respective, ladite recherche de bisection étant exécutée dans une ou plusieurs itérations où, par rapport à chaque itération de recherche, ledit procédé comprend :
    la lecture, lors de l'exécution d'une première instruction de processeur, de la valeur d'entrée respective à partir d'une mémoire de données et le fait d'amener la valeur d'entrée à être placée en mémoire dans ledit cinquième registre de données, la lecture de la valeur de données dudit premier ensemble dont l'adresse dans ladite mémoire de données correspond à l'adresse contenue dans ledit premier registre de données décalée de la valeur de décalage d'adresse courante contenue dans ledit deuxième registre de données, et le fait d'amener ladite valeur de données à être placée en mémoire dans ledit quatrième registre de données, et
    le calcul, lors de l'exécution d'une deuxième instruction de processeur, de la différence entre la valeur d'entrée conservée en mémoire dans ledit cinquième registre de données et ladite valeur de données dudit premier ensemble qui est conservée en mémoire dans ledit quatrième registre de données, ou une valeur dérivée de celle-ci, le fait d'amener la valeur résultante à être placée en mémoire dans ledit cinquième registre de données, et la lecture de la valeur de données dudit deuxième ensemble dont l'adresse dans ladite mémoire de données correspond à l'adresse contenue dans ledit sixième registre de données et le fait d'amener le résultat à être placé en mémoire dans ledit deuxième registre de données, et
    lors de l'exécution d'une troisième instruction de processeur, l'ajustement,
    uniquement si ladite différence contenue dans ledit cinquième registre de données indique que l'itération suivante de la recherche de bisection devrait se dérouler dans une partie supérieure dudit premier ensemble de valeurs de données, de l'adresse mémoire dans ledit premier registre de données selon ledit décalage conservée en mémoire dans ledit troisième registre de données et le fait d'amener l'adresse mémoire ajustée résultante à être placée en mémoire dans ledit premier registre de données (rThreshBase), la lecture de la valeur de données dudit deuxième ensemble dont l'adresse dans ladite mémoire de données correspond à l'adresse contenue dans ledit sixième registre de données et le fait d'amener le résultat à être placé en mémoire dans ledit troisième registre de données, et le fait d'amener l'adresse mémoire contenue dans ledit sixième registre de données à être incrémentée de façon à pointer vers la valeur de données suivante dans ledit deuxième ensemble.
  15. Un programme informatique contenant du code de programme informatique conservé en mémoire dans un support utilisable par un ordinateur et agencé de façon à amener le processeur de l'appareil selon la Revendication 1 à exécuter le procédé selon la Revendication 14.
EP09008170A 2009-06-22 2009-06-22 Appareil et procédé de sélection de bandes de quantification dans des encodeurs audio Active EP2267700B1 (fr)

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EP09008170A EP2267700B1 (fr) 2009-06-22 2009-06-22 Appareil et procédé de sélection de bandes de quantification dans des encodeurs audio
AT09008170T ATE538470T1 (de) 2009-06-22 2009-06-22 Vorrichtung und verfahren zum auswählen von quantisierungsbändern in audiokodierern

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