EP2179356A1 - Compilation de programmes informatiques pour processeurs multic urs et leur réalisation - Google Patents

Compilation de programmes informatiques pour processeurs multic urs et leur réalisation

Info

Publication number
EP2179356A1
EP2179356A1 EP07786690A EP07786690A EP2179356A1 EP 2179356 A1 EP2179356 A1 EP 2179356A1 EP 07786690 A EP07786690 A EP 07786690A EP 07786690 A EP07786690 A EP 07786690A EP 2179356 A1 EP2179356 A1 EP 2179356A1
Authority
EP
European Patent Office
Prior art keywords
threads
program
execution
target
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP07786690A
Other languages
German (de)
English (en)
Inventor
Rainer FÖRTSCH
Christian Strömsdörfer
Frank Volkmann
Michael Wieczorek
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP2179356A1 publication Critical patent/EP2179356A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/45—Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions

Definitions

  • the invention relates to a method for compiling a source program into a target program for a target system with a multicore processor, a method for executing said target program on the target system with the multicore processor and a device that is suitable for executing the target program.
  • the invention is used wherever time-critical processes are to be controlled in real time using a multicore processor.
  • An example of this is called automation technology, in which a large number of sensors must be read in the industrial sector, the corresponding data must be processed in order to generate corresponding control signals for a large number of actuators.
  • the data processing steps carried out in this case must be performed by a programmable logic controller, while maintaining specified real-time conditions, with the shortest possible processing time is sought by the CPU.
  • So-called multicore processors are able to perform different tasks in a computer in parallel or asymmetrically multithreading, thus shortening the overall execution time of computer programs.
  • a software developer of a computer program can use the parallel processing capability of such a multicore processor by dividing its program into several threads. The individual threads can be executed in parallel on several main processors of the multicore processor, so that the overall execution time of the program is considerably reduced compared to conventional single-processor CPUs.
  • the distribution of the threads to the various main processors is performed by an operating system scheduler. In general, the scheduler assigns time slices to the threads with priority control. Prioritizing threads can be used by the software developer to create the computer program.
  • the invention has for its object to accelerate the execution of computer programs on systems with multicore processors.
  • This object is achieved by a method for compiling a source program having at least two threads into a target program executable on a real-time target system with a multicore processor, wherein a runtime information is generated during compilation for each of the at least two threads, which determines the target system the time required to execute the associated thread before it executes.
  • the object is achieved by a computer program product with program code means for carrying out such a method when said computer program product is executed on a data processing system.
  • the object is further achieved by an apparatus for executing a target program compiled from a source program having at least two threads according to such a method, the apparatus comprising a multi-core processor and a real-time operating system for determining the time required for executing each of includes at least two threads based on the associated runtime information prior to the execution of the threads.
  • the invention is based on the finding that the distribution of the threads can be carried out considerably more efficiently by a scheduler of an operating system, if this scheduler at runtime can make a prediction about its time requirement during execution even before the execution of the threads.
  • the runtime information, from which the scheduler can determine the time required is already generated during the compilation of the source program. The fact that this information is generated automatically during the compile time by a code analysis, the software developer is also relieved, since he himself must make no manual distribution of the individual threads on the various main processors of the multicore processor.
  • the runtime information characterizes the runtime of the associated thread as a function of the resources available for the execution of the associated thread.
  • the resources available to run the threads at runtime are usually unknown to the compiler. However, these can be determined by the scheduler at runtime before the threads are distributed to the various main processors, so that the scheduler can determine the time requirement of each thread based on the runtime information.
  • the runtime information is stored as an additional data segment within the target program. If the runtime information is made available to the scheduler as a file segment of, for example, a PE file or ELF file, it can fine-tune the tasks or tasks to be performed with the aid of data determined at runtime. men. In this way, effective use of the CPUs of the multicore processor and faster processing of the computer program are achieved.
  • an embodiment of the invention is advantageous in which the source program is a control program for a programmable logic controller.
  • the object is also achieved by a method for executing a target program on a real-time target system with a multicore processor, wherein the target program has been compiled according to a method according to one of the embodiments described above from the source program with the at least two threads, the time required
  • Executing each of the at least two threads is determined based on the associated runtime information before the execution of the threads.
  • the object is achieved by a computer program product containing program code means for carrying out such a method when said computer program product is executed on a real-time capable data processing system.
  • a computer program compiled according to the above-described method makes the runtime information available for execution so that it can be evaluated by the target system prior to the execution of the threads in order to enable an optimized distribution of the threads to the available hardware resources.
  • the at least two threads are automatically distributed with a scheduler of the target system as a function of their respective time requirement on main processors of the multicore processor. A manual distribution of the threads on the various main processors by the software developer is therefore no longer necessary.
  • the runtime behavior of the target program characterizing measured variables is determined during the runtime of the target program and the time requirement of each of the at least two Threads based on their runtime information and metrics.
  • Such measures can be, for example, the number of memory accesses as well as the number of cache misses.
  • FIG. 1 shows a schematic representation of a method for compiling a computer program with several
  • FIG. 2 shows a data processing system for compiling and a programmable logic controller for executing the computer program.
  • FIG. 1 shows a schematic representation of a method for compiling a computer program having a plurality of threads 2, 3 for a multicore processor system and its execution.
  • the computer program is initially available in the form of a source program 1.
  • two threads 2, 3 are provided with reference numerals by way of example, wherein the source program 1 still includes more threads that are not explicitly shown here for reasons of clarity.
  • the target program 4 created here contains an additional data segment 11.
  • Runtime information 7, 8 is stored within the additional data segment 11, by means of which a real-time operating system 9 with a scheduler 13 at runtime of the Target program 4 can determine the time requirement of the individual threads 2,3.
  • the runtime information 7, 8 are already generated during the compilation process based on a code analysis and serve to optimize the parallelization of the individual threads 2, 3 on the target hardware at the later runtime of the machine program.
  • the finished compiled target program 4 is to be executed on a real-time target system with a multicore processor 6.
  • the multicore processor 6 naturally contains a number of main processors 10, with which different tasks, processes or threads can be executed in parallel.
  • the scheduler 13 analyzes the execution of the target program 4 on the target hardware during the execution of the target program 4. For example, it determines the number of memory accesses and the cache misses, etc. that occur during the processing of the program instructions. If such measured quantities are available even before the execution of one of the threads 2, 3, then it links this information with the runtime information of the still executing threads 2, 3 and can then make a relatively accurate statement about the execution time that the still outstanding threads 2, 3 will need.
  • the scheduler carries out a distribution of the threads 2, 3 still to be processed, to the available main processors 10, which leads to an optimal efficiency and utilization of the main processors 10 during the execution of the target program 4.
  • 2 shows a data processing system 12 for compiling and a programmable logic controller 5 for executing the computer program, which has already been discussed under the description of FIG.
  • the figure shows a software developer 15, which generates the source program 1 with the aid of the data processing system 12, which is a conventional PC or laptop. Within the source program 1, it defines individual threads 2, 3, of which again, for reasons of clarity, only two are shown explicitly and provided with reference numerals.
  • a compiler is installed, which performs a code analysis during the compiling of the source program 1. The result of this code analysis is in each case a runtime information item 7, 8, which is created for each thread 2, 3 of the source program 1. This runtime information 7,8 is written into a new data segment 11, which is an extension of known executable files such as PE or ELF files.
  • the finished compiled target program 4 is then loaded by the data processing system 12 onto a programmable logic controller 5 to be executed by it to control an industrial automated process.
  • the programmable logic controller 5 comprises a multicore processor, which guarantees a much faster processing time of the target program 4 in comparison with a single-processor embodiment.
  • a real-time operating system is installed on the PLC 5, which, based on the runtime information 7, 8 stored in the data segment 11, has an optimized distribution of the threads 2, 3 with regard to the total execution time of the target program 4 the various main processors of the multicore processor.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Stored Programmes (AREA)

Abstract

L'invention concerne un procédé de compilation d'un programme source (1) avec au moins deux unités d'exécution (2, 3) dans un programme cible (4) pour un système cible en temps réel avec un processeur multicœur (6), un procédé de réalisation dudit programme cible (4) sur le système cible ainsi qu'un dispositif qui convient à la réalisation du programme cible (4). Pour accélérer la réalisation du programme cible (4), l'invention propose de générer, pour chacune des deux unités d'exécution (2, 3) ou plus, une information de temps de transit (7, 8) lors de la compilation, ce qui permet au système cible de calculer le temps nécessaire à l'exécution de l'unité d'exécution (2, 3) correspondante avant celle-ci.
EP07786690A 2007-08-16 2007-08-16 Compilation de programmes informatiques pour processeurs multic urs et leur réalisation Withdrawn EP2179356A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2007/007261 WO2009021539A1 (fr) 2007-08-16 2007-08-16 Compilation de programmes informatiques pour processeurs multicœurs et leur réalisation

Publications (1)

Publication Number Publication Date
EP2179356A1 true EP2179356A1 (fr) 2010-04-28

Family

ID=38586808

Family Applications (1)

Application Number Title Priority Date Filing Date
EP07786690A Withdrawn EP2179356A1 (fr) 2007-08-16 2007-08-16 Compilation de programmes informatiques pour processeurs multic urs et leur réalisation

Country Status (2)

Country Link
EP (1) EP2179356A1 (fr)
WO (1) WO2009021539A1 (fr)

Families Citing this family (1)

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Publication number Priority date Publication date Assignee Title
CN103970580B (zh) * 2014-05-05 2017-09-15 华中科技大学 一种面向多核集群的数据流编译优化方法

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Publication number Priority date Publication date Assignee Title
GB0212176D0 (en) * 2002-05-27 2002-07-03 Radioscape Ltd Stochasitc scheduling in CVM
JP3889726B2 (ja) * 2003-06-27 2007-03-07 株式会社東芝 スケジューリング方法および情報処理システム
US20060150188A1 (en) * 2004-12-21 2006-07-06 Manuel Roman Method and apparatus for supporting soft real-time behavior
JP4082706B2 (ja) * 2005-04-12 2008-04-30 学校法人早稲田大学 マルチプロセッサシステム及びマルチグレイン並列化コンパイラ

Non-Patent Citations (1)

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Title
See references of WO2009021539A1 *

Also Published As

Publication number Publication date
WO2009021539A1 (fr) 2009-02-19

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