EP2174228B1 - Discrete hot swap and overcurrent-limiting circuit - Google Patents
Discrete hot swap and overcurrent-limiting circuit Download PDFInfo
- Publication number
- EP2174228B1 EP2174228B1 EP08796465A EP08796465A EP2174228B1 EP 2174228 B1 EP2174228 B1 EP 2174228B1 EP 08796465 A EP08796465 A EP 08796465A EP 08796465 A EP08796465 A EP 08796465A EP 2174228 B1 EP2174228 B1 EP 2174228B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- protection circuit
- circuit
- input
- backplane
- discrete
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Not-in-force
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4081—Live connection to bus, e.g. hot-plugging
Definitions
- the present invention is generally related to a communications system and, more particularly, is related to systems, methods, and apparatus for connecting circuit cards with discrete hot swap and overcurrent-limiting circuits to a live backplane.
- EP-A1-0,661,643 discloses a circuit for controlling current in an adapter card, including a biasing circuit controlling an FET/feedback circuit, which acts as a constant current source, a timer circuit and a latch circuit for turning off the FET upon sensing of a transient current through the load.
- the present invention is directed towards a discrete protection circuit that allows connection or removal of a protected circuit card from a live backplane without any service interruptions.
- the power that is supplied by the backplane to other connected circuit cards is not affected by the connection or removal of a circuit card.
- the discrete protection circuit is located on the circuit card and limits the current inflow to that circuit card. Due to the limited current flow, the voltage across the backplane remains constant. Additionally, the discrete protection circuit is used as an overcurrent-limiting circuit.
- a circuit card equipped with the discrete protection circuit can immediately detect a possible short circuit on the card, which may be caused by faulty component(s), and can limit the input current to protect the circuit card and the backplane; thereby avoiding a complete shutdown of the system.
- FIG. 1 is an abridged block diagram of a communications system 110 that is suitable for use in implementing the present invention.
- a communications system 110 includes a transport network 115 and a transmission network 120.
- the transport network 115 which is fiber optic cable, connects a headend 125 and hubs 130 for generating, preparing, and routing programs and other optical packets over longer distances; whereas a transmission network 120, which is coaxial cable, generally routes electrical packets over shorter distances.
- Programs and other information packets received, generated, and/or processed by headend equipment racked in backplanes is either broadcasted to all subscribers in the system 110, or alternatively, the programs can be selectively delivered to one or more subscribers.
- Fiber optic cable 135 connects the transport network 115 to an optical node(s) 140 that converts the packets from optical packets into electrical packets. Thereafter, coaxial cable 145 routes the packets to one or more subscriber premises 150a-d.
- subscriber premises equipment In the reverse, or upstream, direction, subscriber premises equipment, such as set-top boxes or cable modems, generate reverse electrical signals.
- the optical node 140 which includes an optical transmitter, converts the reverse electrical signals into optical signals for further routing to backplane equipment at the hubs 130.
- the backplane equipment in the hubs 130 then route the optical signals to the equipment in the headend 125 for further processing.
- FIG. 2 is a block diagram of a backplane, which may be located in the headend 125 and/or hubs 130, for receiving and powering conventional equipment, such as circuit cards.
- a live backplane 205 is configured to accept a plurality of circuit cards 210, 215 via a connector 220, 225.
- the circuit cards 210, 215 typically include many active components and circuits, such as microprocessors and Field Programmable Gate Arrays (FPGAs), which require power in order to generate the appropriate signals.
- FPGAs Field Programmable Gate Arrays
- circuit card 210 is connected to the live backplane 205 and circuit card 215 is about to be connected with the live backplane 205.
- circuit cards 210, 215 do not include a circuit that limits the power, a rush of current is drawn from the backplane 205 through circuit card 215 when circuit card 215 is connected.
- the rush of current can cause in a voltage drop across the backplane 205, thereby potentially disrupting the operation of the connected circuit cards and the overall system operation.
- FIG. 3 illustrates the drop in voltage when conventional circuit cards are connected to a live backplane.
- the voltage across the backplane which powers all the connected circuit cards, is 24 Vdc.
- the voltage across the backplane drops significantly.
- active components on any of the previously connected circuit cards 210 are susceptible to the drop in voltage.
- the active components on the newly connected circuit card 215 may be adversely affected by the ensuing rush of current through the circuit card 215.
- FIG. 4 is an illustration of a schematic of an exemplary embodiment of the discrete protection circuit of the present invention that provides a hot swap and over current-limiting circuit.
- the discrete circuit 400 is preferably included on each circuit card 505, 510 that will be connected to or removed from the live backplane 205 for ultimate protection as shown in FIG. 5 .
- An input pin 405 to the discrete circuit 400 connects to the backplane 205 so that power passes through the discrete circuit 400 prior to any other components on the circuit card 505, 510. In this manner, the discrete circuit 400 is able to limit the inrush of current when it connects to the live backplane 205, thereby preventing a subsequent drop in voltage across the backplane 205.
- an on/off pin 410 can be set to the on position in order to protect the circuit card 505, 510. Alternatively, it can be used manually if a user wishes to turn on and off the power to the circuit card 505, 510 when it is inserted into a backplane 205.
- the discrete circuit 400 includes a sense resistor R3 to detect an overcurrent condition, a discrete SCR 435 which latches when an overcurrent condition is detected, and a switch Q5 to control an output load current, so that no load current is delivered when an overcurrent condition is detected
- a transistor Q3 of the circuit 400 is turned on. When transistor Q3 is turned on, it will initiate the charging of the capacitor C1. Once the voltage across capacitor C1 exceeds the gate threshold voltage of a switch Q5, an input source 405 is connected to the output load 430 (i.e., to the load components on the circuit card) through the switch Q5.
- FIG. 6 is a block diagram illustrating the current-limiting function of the discrete circuit of FIG. 4 .
- a load circuit such as a microprocessor or FPGA
- the discrete circuit 400 prevents the short from damaging the circuit card 505 by limiting the available current from the input 405.
- resistor R3 senses the load current at output 430. More specifically, the load current passes through resistor R3 and switch Q5. The load current through resistor R3 develops a proportional voltage across it that is sensed by transistor gates Q1 and Q4 to detect a fault condition.
- SCR 435 Silicon Controlled Rectifier 435, formed by transistors Q1 and Q4, will go into a latch state. This will restrict the input voltage at the gate of switch Q5, and in turn will shut switch Q5 off. Concurrently, capacitor C1 will discharge through Q1 and Q4. As soon as the capacitor C1 is completely discharged, SCR 435 turns off. Switch Q5 remains off until capacitor C1 is charged back above the gate threshold voltage of the switch Q5. Capacitor C1 charge time can be controlled by selecting appropriate values for resistors R1 and R2. Additionally, capacitor C1 charge time controls a retry delay following the detection of the over-current condition.
- Switch Q5, transistor Q1 and transistor Q4, which form the SCR 435, resistor R1, resistor R2, and capacitor C1 form a circuit that has a fast initial response to changes in load current, for example, due to plugging the circuit card into a live backplane, and yet also allows a designer to set the retry delay.
- the retry delay is a predetermined time following a fault condition that the discrete circuit 400 takes before it retries to deliver current back to the load. In this manner, when the fault is cleared, the discrete circuit 400 then retries after the predetermined time and resumes normal operation.
- the retry delay is also useful during a cold start (i.e., an initial turn-on of the circuit card) where large load capacitors located on the circuit card are required to be charged with limited input current. Furthermore, the retry delay also keeps switch Q5 dissipation under control during an output short circuit condition.
- the discrete protection circuit of the invention offers distinct advantages over prior art integrated circuits that are designed for hotswap and current-limiting applications. For instance, integrated circuit overcurrent protection circuits are relatively expensive as they are typically single sourced and designed for particular applications. The present invention, however, can be made of relatively inexpensive parts that are easily accessible from a variety of sources. Furthermore, because they are single sourced, most integrated circuits for hot swap applications are not compatible with each other. The present invention provides a hot swap overcurrent protection circuit that is suitable and cost-effective for a variety of applications. The protection circuit of the present invention also has a lower parts count and an increased reliability.
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Direct Current Feeding And Distribution (AREA)
- Power Sources (AREA)
- Emergency Protection Circuit Devices (AREA)
Abstract
Description
- The present invention is generally related to a communications system and, more particularly, is related to systems, methods, and apparatus for connecting circuit cards with discrete hot swap and overcurrent-limiting circuits to a live backplane.
- Integration of hot swap and overcurrent-limiting circuits are becoming an essential part of modem systems since any system downtime is unacceptable before and during any system hardware upgrades. Although there are many integrated circuits in the market today that handle these functions, they are expensive and single-sourced. Therefore, there is a need to address the issues of performing hot swaps as well as providing current- limiting protection with a simple and cost effective solution.
-
EP-A1-0,661,643 discloses a circuit for controlling current in an adapter card, including a biasing circuit controlling an FET/feedback circuit, which acts as a constant current source, a timer circuit and a latch circuit for turning off the FET upon sensing of a transient current through the load. - Aspects of the invention are set out in the independent claims and preferred features are set out in the dependent claims.
- The invention can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present invention. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.
-
FIG. 1 is an abridged block diagram of a communications system that is suitable for use in implementing the present invention. -
FIG. 2 is a block diagram of a backplane for receiving and powering conventional circuit cards. -
FIG. 3 illustrates the drop in voltage across a backplane when unprotected circuit cards are connected thereto.FIG. 4 is an illustration of a schematic of the discrete protection circuit of the present invention. -
FIG. 5 is a block diagram of the live backplane for receiving and powering circuit cards including the discrete protection circuit ofFIG. 4 . -
FIG. 6 is a block diagram illustrating the current- limiting function of the discrete protection circuit ofFIG. 4 . - The invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. The invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Furthermore, all "examples" given herein are intended to be non-limiting.
- The present invention is directed towards a discrete protection circuit that allows connection or removal of a protected circuit card from a live backplane without any service interruptions. Importantly, the power that is supplied by the backplane to other connected circuit cards is not affected by the connection or removal of a circuit card. More specifically, the discrete protection circuit is located on the circuit card and limits the current inflow to that circuit card. Due to the limited current flow, the voltage across the backplane remains constant. Additionally, the discrete protection circuit is used as an overcurrent-limiting circuit. A circuit card equipped with the discrete protection circuit can immediately detect a possible short circuit on the card, which may be caused by faulty component(s), and can limit the input current to protect the circuit card and the backplane; thereby avoiding a complete shutdown of the system.
-
FIG. 1 is an abridged block diagram of acommunications system 110 that is suitable for use in implementing the present invention. Typically, acommunications system 110 includes atransport network 115 and atransmission network 120. Thetransport network 115, which is fiber optic cable, connects aheadend 125 andhubs 130 for generating, preparing, and routing programs and other optical packets over longer distances; whereas atransmission network 120, which is coaxial cable, generally routes electrical packets over shorter distances. Programs and other information packets received, generated, and/or processed by headend equipment racked in backplanes is either broadcasted to all subscribers in thesystem 110, or alternatively, the programs can be selectively delivered to one or more subscribers. Fiberoptic cable 135 connects thetransport network 115 to an optical node(s) 140 that converts the packets from optical packets into electrical packets. Thereafter,coaxial cable 145 routes the packets to one or moresubscriber premises 150a-d. - In the reverse, or upstream, direction, subscriber premises equipment, such as set-top boxes or cable modems, generate reverse electrical signals. The
optical node 140, which includes an optical transmitter, converts the reverse electrical signals into optical signals for further routing to backplane equipment at thehubs 130. The backplane equipment in thehubs 130 then route the optical signals to the equipment in theheadend 125 for further processing. -
FIG. 2 is a block diagram of a backplane, which may be located in theheadend 125 and/orhubs 130, for receiving and powering conventional equipment, such as circuit cards. Alive backplane 205 is configured to accept a plurality ofcircuit cards connector circuit cards FIG. 2 ,circuit card 210 is connected to thelive backplane 205 andcircuit card 215 is about to be connected with thelive backplane 205. If thecircuit cards backplane 205 throughcircuit card 215 whencircuit card 215 is connected. The rush of current can cause in a voltage drop across thebackplane 205, thereby potentially disrupting the operation of the connected circuit cards and the overall system operation. -
FIG. 3 illustrates the drop in voltage when conventional circuit cards are connected to a live backplane. Prior tocircuit card 215 being connected to thelive backplane 205, the voltage across the backplane, which powers all the connected circuit cards, is 24 Vdc. At thetime 305circuit card 215 is connected tobackplane 205, the voltage across the backplane drops significantly. As mentioned, active components on any of the previously connectedcircuit cards 210 are susceptible to the drop in voltage. Furthermore, the active components on the newly connectedcircuit card 215 may be adversely affected by the ensuing rush of current through thecircuit card 215. -
FIG. 4 is an illustration of a schematic of an exemplary embodiment of the discrete protection circuit of the present invention that provides a hot swap and over current-limiting circuit. Thediscrete circuit 400 is preferably included on eachcircuit card live backplane 205 for ultimate protection as shown inFIG. 5 . Aninput pin 405 to thediscrete circuit 400 connects to thebackplane 205 so that power passes through thediscrete circuit 400 prior to any other components on thecircuit card discrete circuit 400 is able to limit the inrush of current when it connects to thelive backplane 205, thereby preventing a subsequent drop in voltage across thebackplane 205. Prior to a hot swap, an on/offpin 410 can be set to the on position in order to protect thecircuit card circuit card backplane 205. - As shown in the exemplary embodiment of
FIG. 4 , thediscrete circuit 400 includes a sense resistor R3 to detect an overcurrent condition, adiscrete SCR 435 which latches when an overcurrent condition is detected, and a switch Q5 to control an output load current, so that no load current is delivered when an overcurrent condition is detected When the on/offpin 410 is turned on, for example a logic high is associated with the on/offpin 410, and power is supplied to thediscrete circuit 400, a transistor Q3 of thecircuit 400 is turned on. When transistor Q3 is turned on, it will initiate the charging of the capacitor C1. Once the voltage across capacitor C1 exceeds the gate threshold voltage of a switch Q5, aninput source 405 is connected to the output load 430 (i.e., to the load components on the circuit card) through the switch Q5. -
FIG. 6 is a block diagram illustrating the current-limiting function of the discrete circuit ofFIG. 4 . If, for example, a load circuit, such as a microprocessor or FPGA, fails oncircuit card 505, thediscrete circuit 400 prevents the short from damaging thecircuit card 505 by limiting the available current from theinput 405. In operation, resistor R3 senses the load current atoutput 430. More specifically, the load current passes through resistor R3 and switch Q5. The load current through resistor R3 develops a proportional voltage across it that is sensed by transistor gates Q1 and Q4 to detect a fault condition. If a voltage drop across resistor R3 is greater than the emitter-base (E-B) diode drop of transistor Q1, then Silicon Controlled Rectifier (SCR) 435, formed by transistors Q1 and Q4, will go into a latch state. This will restrict the input voltage at the gate of switch Q5, and in turn will shut switch Q5 off. Concurrently, capacitor C1 will discharge through Q1 and Q4. As soon as the capacitor C1 is completely discharged,SCR 435 turns off. Switch Q5 remains off until capacitor C1 is charged back above the gate threshold voltage of the switch Q5. Capacitor C1 charge time can be controlled by selecting appropriate values for resistors R1 and R2. Additionally, capacitor C1 charge time controls a retry delay following the detection of the over-current condition. - Switch Q5, transistor Q1 and transistor Q4, which form the
SCR 435, resistor R1, resistor R2, and capacitor C1 form a circuit that has a fast initial response to changes in load current, for example, due to plugging the circuit card into a live backplane, and yet also allows a designer to set the retry delay. The retry delay is a predetermined time following a fault condition that thediscrete circuit 400 takes before it retries to deliver current back to the load. In this manner, when the fault is cleared, thediscrete circuit 400 then retries after the predetermined time and resumes normal operation. The retry delay is also useful during a cold start (i.e., an initial turn-on of the circuit card) where large load capacitors located on the circuit card are required to be charged with limited input current. Furthermore, the retry delay also keeps switch Q5 dissipation under control during an output short circuit condition. - The discrete protection circuit of the invention offers distinct advantages over prior art integrated circuits that are designed for hotswap and current-limiting applications. For instance, integrated circuit overcurrent protection circuits are relatively expensive as they are typically single sourced and designed for particular applications. The present invention, however, can be made of relatively inexpensive parts that are easily accessible from a variety of sources. Furthermore, because they are single sourced, most integrated circuits for hot swap applications are not compatible with each other. The present invention provides a hot swap overcurrent protection circuit that is suitable and cost-effective for a variety of applications. The protection circuit of the present invention also has a lower parts count and an increased reliability.
- Accordingly, systems and methods have been described regarding a discrete protection circuit that provides protection to circuit cards that are attached to a live backplane. It should be emphasized that the above-described embodiments of the present invention, particularly, any "preferred" embodiments, are merely possible examples of implementations, merely set forth for a clear understanding of the principles of the invention. Many variations and modifications may be made to the above-described embodiment(s) of the invention without departing substantially from the scope of the claims. All such modifications and variations are intended to be included herein within the scope of the following claims.
Claims (15)
- A discrete protection circuit (400) for protecting a circuit card (510) adapted to couple to a live backplane (205), the backplane (205) providing a backplane voltage to the circuit card (510), the protection circuit (400) comprising:a first capacitor coupled to an input (405) and adapted to accumulate a charge based on a voltage at the input;a sense resistor adapted to sense a load current and have a voltage proportional to the load current so that an overcurrent condition can be detected by sensing the voltage across the sense resistor;a switch adapted to control the load current delivered from the input to an output port;a discrete Silicon Controller Rectifier, hereinafter referred to as SCR, (435) adapted to latch when an overcurrent condition is detected, thereby preventing the flow of the load current to the output port; characterized in that the protection circuit further comprisesa series of two resistors coupled between the input (405) and ground, the series of two resistors adapted to set a charge time for the first capacitor, the charge time controlling the retry delay subsequent to the detection of an overcurrent condition.
- The protection circuit of claim 1, further comprising:an on/off pin (410) adapted to turn the discrete overcurrent protection circuit on and off; anda control transistor connected between the series of two resistors and ground, the control transistor adapted to turn on when the on/off pin is in an on position, thereby initiating charging of the first capacitor.
- The protection circuit of claim 1, the SCR (435) comprising a first transistor with a base-emitter voltage and adapted to turn off the switch when the load current resistor voltage exceeds the base-emitter voltage.
- The protection circuit of claim 1, wherein the first capacitor discharges through the SCR (435) when the switch is turned off.
- The protection circuit of claim 1, wherein the charge time of the capacitor can be controlled by selecting the appropriate values of the series of two resistors.
- The protection circuit of claim 1, wherein the series of two resistors further comprises:a first resistor connected between the input and an intermediate node, anda second resistor connected between the intermediate node and the ground, and wherein the switch has a control input that is coupled to the intermediate node for controlling operation of the switch.
- The protection circuit of claim 6, wherein the first capacitor and the SCR (435) each is connected in parallel with each other between the input and the intermediate node, such that the switch is operated to prevent the flow of the load current to the output in response to the SCR being latched.
- A system comprising:a live backplane (205) adapted to provide a backplane voltage to one or more circuit cards (505, 510) connected thereto; and
at least one protected circuit card (510) adapted to couple to the live backplane, the protected circuit card including a discrete protection circuit (400) according to any of Claims 1 to 7. - The system of claim 8, wherein at least one circuit card is connected to the live backplane (205).
- The system of claim 9, wherein the voltage provided to the at least one connected circuit card remains constant while a protected circuit card (510) is being connected to the live backplane (205).
- The system of claim 8, wherein at least one protected circuit card (505) is coupled to the backplane (205).
- A method of providing a discrete protection circuit (400), comprising:providing a first capacitor connected to receive an input (405) and accumulate a charge based on the input;providing a sense resistor adapted to sense a load current and have a voltage proportional to the load current so that an overcurrent condition can be detected by sensing the voltage across the sense resistor;providing a switch to control the load current delivered from the input (405) to an output port;providing a discrete SCR (435) adapted to latch when an overcurrent condition is detected, thereby preventing the flow of the load current to the output port; andproviding a series of two resistors coupled between the input (405) and ground, the series of two resistors adapted to set a charge time for the first capacitor, the charge time controlling the retry delay following the turning off of the switch due to the detection of an overcurrent condition.
- The method of claim 12, further comprising:providing an on/off pin (410) adapted to turn the discrete protection circuit on and off; andproviding a control transistor connected between the series of two resistors and ground, the control transistor adapted to turn on when the on/off pin is in an on position, thereby initiating the charging of the first capacitor.
- The method of claim 12, further comprising providing an input from a live backplane (205) to the protection circuit.
- The method of claim 12, further comprising coupling the protection circuit (400) to electrical components to form a protected circuit board (510).
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/829,112 US7813095B2 (en) | 2007-07-27 | 2007-07-27 | Discrete hot swap and overcurrent-limiting circuit |
PCT/US2008/070843 WO2009018036A1 (en) | 2007-07-27 | 2008-07-23 | Discrete hot swap and overcurrent-limiting circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
EP2174228A1 EP2174228A1 (en) | 2010-04-14 |
EP2174228B1 true EP2174228B1 (en) | 2012-02-01 |
Family
ID=39821515
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP08796465A Not-in-force EP2174228B1 (en) | 2007-07-27 | 2008-07-23 | Discrete hot swap and overcurrent-limiting circuit |
Country Status (5)
Country | Link |
---|---|
US (1) | US7813095B2 (en) |
EP (1) | EP2174228B1 (en) |
AT (1) | ATE544117T1 (en) |
CA (1) | CA2693415C (en) |
WO (1) | WO2009018036A1 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102035165B (en) * | 2009-09-29 | 2014-07-30 | 意法半导体研发(上海)有限公司 | System and method for providing short-circuit protection |
US8680893B2 (en) | 2011-10-05 | 2014-03-25 | Analog Devices, Inc. | Circuits and techniques for load current control |
US20130150812A1 (en) | 2011-12-12 | 2013-06-13 | Corinthian Ophthalmic, Inc. | High modulus polymeric ejector mechanism, ejector device, and methods of use |
KR20210026952A (en) | 2019-09-02 | 2021-03-10 | 삼성전자주식회사 | Electronic device with overcurrent protection and method for overcurrent protection |
US11146257B2 (en) * | 2019-12-04 | 2021-10-12 | Denso International America, Inc. | Latching DC switch circuit with overcurrent protection using field effect transistors |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5572395A (en) | 1993-12-21 | 1996-11-05 | International Business Machines Corporation | Circuit for controlling current in an adapter card |
DE69428884T2 (en) * | 1994-03-22 | 2002-06-20 | St Microelectronics Srl | Overload protection circuit for MOS power drivers |
US5910690A (en) | 1997-02-11 | 1999-06-08 | Cabletron Systems, Inc. | Hotswappable chassis and electronic circuit cards |
US6163712A (en) * | 1998-02-04 | 2000-12-19 | Motorola, Inc. | Inrush current limiter with output voltage detection for control of input current level and activation of current bypass path |
JP3784594B2 (en) * | 1999-11-30 | 2006-06-14 | 富士通株式会社 | Current control circuit |
-
2007
- 2007-07-27 US US11/829,112 patent/US7813095B2/en active Active
-
2008
- 2008-07-23 EP EP08796465A patent/EP2174228B1/en not_active Not-in-force
- 2008-07-23 CA CA2693415A patent/CA2693415C/en not_active Expired - Fee Related
- 2008-07-23 AT AT08796465T patent/ATE544117T1/en active
- 2008-07-23 WO PCT/US2008/070843 patent/WO2009018036A1/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
CA2693415A1 (en) | 2009-02-05 |
ATE544117T1 (en) | 2012-02-15 |
CA2693415C (en) | 2013-12-31 |
US20090027818A1 (en) | 2009-01-29 |
EP2174228A1 (en) | 2010-04-14 |
WO2009018036A1 (en) | 2009-02-05 |
US7813095B2 (en) | 2010-10-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR102379554B1 (en) | Protection circuit | |
US9152197B2 (en) | Overcurrent protection circuit and server using the same | |
US20190138071A1 (en) | Hot plug module power supply device, method and system | |
EP2174228B1 (en) | Discrete hot swap and overcurrent-limiting circuit | |
TWI514707B (en) | Over-current protection circuit and electronic device appling the over-current protection circuits | |
US20070283173A1 (en) | System and method of detection of power loss in powered ethernet devices | |
US20110119506A1 (en) | Powered device | |
US20200228001A1 (en) | Systems and methods for distributing power in a power-to-the-edge system architecture | |
US20160156173A1 (en) | CIRCUIT ARCHITECTURES FOR PROTECTING AGAINST PoDL WIRE FAULTS | |
US9954430B2 (en) | Overvoltage and surge protection in a power over ethernet device | |
US8953291B2 (en) | Reversal connection protecting circuit | |
CN111949592B (en) | Hot plug circuit device suitable for LVDS | |
US20120081816A1 (en) | Integrated variable output power supply protection circuit | |
JPH05137278A (en) | Electric power supply system | |
US7656628B2 (en) | Apparatus for providing fault protection in a circuit supplying power to an electronic device | |
US20130134801A1 (en) | Power supply circuit for antenna, antenna control system, and digital communication device | |
US10224706B2 (en) | Fuse box for mitigating arc faults and current surges | |
KR20000001822A (en) | Stabilization circuit for interface apparatus | |
US6014299A (en) | Device and method for protecting a CPU from being damaged by an overrating voltage or overrating current | |
US8373951B2 (en) | Universal serial bus protection circuit | |
US6850396B1 (en) | Fail safe circuit with reset capability for a power supply | |
US20160211887A1 (en) | Network fieldbus power supply | |
AU634632B2 (en) | System for protecting a dc power distribution bus during hot servicing | |
CN109861167A (en) | Interface short circuit protection circuit and set-top box | |
US7079366B1 (en) | Power on sequence and ground fault interruptor for hot plug device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 20091207 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MT NL NO PL PT RO SE SI SK TR |
|
AX | Request for extension of the european patent |
Extension state: AL BA MK RS |
|
17Q | First examination report despatched |
Effective date: 20100706 |
|
DAX | Request for extension of the european patent (deleted) | ||
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
GRAS | Grant fee paid |
Free format text: ORIGINAL CODE: EPIDOSNIGR3 |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: SCIENTIFIC-ATLANTA, LLC |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MT NL NO PL PT RO SE SI SK TR |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D |
|
REG | Reference to a national code |
Ref country code: AT Ref legal event code: REF Ref document number: 544117 Country of ref document: AT Kind code of ref document: T Effective date: 20120215 Ref country code: CH Ref legal event code: EP |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R096 Ref document number: 602008013123 Country of ref document: DE Effective date: 20120405 |
|
REG | Reference to a national code |
Ref country code: NL Ref legal event code: VDEP Effective date: 20120201 |
|
LTIE | Lt: invalidation of european patent or patent extension |
Effective date: 20120201 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: HR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20120201 Ref country code: NL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20120201 Ref country code: NO Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20120501 Ref country code: IS Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20120601 Ref country code: LT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20120201 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20120201 Ref country code: LV Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20120201 Ref country code: PL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20120201 Ref country code: BE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20120201 Ref country code: GR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20120502 Ref country code: PT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20120601 |
|
REG | Reference to a national code |
Ref country code: AT Ref legal event code: MK05 Ref document number: 544117 Country of ref document: AT Kind code of ref document: T Effective date: 20120201 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: CY Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20120201 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: RO Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20120201 Ref country code: SI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20120201 Ref country code: DK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20120201 Ref country code: EE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20120201 Ref country code: SE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20120201 Ref country code: CZ Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20120201 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20120201 Ref country code: SK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20120201 |
|
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
26N | No opposition filed |
Effective date: 20121105 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: AT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20120201 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: MC Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20120731 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R097 Ref document number: 602008013123 Country of ref document: DE Effective date: 20121105 Ref country code: CH Ref legal event code: PL |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: ES Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20120512 Ref country code: CH Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20120731 Ref country code: LI Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20120731 |
|
REG | Reference to a national code |
Ref country code: IE Ref legal event code: MM4A |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20120723 Ref country code: MT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20120201 Ref country code: BG Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20120501 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: TR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20120201 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: LU Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20120723 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: HU Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20080723 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 8 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 9 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 10 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R082 Ref document number: 602008013123 Country of ref document: DE Representative=s name: BOSCH JEHLE PATENTANWALTSGESELLSCHAFT MBH, DE Ref country code: DE Ref legal event code: R081 Ref document number: 602008013123 Country of ref document: DE Owner name: CISCO TECHNOLOGY, INC., SAN JOSE, US Free format text: FORMER OWNER: SCIENTIFIC-ATLANTA, LLC, LAWRENCEVILLE, GA., US |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: 732E Free format text: REGISTERED BETWEEN 20180621 AND 20180627 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 11 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 20200728 Year of fee payment: 13 Ref country code: GB Payment date: 20200727 Year of fee payment: 13 Ref country code: DE Payment date: 20200729 Year of fee payment: 13 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R119 Ref document number: 602008013123 Country of ref document: DE |
|
GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20210723 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20210723 Ref country code: DE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20220201 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20210731 |
|
P01 | Opt-out of the competence of the unified patent court (upc) registered |
Effective date: 20230525 |