EP2171960A1

EP2171960A1 - Apparatus and method for hierarchical modulation and apparatus and method for hierarchical demodulation

Info

Publication number: EP2171960A1
Application number: EP08741574A
Authority: EP
Inventors: Hyoung Soo Lim; Sung-Hoon Kim; Heung Mook Kim; Jong Soo Lim; Soo In Lee
Original assignee: Electronics and Telecommunications Research Institute ETRI
Current assignee: Electronics and Telecommunications Research Institute ETRI
Priority date: 2007-06-29
Filing date: 2008-04-28
Publication date: 2010-04-07
Also published as: WO2009005216A1; CN101796791A; CN101796791B; KR100874016B1

Abstract

An apparatus for hierarchical modulation generates a first hierarchical symbol sequence by mapping a first hierarchical bit sequence corresponding to an information bit sequence into a bit position in a first signal constellation according to a first modulation method. Further, the apparatus for hierarchical modulation generates a second hierarchical symbol sequence by mapping a second hierarchical bit sequence corresponding to an additional information bit sequence into a bit position in a second signal constellation according to a second modulation method and then phase-rotating the second hierarchical bit sequence as much as the phase of each first hierarchical symbol. The apparatus for hierarchical modulation generates a hierarchical modulating symbol sequence by adding up symbols in the generated second hierarchical symbol sequence and symbols in the first hierarchical symbol sequence.

Description

APPARATUS AND METHOD FOR HIERARCHICAL MODULATION AND APPARATUS AND METHOD FOR HIERARCHICAL DEMODULATION

Technical Field

[1] The present invention relates to an apparatus and a method for hierarchical modulation, and an apparatus and a method for hierarchical demodulation. More particularly, the present invention relates to a bit mapping technology in a signal constellation based on the modulation method.

[2] This work was supported by the IT R&D program of MIC/IITA [2006-S-016-02, Development of Distributed Translator Technology for Terrestrial DTV]. Background Art

[3] Each of the mass media has provided a variety of broadcasting services with the advent of digital broadcasting. Since OFDM (orthogonal frequency division multiplexing), a modulation method used in terrestrial digital broadcasting, has high spectrum efficiency and strength in a fading channel, it is mainly used for communication, such as high-speed wire/wireless communication.

[4] Currently, a digital broadcasting system uses a hierarchical modulation method in which the modulation method is determined according to priority relating to characteristics of transmission information. In the hierarchical modulation method used in the OFDM digital broadcasting system, high-priority (HP) data streams and low-priority (LP) data streams are individually modulated and one transmission stream is generated by superimposing the LP signal of lower power to the HP signal of high power. Using the hierarchical modulation method as described above, it is possible to generate different data streams from one channel and receive the data streams from different receiving apparatuses.

[5] The receiving apparatus determines an HP stream on the basis of the hierarchical- modulated transmission stream, estimates and compensates channel distortion on the basis of the decision, and then demodulates an LP stream in the same phase from the transmission stream with the channel distortion compensated. However, when the receiving apparatus incorrectly determines the HP stream, an error is caused in estimating of channel distortion, and the error in estimating of the channel distortion deteriorates receiving performance. Further, since the receiving apparatus performs decision -based channel estimation, the configuration of hardware becomes complicated.

[6] The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art. Disclosure of Invention

Technical Problem

[7] The present invention has been made in an effort to provide an apparatus and a method for hierarchical modulation, and an apparatus and a method for hierarchical demodulation, having advantages of minimizing the degradation of receiving performance due to incorrect decision and simplifying the configuration of the hardware of a receiving apparatus. Technical Solution

[8] A method for hierarchical modulation according to an exemplary embodiment of the present invention includes: generating a first hierarchical symbol sequence by mapping a first hierarchical bit sequence into the bit position in a first signal constellation according to a first modulation method; generating a second hierarchical symbol sequence by mapping a second hierarchical bit sequence into the bit position in a second signal constellation according to a second modulation method; rotating phases of the symbols in the second hierarchical symbol sequence; and generating a hierarchical modulation symbol sequence from the first hierarchical symbol sequence and the phase-rotated second hierarchical symbol sequence.

[9] An apparatus for hierarchical modulation according to another exemplary embodiment of the present invention, includes: a first modulator that generates a first hierarchical symbol sequence by mapping a first hierarchical bit sequence into a plurality of first hierarchical symbols in a first signal constellation; a second modulator that rotates phases of a plurality of second symbols in a second signal constellation, where a second hierarchical bit sequence is mapped, according to the phases of the first hierarchical symbols, and generates a second hierarchical symbol sequence by mapping the second hierarchical bit sequence into the phase-rotated second hierarchical symbols; and a hierarchical modulator that generates a hierarchical modulation symbol sequence by combining the second hierarchical symbols in the second hierarchical symbol sequence with the first hierarchical symbols in the first hierarchical symbol sequence.

[10] According to another exemplary embodiment of the present invention, an apparatus for hierarchical demodulation of a hierarchical modulation symbol sequence transmitted from an apparatus for hierarchical modulation is provided. The apparatus for hierarchical demodulation includes: a first demodulator that demodulates the first hierarchical bit sequence from the hierarchical modulation symbol sequence; a channel estimator that extracts pilot symbols from the hierarchical modulated symbol sequence, estimates channel coefficients from the extracted pilot symbols, and then interpolates the channel coefficients from the pilot symbols; a channel equalizer that equalizes each symbol in the hierarchical modulation symbol sequence using the interpolated channel coefficients; and a second demodulator that demodulates the second hierarchical bit sequence from the equalized hierarchical modulation symbol sequence.

[11] According to another exemplary embodiment of the present invention, a method for hierarchical demodulation of a hierarchical modulation symbol sequence transmitted from an apparatus for hierarchical modulation is provided. The method includes: demodulating a first hierarchical bit sequence from the hierarchical modulation symbol sequence; extracting pilot symbols from the hierarchical modulation symbol sequence; interpolating the channel coefficients of the pilot symbols by estimating channel coefficients from the extracted pilot symbols; compensating channel distortion of each symbol in the hierarchical modulation symbol sequence using the interpolated channel coefficients; and demodulating the second hierarchical bit sequence from the hierarchical modulation symbol sequence with the channel distortion compensated.

Advantageous Effects

[12] According to an exemplary embodiment of the present invention, it is possible to minimize a decrease in receiving performance due to incurred decision of a first hierarchical bit sequence in a receiving apparatus. Brief Description of the Drawings

[13] FIG. 1 is a schematic block diagram showing an apparatus for hierarchical modulation according to a first exemplary embodiment of the present invention,

[14] FIG. 2 is a flow chart illustrating the operation of the apparatus for hierarchical modulation according to the first exemplary embodiment of the present invention,

[15] FIG. 3 and FIG. 4 are diagrams showing odd- numbered and even-numbered symbols in π/4 -DQPSK signal constellations, respectively,

[16] FIG. 5 is a diagram showing a QPSK signal constellation,

[17] FIG. 6 and FIG. 7 are diagrams showing signal constellations of odd-numbered and even-numbered hierarchical modulation symbols with QPSK symbols in a π/4 DQPSK according to an exemplary embodiment of the invention, respectively,

[18] FIG. 8 and FIG. 9 are exemplary diagrams illustrating the arrangement of pilot symbols, respectively,

[19] FIG. 10 is a flow chart illustrating the operation of a second modulator according to a second exemplary embodiment of the present invention,

[20] FIG. 11 and FIG. 12 are exemplary diagrams each showing a signal constellation of odd-numbered and even-numbered hierarchical modulation symbols of the π/4 DQPSK with QPSK symbols, [21] FIG. 13 is an exemplary diagram illustrating bit mapping of a second hierarchical bit sequence due to a decision error,

[22] FIG. 14 is a schematic block diagram of an apparatus for hierarchical demodulation according to an exemplary embodiment of the present invention, and

[23] FIG. 15 is a flow chart illustrating the operation of an apparatus for hierarchical demodulation according to an exemplary embodiment of the present invention. Mode for the Invention

[24] In the following detailed description, only certain exemplary embodiments of the present invention have been shown and described, simply by way of illustration. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification.

[25] It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. In addition, the terms -er, -or, module, and block described in the specification mean units for processing at least one function and operation, and can be implemented by hardware components or software components, and combinations thereof.

[26] An apparatus and a method for hierarchical modulation according to an exemplary embodiment of the present invention are described hereafter in detail with reference to the accompanying drawings.

[27] FIG. 1 is a schematic block diagram of an apparatus for hierarchical modulation according to an exemplary embodiment of the present invention.

[28] As shown in FIG. 1, an apparatus for hierarchical modulation 100 includes a first modulator 110, a second modulator 120, a pilot inserting block 130, and a hierarchical modulator 140.

[29] The first modulator 110 generates a first hierarchical symbol sequence by mapping a first hierarchical bit sequence corresponding to an information bit sequence, which is an HP stream, into a bit position in a signal constellation according to predetermined modulation, and outputs the generated first hierarchical symbol sequence.

[30] The second modulator 120 generates a second hierarchical symbol sequence by mapping a second hierarchical bit sequence corresponding to an additional bit sequence, which is an LP stream, into a bit position in a signal constellation according to predetermined modulation, rotates each of the generated symbols in the second hierarchical symbol sequence by phases corresponding to the symbols in the first hierarchical symbol sequence, and then outputs them. Alternatively, the second modulator 120 rotates the bit positions of symbols in a signal constellation according to predetermined modulation, by which the bits of the second hierarchical bit sequence corresponding to the additional bit sequence are modulated, by the phases of corresponding first hierarchical symbols, generates a second hierarchical symbol sequence by mapping the bits of the second hierarchical bit sequence into the bit positions with the phases rotated in a signal constellation according to predetermined modulation, and then outputs the generated second hierarchical symbol sequence. The first modulator 110 uses π/4 -DQPSK (π/4 -differential quadrature phase shift keying) modulation and the second modulator 120 uses QPSK (quadrature phase shift keying) or π/4 -DQPSK modulation. Further, the second modulator 120 may use any one of 2- ASK (2-amplitude shift keying) and 4- ASK modulation, and 16-QAM (16-quadrature amplifier modulation), and may use various modulation methods according to propagation environments and data speed.

[31] The pilot inserting block 130 inserts pilot symbols into the second hierarchical symbol sequence outputted from the second modulator 120 at a predetermined interval and outputs them.

[32] The hierarchical modulator 140 generates a hierarchical modulation symbol sequence by adding the symbols in the first hierarchical symbol sequence outputted from the first modulator 110 and the symbols in the second hierarchical symbol sequence having the pilot symbols outputted from the pilot inserting block.

[33] Further, the apparatus for hierarchical modulation 100 may further include a channel encoding block (not shown) that encodes channels of the first and second hierarchical bit sequences and outputs them to the first and second modulators 110 and 120. The channel encoding method includes convolution encoding, lattice encoding, turbo encoding, LDPC (low density parity check) encoding, or concatenated encoding of two thereof. Further, the apparatus for hierarchical modulation 100 may include an in- terleaver block (not shown). The interleaver block (not shown) interleaves the first hierarchical symbol sequence and the second hierarchical symbol sequence respectively. The interleaver block (not shown) outputs the interleaved second hierarchical symbol sequence to the pilot inserting block 130.

[34] Further, the apparatus for hierarchical modulation 100 according to an exemplary embodiment of the present invention may be applied to digital audio broadcasting or a multi-carrier signal transmission system, such as a terrestrial digital multimedia broadcasting system. For example, a transmitting device of an OFDM (orthogonal frequency division multiplexing) transmission system sequentially maps the hier- archical modulation symbol sequence generated from the apparatus for hierarchical modulation 100 into a plurality of subcarriers, applies OFDM modulation through an OFDM modulation block including an IFFT (inverse fast Fourier transform) block, and then outputs the OFDM symbol sequence to an RF terminal. When the apparatus for hierarchical modulation 100 is not provided with the interleaver block, the transmitting apparatus of the OFDM transmission system may further include an interleaver block. The interleaver block interleaves the hierarchical modulation symbol sequence generated from the apparatus for hierarchical modulation 100 and then outputs them to the IFFT block.

[35] Subsequently, a method of generating a hierarchical modulation symbol sequence in the apparatus for hierarchical modulation 100 according to an exemplary embodiment of the present invention will be described.

[36] FIG. 2 is a flow chart illustrating the operation of an apparatus for hierarchical modulation according to an exemplary embodiment of the present invention, and FIG. 3 and FIG. 4 are diagrams showing odd-numbered and even-numbered symbols in a transmission frame in a π/4 -DQPSK signal constellation, respectively. FIG. 5 is a diagram showing a QPSK signal constellation. FIG. 6 and FIG. 7 are diagrams showing signal constellations of odd-numbered and even-numbered hierarchical modulation symbols with QPSK symbols in a π/4 DQPSK according to an exemplary embodiment of the invention, respectively. FIG. 8 and FIG. 9 are exemplary diagrams illustrating arrangements of pilot symbols. Hereinafter, it is assumed that the apparatus for hierarchical modulation 100 applied to an OFDM system modulates the first hierarchical bit sequence using π/4 -DQPSK modulation and the second hierarchical bit sequence using QPSK modulation.

[37] As shown in FIG. 2, a first modulator 110 generates a first hierarchical symbol sequence by mapping a first hierarchical bit sequence into a π/4 -DQPSK symbol at a constellation dot of a complex number and then outputs the generated first hierarchical symbol sequence (S210). In this process, the first modulator 110 maps the bits of the first hierarchical bit sequence into aπ/4 -DQPSK symbol. In this case, twos are modulated from an uppermost bit. The signal constellation shown in FIG. 3 and 3B may be used for π/4 -DQPSK modulation. The signal constellation shown in FIG. 3 illustrates subcarrier signals of odd-numbered OFDM symbols from a PRS (phase reference symbol) and the signal constellation shown in FIG. 4 illustrates subcarrier signals of even-numbered OFDM symbols from the PRS, of which the phases are rotated by π/4 from the signal constellation shown in FIG. 3.

[38] The second modulator 120 generates a second hierarchical symbol sequence by mapping the second hierarchical bit sequence into the QPSK symbol at a constellation dot of a complex number and then outputs the generated second hierarchical symbol sequence (S220). Further, the second modulator 120 maps the bits in the second hierarchical bit sequence into a QPSK symbol. In this case, twos are modulated from an uppermost bit. The signal constellation shown in FIG. 5 may be used for QPSK modulation. Subsequently, the second modulator 120 rotates each symbol in the second hierarchical symbol sequence by the phases of the first hierarchical symbol (S230). That is, the bits in the QPSK signal constellation shown in FIG. 5 rotate by the phase of the first hierarchical symbol.

[39] The pilot inserting block 130 generates pilot symbols from the first hierarchical bit sequence and then inserts the generated pilot symbols into the modulated second hierarchical symbol sequence (S240). In this process, as shown in FIG. 8, the pilot inserting block 130 may insert one pilot symbol for every ten subcarrier signals in the frequency direction and for every three OFDM symbols in the time direction at the same position as in the subcarrier signals, and, as shown in FIG. 9, may insert a pilot symbol for each OFDM symbol at the same subcarrier signal position to provide division in the frequency direction and continuity in the time direction. The pilot symbols, which are generated by modulating random rather than predetermined data between the apparatus for hierarchical modulation 100 and an apparatus for hierarchical demodulation (200 in FIG. 14), are the signals having correlation with the first hierarchical symbols corresponding to the same subcarrier signals or the same hierarchical modulation symbols, and may be generated by power-boosting the first hierarchical symbols. The number of signal constellations of the pilot symbol is the same as the number of signal constellations of the first hierarchical symbol, that is, odd- numbered symbols or even-numbered symbols in the pilot symbol have four signal constellations, respectively.

[40] Subsequently, a hierarchical modulator 140 generates a hierarchical modulation symbol sequence by adding up the second hierarchical symbol sequence including the pilot symbols and the first hierarchical symbol sequence, and then outputs the hierarchical modulation symbol sequence (S250-S260). For example, the signal constellation of hierarchical modulation symbols shown in FIG. 6 and FIG. 7 can be obtained by rotating the QPSK signal constellation shown in FIG. 5 by the phase of the first hierarchical symbol. That is, when the first hierarchical symbol is the constellation dot represented by x in the second quadrant in FIG. 3, the second hierarchical bit sequence is mapped into the QPSK symbol of the signal constellation shown in FIG. 5 and the signal constellation of FIG. 5 is rotated counterclockwise by 135°. According to the above process, the four constellation dots represented by o in the second quadrant in FIG. 6 and bit mapping for each of the constellation dots can be obtained. Further, the hierarchical modulation symbol sequence according to FIG. 6 and FIG. 7 is transmitted to the receiving apparatus. [41] On the other hand, the second modulator 120 may generate a second hierarchical symbol sequence according to a method other than that of the first exemplary embodiment of the present invention. This exemplary embodiment will be described with reference to FIG. 10.

[42] FIG. 10 is a flow chart illustrating the operation of a second modulator according to a second exemplary embodiment of the present invention.

[43] As shown in FIG. 10, the second modulator 120 rotates the bit positions of QPSK symbols in a QPSK signal constellation where a second hierarchical bit sequence is mapped, by the phases of the corresponding symbols in a first hierarchical symbol sequence (S810). Thereafter, the second modulator 120 may generate a second hierarchical symbol sequence by mapping the bits in the second hierarchical bit sequence into the QPSK symbols at the bit positions that are phase-rotated (S820-S830). The steps (S810-S830) shown in FIG. 10 correspond to the steps (S220-S230) shown in FIG. 2.

[44] Further, when receiving the hierarchical modulation symbol sequence, a hierarchical demodulating device of the receiving apparatus estimates pilot symbols, determines a first hierarchical bit sequence from the estimated pilot symbols, and then performs decision-based channel estimation in which channel distortion is compensated on the basis of the determined hierarchical bit sequence.

[45] In general, the signal constellation of odd-numbered and even-numbered hierarchical modulation symbols of a π/4 DQPSK with QPSK is shown in FIG. 11 and FIG. 12.

[46] FIG. 11 and FIG. 12 are exemplary diagrams each showing a signal constellation of odd-numbered and even-numbered hierarchical modulation symbols of the π/4 DQPSK with QPSK symbols, and FIG. 13 is an exemplary diagram illustrating bit mapping of a second hierarchical bit sequence due to a decision error.

[47] As shown in FIG. 11 and FIG. 12, the signal constellation of the π/4 DQPSK with

QPSK symbols are set such that only 1 bit is different between adjacent symbols in the first quadrant, such as gray mapping, and modulation symbols in the first quadrant are symmetrically arranged about axes in the other quadrants.

[48] Assuming that the constellation dots of the first hierarchical bit sequence that is substantially transmitted is the x in the first quadrant in the signal constellation shown in FIG. 3, when the apparatus for hierarchical demodulation incorrectly determines that the x in the second quadrant is received, the apparatus for hierarchical demodulation recognizes that additional phase distortion of 90° is generated to the phases distortion of the substantial channel, such that it performs channel equalization on the basis of the incorrectly estimated channel distortion. Accordingly, as shown in FIG. 13, bit mapping of a distorted signal constellation that is different from FIG. 11 is obtained, which deteriorates the receiving performance. [49] However, according to an exemplary embodiment of the present invention, since the second hierarchical symbol is rotated by the phase of the first hierarchical symbol, even though the apparatus for hierarchical demodulation recognizes that phase distortion of an integer times 90° is added to the phase distortion of the substantial channel, the apparatus for hierarchical demodulation can obtain the same bit mapping as in FIG. 6.

[50] Therefore, the apparatus for hierarchical demodulation according to an exemplary embodiment of the invention may perform channel estimation, assuming that a certain symbol is transmitted, without symbol decision.

[51] Further, according to an exemplary embodiment of the present invention, the apparatus for hierarchical demodulation as described above does not need to perform symbol decision, such that channel equalization for symbol decision is also not needed. The apparatus for hierarchical demodulation is described hereafter with reference to FIG. 14 and FIG. 15.

[52] FIG. 14 is a schematic block diagram of an apparatus for hierarchical demodulation according to an exemplary embodiment of the present invention, and FIG. 15 is a flow chart illustrating the operation of an apparatus for hierarchical demodulation according to an exemplary embodiment of the present invention. As shown in FIG. 14, an apparatus for hierarchical demodulation 200 includes a channel estimator 210, a channel equalizer 220, a first hierarchical demodulator 230, and a second hierarchical demodulator 240.

[53] The channel estimator 210 estimates a pilot symbol from a received signal, and estimates distortion of the received signal by estimating a channel coefficient from the estimated pilot symbol. The channel estimator 210 includes a pilot extractor 212, a channel coefficient estimator 214, and an interpolator 216. The pilot extractor 212 extracts the pilot symbol from the received signal (S 1210), and the channel coefficient estimator 214 estimates a channel coefficient for the extracted pilot symbol (S 1220). The interpolator 216 interpolates a channel coefficient on the basis of the estimated channel coefficient for the pilot symbol (S 1230).

[54] The channel equalizer 220 compensates channel distortion of the received signal on the basis of the interpolated channel coefficient (S 1240).

[55] The first hierarchical demodulator 230 demodulates the received signal, that is, a first hierarchical bit sequence from a hierarchical modulation symbol sequence (S 1250). The second hierarchical demodulator 240 demodulates a second hierarchical bit sequence in the same phase from the received signal with the channel distortion compensated (S 1250).

[56] As described above, the apparatus for hierarchical demodulation 200 according to an exemplary embodiment of the present invention does not perform symbol decision and channel equalization for the symbol decision, such that the configuration of the hardware of the apparatus for hierarchical demodulation 200 is not complicated.

[57] Further, in the apparatus for hierarchical modulation (100 in FIG. 1), when the first and second hierarchical bit sequences pass through the channel encoding block (not shown), the apparatus for hierarchical demodulation 200 according to an exemplary embodiment of the present invention may further include a channel decoding block (not shown). The channel decoding block (not shown) applies channel decoding to the first and second hierarchical bit sequences at the outputs of the first hierarchical demodulator 230 and the second hierarchical demodulator 240, respectively. The channel decoding method follows the channel encoding method used in the channel encoding block.

[58] Further, in the apparatus for hierarchical modulation (100 in FIG. 1), when the first and second hierarchical symbol sequences pass through the interleaver block, the apparatus for hierarchical demodulation 200 may further include a deinterleaver block (not shown). The deinterleaver block (not shown) deinterleaves the hierarchical modulation symbol sequence and the channel equalizer then outputs the deinterleaved hierarchical modulation symbol sequence and the interpolated channel coefficients to the first hierarchical demodulator 230 and the second hierarchical demodulator 240, respectively..

[59] Further, when the apparatus for hierarchical modulation (100 in FIG. 1) is applied to an OFDM transmission system, the received signal may be an OFDM symbol sequence, and the receiving apparatus of the OFDM transmission system outputs OFDM signals demodulated from the transmitted OFDM symbol sequence through the OFDM demodulation block including the FFT (fast Fourier transform) block to the apparatus for hierarchical demodulation 200. When the apparatus for hierarchical demodulation 200 is not provided with the deinterleaver block, the receiving apparatus of the OFDM transmission system may further include the deinterleaver block. The deinterleaver block deinterleaves the received OFDM symbol sequence and then outputs it to the OFDM demodulation block.

[60] The embodiment of the present invention described above is not implemented by only the method and apparatus, but it may be implemented by a program for executing the functions corresponding to the configuration of the exemplary embodiment of the present invention or a recording medium having the program recorded thereon. These implementations can be realized by the ordinary skilled person in the art from the description of the above-described exemplary embodiment.

[61] While this invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

[1] A method for hierarchical modulation, comprising: generating a first hierarchical symbol sequence by mapping a first hierarchical bit sequence into a bit position of a first signal constellation according to a first modulation method; generating a second hierarchical symbol sequence by mapping s second hierarchical bit sequence into a bit position in a second signal constellation according to a second modulation method; rotating phases of the symbols in the second hierarchical symbol sequence; and generating a hierarchical modulation symbol sequence from the first hierarchical symbol sequence and the phase-rotated second hierarchical symbol sequence. The method of claim 1, wherein phases of the symbols in the second hierarchical symbol sequence are rotated by the phases of corresponding symbols in the first hierarchical symbol sequence.

[2] The method of claim 1, wherein phases of the symbols in the second hierarchical symbol sequence are rotated by the phases of corresponding symbols in the first hierarchical symbol sequence.

[3] The method of claim 2, further comprising: inserting pilot symbols into the phase-rotated second hierarchical symbol sequence before the generating of the hierarchical modulation symbol sequence.

[4] The method of claim 3, wherein the pilot symbols are generated by amplifying corresponding symbols in the first hierarchical symbol sequence.

[5] An apparatus for hierarchical modulation, comprising: a first modulator that generates a first hierarchical symbol sequence by mapping a first hierarchical bit sequence into a plurality of first hierarchical symbols in a first signal constellation; a second modulator that rotates phases of a plurality of second symbols in a second signal constellation, where a second hierarchical bit sequence is mapped, according to the phases of the first hierarchical symbols, and generates a second hierarchical symbol sequence by mapping the second hierarchical bit sequence into the phase-rotated second hierarchical symbols; and a hierarchical modulator that generates a hierarchical modulation symbol sequence by combining the second hierarchical symbols in the second hierarchical symbol sequence with the first hierarchical symbols in the first hierarchical symbol sequence.

[6] The apparatus of claim 5, further comprising a pilot inserting block that inserts pilot symbols into the second symbol sequence and then outputs inserted pilot symbols to the hierarchical modulator, wherein at least one hierarchical modulation symbol in the hierarchical modulation symbol sequence is generated by combination of the first symbol and the pilot symbol.

[7] The apparatus of claim 6, wherein the hierarchical modulation symbol is mapped into a plurality of subcarrier signals and then transmitted to a receiving apparatus, and the pilot symbol has a relationship to a first hierarchical symbol that is mapped into the same subcarrier signals.

[8] The apparatus of claim 6, wherein the first symbol is a π/4DQPSK (differential quadrature phase shift keying) symbol, the second symbol is one of a QPSK (quadrature phase shift keying) symbol, a 2- ASK (2-amplitude shift keying) symbol, a 4- ASK symbol, or a 16-QAM (16-quadrature amplifier modulation).

[9] A method for hierarchical demodulation of a hierarchical modulation symbol sequence transmitted from an apparatus for hierarchical modulation, comprising: demodulating a first hierarchical bit sequence from the hierarchical modulation symbol sequence; extracting pilot symbols from the hierarchical modulation symbol sequence; interpolating the channel coefficients of the pilot symbols by estimating channel coefficients from the extracted pilot symbols; compensating channel distortion of each symbol in the hierarchical modulation symbol sequence using the interpolated channel coefficients; and demodulating the second hierarchical bit sequence from the hierarchical modulation symbol sequence with the channel distortion compensated.

[10] The method of claim 9, wherein each hierarchical modulation symbol in the hierarchical modulation symbol sequence includes one symbol from among a plurality of first symbols corresponding to the first hierarchical bit sequence and one symbol from among a plurality of second symbols corresponding to the second hierarchical bit sequence, and the bit position of each of the second symbols is determined by phase rotation of the bit position of a signal constellation for the modulation method of the second hierarchical bit sequence according to the phase of each of the first symbols.

[11] The method of claim 10, wherein at least one of the second symbols is the pilot symbol.

[12] The method of claim 11, wherein the pilot symbol is generated by amplifying the size of the first symbol included in the same hierarchical modulation symbol.

[13] An apparatus for hierarchical demodulation of a hierarchical modulation symbol sequence transmitted from an apparatus for hierarchical modulation, comprising: a first demodulator that demodulates a first hierarchical bit sequence from the hierarchical modulation symbol sequence; a channel estimator that extracts pilot symbols from the hierarchical modulated symbol sequence, estimates channel coefficients from the extracted pilot symbols, and then interpolates the channel coefficients from the pilot symbols; a channel equalizer that equalizes each symbol in the hierarchical modulation symbol sequence using the interpolated channel coefficients; and a second demodulator that demodulates a second hierarchical bit sequence from the equalized hierarchical modulation symbol sequence.

[14] The apparatus of claim 13, wherein the hierarchical modulation symbols in the hierarchical modulation symbol sequence include a plurality of first symbols corresponding to the first hierarchical bit sequence and a plurality of second symbols corresponding to the second hierarchical bit sequence, and each of the second symbols has a bit position that is determined by phase- rotating the bit position of a signal constellation, in which the second hierarchical bit sequence exists, according to the phase of each first symbol included in the same hierarchical modulation symbol.

[15] The apparatus of claim 14, wherein at least one of the second symbols is the pilot symbol.