EP2137914A1

EP2137914A1 - Lin receiver

Info

Publication number: EP2137914A1
Application number: EP08749061A
Authority: EP
Inventors: Wolfgang Horn
Original assignee: TDK Micronas GmbH
Current assignee: TDK Micronas GmbH
Priority date: 2007-04-23
Filing date: 2008-04-23
Publication date: 2009-12-30
Anticipated expiration: 2028-04-23
Also published as: DE102007019356A1; JP2010525701A; US20100231288A1; US8362810B2; EP2137914B1; WO2008128763A1; JP5449135B2

Abstract

The invention relates to a LIN receiver providing sleep/wake up functionality and comprising an input (LINI) to a LIN bus (LIN), an output (RXDO), connections for at least one supply voltage (BVDD) and transistors (M1-M17). The transistors (M1-M17) are connected to activate the receiver in the recessive state of the LIN bus by switching the state at the LIN bus into an active state of the receiver. In particular, the input (LINI) is connected between components of a voltage-to-current converter (SSW), in particular between a first and a second resistance (R1, R2).

Description

description

LIN Receiver

The invention relates to a LIN receiver with sleep / wake-up functionality according to the preamble features according to claim 1.

LIN receivers (LIN: Local Interconnect Network) are designed to detect a level on a LIN bus. According to the LIN specification 2.1, page 115, voltage dividers with different division ratios on the LIN bus and on the supply, in particular a battery, are used to evaluate a LIN level on the bus. Fig. 6 shows an exemplary arrangement according to the current state of the art. Between a ground voltage GND and a connection or input LINI to the LIN bus, a voltage divider chain of two resistors is connected. Another voltage divider chain also consisting of two resistors is connected between ground GND and a positive supply voltage of the bus BVDD. The connection for the ground GND can also be connected as negative supply voltage of the bus. Contact points between the two respective resistors of the two voltage divider chains lead to a positive or a negative input of an operational amplifier with an output RXDO [Ai], to which data, in particular receive data RXD are applied in a manner known per se.

A disadvantage of such a solution is the permanent power consumption of the divider chains and the required chip area for the implementation of high-ohmic resistors. This requires a balance between power consumption and chip area. To realize a sleep function (sleep function), the divider chains can be switched off. However, this has the consequence that the level on the LIN bus can no longer be evaluated correctly and a wake function (wake-up function) via the LIN bus is no longer possible. Accordingly, currently available LIN receivers and LIN transceivers with integrated receiver function have a relatively high power consumption in sleep mode.

The object of the invention is to propose a circuit arrangement or a LIN receiver with a corresponding circuit arrangement, which allow a reduction in power consumption in sleep mode.

This object is achieved by a LIN receiver with sleep / wake-up functionality with the features according to claim 1. Advantageous embodiments are the subject of dependent claims.

Accordingly, in particular a LIN receiver with sleep / wake-up functionality is preferred, which has an input to a LIN bus, an output and connections for at least one supply voltage, wherein the LIN receiver additionally has transistors which are connected to activate of the receiver in the recessive state of the LIN bus by a state change on the LIN bus in an active state of the receiver.

In this case, a LIN receiver does not necessarily have to be understood as an independent component. Also, corresponding circuit arrangements, in particular circuit arrangements in higher-level devices with such a LIN receiver functionality are included. This is especially true for LIN transceivers, which in addition to a receiver functionality additionally also have a transmit functionality. In particular, such a preferred LIN receiver is characterized by a very low power consumption in the recessive state of the LIN bus, that is, in the sleep function from. Nevertheless, the receiver can be automatically activated by a state change on the LIN bus to the active or dominant state, which provides a wake-up functionality. During waking or activating or afterwards, the LIN receiver can then generate a signal with which z. B. via an interrupt a processor can be activated.

This results in a variety of advantages. Excluding leakage currents eliminates a power consumption in sleep mode. Depending on the embodiment, no high-ohmic voltage dividers are required. Even in active operation, only a low power consumption is required. In particular, an automatic activation of the circuit during activity on the LIN bus is made possible, so that a separate wake-up signal is not required. The hysteresis is advantageously proportional to the supply voltage.

In particular, such a LIN receiver is preferred in which the input is connected between components of a voltage-to-current converter, in particular between a first and a second resistor.

In particular, a first resistor of the voltage-to-current converter is connected and dimensioned in such a way as a pull-up resistor, that at a dominant level at the input current flows through the first resistor. At least a first, second and third of the transistors are preferably connected to mirror the flow of current through the first resistor, and at least one eighth and one fourteenth transistor and further twelfth, thirteenth and second transistors connected as cascode transistors Fifteenth transistors are preferably connected for activating the LIN receiver and / or the output [A2].

In the case of the LIN receiver, a second resistor of the voltage-to-current converter is advantageously connected by means of transistors to a negative supply voltage or ground.

At least a third and a fifteenth transistor may be connected between a positive supply voltage and the negative supply voltage or ground for comparing a current flow component through the first resistor and a current flow component through the second resistor.

A tenth and an eleventh transistor may be connected on the output side to the third and the fifteenth transistor to pull the output to ground or the negative supply voltage of the bus.

In particular, at least a fourth, a fifth and a seventh transistor may be connected between the positive supply voltage and the negative supply voltage or ground in such a way that a current flow component through the second resistor of the voltage-to-current converter the gate of the seventh transistor and over the fourth and the fifth transistor drives to compensate for the current share through the second resistor. By the fourth and fifth of the transistors while the current is mirrored to the input. From the LIN bus, the second resistor becomes invisible.

In addition, at least one eighth and one fourteenth transistor may be connected between the positive supply voltage and the negative supply voltage or ground, that they switch off a current flow through the second resistance at the recessive level at the input by means of a switch. The switching off can be effected by, for example, a twelfth transistor controlled by these transistors, which is connected between the second resistor and the negative supply voltage or ground. Ultimately, the entire circuit is thereby de-energized. This results in a possibly low current consumption, which is limited in the recessive state both on the LIN bus and the supply connection to leakage currents.

A switch and a seventeenth transistor for hysteresis may be connected as additional components in series between the second resistor and the negative supply voltage or ground, which switch is then switched, depending on a circuit state at the output, a current flow through the seventeenth transistor. or turn off. By such a circuit arrangement results in a hysteresis whose value is not constant, but proportional to the supply voltage. This behavior is advantageous because the definition of hysteresis in the LIN specification refers to the supply voltage.

The transistors may generally be dimensioned by means of scaling factors to correspondingly reduce all currents except that by a first resistor of the voltage-to-current converter which can be switched to the positive supply voltage. High scaling factors are also possible because the speed requirements of such LIN receivers are low if the maximum frequency of the LIN bus is in particular fmax (LIN) = 2OkHz. A sixteenth transistor can be connected as an integrated reverse protection diode between a positive supply voltage and the other transistors. By a corresponding interconnection of the gate of the sixteenth transistor is this at normal polarized supply voltage of the bus in the Rdson operation, whereby a voltage drop can be neglected with appropriate dimensioning.

As far as the named transistors are numbered, it is merely a characteristic of this distinguishing the individual of the transistors and not a numbering in the sense of a numerical listing.

According to particularly emphasized aspects disadvantages are thus eliminated depending on the embodiment of the embodiments by the elimination of the divider chain to the supply or supply voltage by using the prescribed according to the LIN specification pull-up resistor for signal evaluation. In addition, deactivation of the entire circuit in a recessive state on the LIN bus can take place. In the non-recessive state on the LIN bus, an automatic activation can take place.

An embodiment will be described below with reference to various embodiments. The same reference numerals in the various figures refer to the same or equivalent components and functions, so that reference is made in particular in the extended embodiments with respect to such same reference numerals to the statements of the other and in particular each preceding figures. In general, it is true that components of the further embodiments of course also without interposed described embodiments. tion forms can be directly combined with the first embodiment. Show it:

1 shows a circuit arrangement of a first preferred LIN receiver,

2 shows a second circuit arrangement of a contrast modified LIN receiver,

3 shows a comparison with FIG. 2 further modified embodiment of a LIN receiver,

4 shows a still further modified embodiment of such a LIN receiver,

FIG. 5 shows a further embodiment of such a LIN receiver modified relative to FIG. 1, and FIG

Fig. 6 shows an exemplary arrangement according to the prior art.

Fig. 1 shows an exemplary circuit arrangement with an input LINI as a connection point for a LIN bus LIN, an output RXDO, on which receive data RXD can be tapped, a positive supply voltage of the bus BVDD and a negative supply voltage of the bus BVSS. In a manner known per se, the ratio of the negative and the positive supply voltages of the bus BVSS, BVDD is relevant to their reIative ratio. In particular, the negative supply voltage can optionally also correspond to ground or to the ground connection. In addition, a supply voltage VDD is applied to the circuit arrangement.

The input LINI is connected between a first and a second ohmic resistance R 1, R 2. By way of example, the first resistor Rl have a resistance of 35k. The first and the second resistor Rl, R2 thus form a voltage-to-current converter SSW.

The terminal of the first resistor Rl facing away from the input LINI is connected to a first transistor M1, namely to the drain and the gate. The first transistor Ml is also connected to the source and BuIk to the positive supply voltage of the bus BVDD. In addition, the second terminal of the first resistor Rl facing away from the input LINI is connected to a second transistor M2 and to a third transistor M3, in each case at its gate. The second and the third transistor M2, M3 are each connected with their terminals Source and BuIk to the positive supply voltage of the bus BVDD.

In addition, the positive supply voltage of the bus BVDD is applied to a fourth and to a fifth transistor M4, M5, in each case at their source and bulk terminals. At the drain of the fourth transistor M4 is also the input LINI. The gate terminals of the fourth and fifth transistors M4, M5 are connected to the drain of the fifth transistor M5.

The second terminal of the second resistor R2 facing away from the input LINI can be applied to the negative supply voltage of the bus BVSS via a twelfth and a sixth transistor M12, M6. In this case, the second resistor R2 is connected to the source of the twelfth transistor M12, the drain of the twelfth transistor M12 is connected to the source and gate of the sixth transistor M6, and the drain of the sixth transistor M6 is connected to the negative supply voltage of the bus BVSS. The twelfth transistor M12 is connected with its gate terminal to a common node with gate terminals of a thirteenth transistor M13, a fourteenth transistor M14 and a fifteenth transistor M15. In addition, this node is connected to the source of the fourteenth transistor M14 and to the drain of the second transistor M2. Source of the thirteenth transistor M13 is also applied to the gate terminal of the fourth and fifth transistors M5. In addition, source of the fifteenth transistor M15 is connected to the drain of the third transistor M3.

The gate terminal of the sixth transistor M6 is commonly connected to gate terminals of a seventh transistor M7 and a ninth transistor M9. The drain of the thirteenth transistor M13 is connected to the source of the seventh transistor M7, and the drain of the seventh transistor M7 is connected to the negative supply voltage of the bus BVSS. The drain of the fourteenth transistor M14 is connected to the source and gate of an eighth transistor M8. The drain of the eighth transistor M8 is connected to the negative supply voltage of the bus BVSS. The ninth transistor M9 is connected to source to drain of the fifteenth transistor M15 and drain to the negative supply voltage of the bus BVSS.

A tenth and an eleventh transistor MIO, MIl are connected with their gate terminals both to the source of the tenth transistor MIO and to the drain of the third transistor M3. With their drain terminals of the tenth and the eleventh transistor MIO, MIl are each connected to the negative supply voltage of the bus BVSS. Drain of the eleventh transistor MIl is connected both to a current source whose further input corresponds to the supply voltage VDD and to a Schmitt trigger whose output terminal corresponds to the output RXDO. Preferably, the first five of the transistors Ml - M5 are designed as MOSFETs. In principle, however, the use of bipolar transistors instead of MOSFETs is generally possible.

In terms of functionality, the first resistor R1 corresponds to the pull-up resistor prescribed according to the LIN specification. At dominant level (low) on the LIN bus or at the input LINI current flows through the first resistor Rl. This current flow is mirrored via the arrangement of the first, second and third transistors M1-M3 and activated via the eighth and the fourteenth transistor M8, M14 and the twelfth, thirteenth and fifteenth transistors M12, M13, M15 connected as cascode transistors. Thus, a current flows through the second resistor R2, which is mirrored by the sixth, seventh and ninth transistor M6, M7, M9.

At the connection of the third and the fifteenth transistor M3, M15, the two current components are compared by the two resistors Rl, R2. If the proportion predominates through the first resistor Rl, a current flow occurs in the tenth transistor MIO, which is mirrored via the eleventh transistor MI1 and thereby pulls the output RXDO to ground or to the negative supply voltage of the bus BVSS.

The current share through the second resistor R2 is in principle undesirable, especially since it is not provided in the LIN specification. Therefore, the current share is preferably compensated by the second resistor R2. For this purpose, the current from the seventh transistor M7 via the fifth and the fourth transistor M5, M4 to the input LINI mirrored. Seen from the LIN bus LIN, the second resistor R2 thus becomes invisible.

With a recessive level on the LIN bus (high) there is no current flow in the first resistor R1, whereby the eighth and the fourteenth transistor M8, M14, which are connected as MOS diodes, are switched off. By the twelfth transistor M12 thereby the current flow in the second resistor R2 is suppressed and the entire circuit is de-energized. As a result, there is no high current consumption, which is limited to leakage currents both at the LIN bus LIN and at the supply connection.

Fig. 2 shows a modified embodiment which serves to reduce the power consumption during active operation. Scaling factors n and / or m can be introduced for this purpose. By way of example, a second scaling factor m is provided at the first, fourth and sixth transistors M1, M4, M6, a factor 1 is provided at the second, third, fifth and seventh transistors M2, M3, M5, M7 and a first scaling factor n at the ninth transistor M9. The second resistor R2 is dimensioned according to the product of the first scaling value n and the resistance value, e.g. B. 35k, the first resistor Rl. As a result, all currents except those reduced by the first resistor Rl accordingly. Since the speed requirements for such LIN receivers are low, since the maximum frequency of the LIN bus is fmax (LIN) = 2OkHz, correspondingly high scaling factors can be selected.

FIG. 3 shows an embodiment which, compared to the embodiment according to FIG. 2, is extended by a sixteenth transistor M16, which is preferably again a MOSFET. As is true for the other transistors, however, can Also corresponding circuits are constructed with bipolar transistors instead of field effect transistors. The sixteenth transistor M16 serves as an integrated polarity reversal protection diode, wherein the sixteenth transistor M16 is connected with its gate to the gate of the first transistor Ml. Drain and source are connected between the positive supply voltage of the bus BVDD and the source terminals of the first to fifth transistors Ml - M5. Thus, the positive supply voltage of the bus BVDD is no longer directly connected to the latter. By connecting the gate of the sixteenth transistor Mlβ this is at normal polarized supply voltage of the bus BVDD in Rdson operation (Rdson: on-resistance or drain-source resistance), whereby the resulting voltage drop can be neglected with appropriate dimensioning.

FIG. 4 shows a still further modified embodiment having additional components compared to the embodiment shown in FIG.

The circuit arrangement according to FIG. 4 additionally implements a hysteresis by using a seventeenth transistor M17, which is designed for example as a bipolar transistor. In addition, the arrangement has a switch S, which z. B. can be designed as an NMOS transistor. In detail, the seventeenth transistor M17 is connected to its gate with, inter alia, the gate of the sixth transistor M6 and is driven in accordance with the sixth transistor M6. Source of the seventeenth transistor M17 is connected to the negative supply voltage of the bus BVSS. Drain of the seventeenth transistor M17 is connected to one of the terminals of the switch S. The other terminal of the switch S is connected to the source terminal of the twelfth transistor M12. prevented. The switch S is switched by a connection to a node which connects the drain terminal of the eleventh transistor MIl with the Schmitt trigger and the voltage source. By such a circuit arrangement results in a hysteresis whose value is not constant but proportional to the supply voltage BVDD. This behavior is advantageous because the definition of hysteresis in the LIN specification refers to the supply voltage BVDD.

[0]

In addition to the various embodiments shown, there are a variety of other implementation options for achieving a reduced or even completely eliminated power consumption. For example, bipolar transistors may be used instead of MOSFETs. In particular, it is also possible to implement a correspondingly structured circuit arrangement which uses another voltage-to-current converter SSW instead of the one of the first and the second ohmic resistor R 1, R 2 shown. For example, MOS transistors connected as resistors can be used in place of the first and second resistors R1, R2.

In addition, additional cascodes, in particular NMOS and / or PMOS, can be used to increase the accuracy and / or dielectric strength in a corresponding circuit arrangement. It is also possible to use additional protective elements which do not influence the basic mode of operation, in particular resistors and / or Zener diodes for increasing the robustness of such a circuit arrangement.

In particular, the decoupling of a current signal instead of a voltage signal by appropriate redesign of the circuit arrangements is possible. Also advantageous is an additional switching of the seventh transistor M7 to adjust the compensation current to the hysteresis switching, since in the illustrated circuit arrangements, the compensation by the influence of the hysteresis transistor is not quite ideal.

Claims

claims

1. LIN receiver with sleep / wake-up functionality, featuring

an input (LINI) to a LIN bus (LIN),

- an output (RXDO) and

- Connections for at least one supply voltage (BVDD), characterized by

Transistors which are connected for activating the receiver in the event of a recessive state of the LIN bus by a state change on the LIN bus into an active state of the receiver.

2. LIN receiver according to claim 1, wherein the input (LINI) is connected between components of a voltage-to-current converter (SSW), in particular between a first and a second resistor (Rl, R2) is connected.

3. LIN receiver according to claim 2, wherein a first resistor (Rl) of the voltage-to-current converter (SSW) in such a way as pull-up

Resistor switched and dimensioned is that at dominant level at the input (LINI) current flows through the first resistor (Rl).

4. LIN receiver according to claim 3 with

- At least first, second and third transistors (Ml - M3), which are connected to mirror the flow of current through the first resistor (Rl), and

at least one eighth and one fourteenth transistor (M8, M14) and further twelfth, thirteenth and fifteenth transistors (M12, M13, M15) connected as cascode transistors, which are connected for activating the LIN receiver and / or the output (RXDO ).

5. LIN receiver according to one of claims 2 to 4, wherein

- A second resistor (R2) of the voltage-to-current converter (SSW) by means of transistors (M12, M6) is connected to a negative supply voltage (BVSS) or ground switchable.

6. LIN receiver according to claim 5, wherein at least a third and a fifteenth transistor (M3, M15) between a positive supply voltage (BVDD) and the negative supply voltage (BVSS) or ground are connected to compare a current flow component through the first resistor ( Rl) and a current flow portion through the first resistor (R2).

A LIN receiver according to claim 6, wherein a tenth and an eleventh transistors (MIO, MIl) are connected on the output side to the third and the fifteenth transistors (M3, M15), the output (RXDO) to ground or the negative supply voltage of the To draw bus (BVSS).

8. LIN receiver according to one of claims 5 to 7, wherein the at least a fourth, a fifth and a seventh transistor

(M4, M5, M7) are connected between the positive supply voltage (BVDD) and the negative supply voltage (BVSS) or ground such that a current flow rate through the second resistor (R2) of the voltage-to-current converter (SSW) the Ga - Terminal of the seventh transistor (M7) and via the fourth and the fifth transistor (M4, M5) drives to compensate for the current share through the second resistor (R2).

9. LIN receiver according to one of claims 5 to 8, wherein at least one eighth and a fourteenth transistor (M8, M14) are connected between the positive supply voltage (BVDD) and the negative supply voltage (BVSS) or ground such that they have a Switch off current flow through the second resistor (R2) at the recessive level at the input (LINI) by means of a switch.

10. LIN receiver according to one of claims 5 to 9, wherein a switch (S) and for generating a hysteresis a seventeenth transistor (M17) as additional components in series between the second resistor (R2) and the negative supply voltage (BVSS) or ground, the switch (S) being switched to turn on or off a current flow through the seventeenth transistor (M17), depending on a switching state at the output (RXDO).

11. The LIN receiver according to one of claims 2 to 10, wherein the transistors are dimensioned by means of scaling factors (m, n, 1), all currents except those through a first resistor (Rl) of the voltage-to-current converter (SSW ) accordingly.

12. LIN receiver according to one of claims 2 to 11, wherein a sixteenth transistor (M16) as an integrated reverse protection diode between a positive supply voltage (BVDD) and the other transistors is connected.