EP2092645A2 - A switching circuit - Google Patents

A switching circuit

Info

Publication number
EP2092645A2
EP2092645A2 EP07848034A EP07848034A EP2092645A2 EP 2092645 A2 EP2092645 A2 EP 2092645A2 EP 07848034 A EP07848034 A EP 07848034A EP 07848034 A EP07848034 A EP 07848034A EP 2092645 A2 EP2092645 A2 EP 2092645A2
Authority
EP
European Patent Office
Prior art keywords
data input
node
input unit
switching circuit
control unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP07848034A
Other languages
German (de)
French (fr)
Inventor
Cagatay Buyuktopcu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Arcelik AS
Original Assignee
Arcelik AS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Arcelik AS filed Critical Arcelik AS
Publication of EP2092645A2 publication Critical patent/EP2092645A2/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1731—Optimisation thereof
    • H03K19/1732—Optimisation thereof by limitation or reduction of the pin/gate ratio
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0231—Astable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M11/00—Coding in connection with keyboards or like devices, i.e. coding of the position of operated keys
    • H03M11/22—Static coding
    • H03M11/24—Static coding using analogue means, e.g. by coding the states of multiple switches into a single multi-level analogue signal or by indicating the type of a device using the voltage level at a specific tap of a resistive divider

Definitions

  • the present invention relates to a switching circuit.
  • data input is generally done by either using an ADC (analog digital converter) channel of the microprocessor or by using the I/O (input/output) pins.
  • ADC analog digital converter
  • I/O input/output
  • browsing method is used at least 3-4 I/O pins are set aside for data input.
  • I/O pin number is limited, setting aside 3-4 I/O pins for only this job leaves the card designers in a dilemma. Both conditions increase the cost of the electronic cards that will be produced.
  • the object of the present invention is to design a switching circuit that does not use the ADC channels of the control unit and supplies data input by using a minimum number of 170 pins.
  • the op-amp compares received analog signals with the reference voltage value received from the voltage divider circuit.
  • the quality of the received analog signals are changed to produce square wave numerical signals.
  • these numerical signals are directed to one pin of the control unit by the data input unit.
  • the control unit calculates the differences of frequencies and chooses which switch is closed.
  • a resistor is provided for regulating the current delivered to the control unit. This resistor prevents the probable over-currents.
  • the numerical signals supplied as a result of comparisons are delivered to the input capture unit pin of the control unit.
  • the software to be used in the control unit of the switching circuit is reduced.
  • the cost of software decreases with the said unit.
  • Figure 1 - is the schematic view of the switching unit.
  • the elements illustrated in the figures are numbered as follows:
  • the switching circuit (1) comprises,
  • control unit (9) that controls data input and connected to the exit end "A" point of the data input unit (8).
  • the voltage divider circuit (6) comprises two resistors (Rl, R2).
  • the node (“E") wherein the resistors (Rl, R2) are connected to each other is also connected to one of the entrance ends (B2 or B3) of the op-amp (5).
  • the control unit (9) is a microcontroller or a microprocessor.
  • the "C” node is the point where one end of the capacitor (4), one ends of the switches (2, 21, 22) and the entrance leg (B2 or B3) of the op-amp (5) join together.
  • the "D" node is the point where the exit leg (Bl) of the op-amp (5), the feed back resistors (3, 31, 32), the voltage divider circuit (6) and the current limiting circuit (7) join together.
  • the "A" point is the point at which the data input unit (8) is connected to the control unit (9). Data input information is transferred to the control unit (9) with this end ("A") to be processed.
  • the data input unit (8) comprising the switches (2, 21, 22) , the feed back resistors
  • the electronic card is used for the control of a device that requires data input.
  • the op-amp (5) is fed with ⁇ 5 volt according to the requirements of the electronic device wherein the electronic card will be used, then ⁇ 5 volt is seen at node "D" (the op-amp feeds are not shown in the figure).
  • the path leading to the capacitor (4) cannot be completed through the feed back resistor (3 or 31 or 32). Therefore, voltage is not produced in the leg (B2 or B3) of the op-amp (5) connected to the feed back resistors (3, 31, 32).
  • the feed back path is the path that joins the entrance (B2 or B3) and the exit (B 1) of the op-amp (5) by means of the switches (2, 21, 22) and the resistors (3, 31, 32).
  • an "input capture unit (ICP)" is provided in the control unit (9). If this feature of the control unit (9) is used, the exit end ("A") of the data input unit (8) is directly connected to the pin of the input capture unit. In this embodiment, the frequency can be calculated with a software. [0024] In an embodiment of the present invention, the exit ("A") of the data input unit (8) is connected to any pin of the control unit (9) and the required software is applied to the control unit (9) if the ICP pin is reserved for another task or if there is no such unit at the control unit (9) due to the requirements of the electronic card. Thus which switch (2 or 21 or 22) is closed can be detected.
  • the data input circuit (1) provides the frequency generated when any one switch (2 or 21 or 22) is closed to always be at different values from the frequency generated when that switch (2 or 21 or 22) is opened and a different switch (2 or 21 or 22) is closed. Then the different square wave frequencies produced by the data input circuit (1) is delivered to the control unit (9). These differences in frequency are calculated by the control unit (9) to easily detect which switch (2 or 21 or 22) is closed. Consequently without using the ADC channel of the control unit (9) and using any idle pin, any number of data input can be retrieved over the same pin accurately and inexpensively.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Electronic Switches (AREA)
  • Keying Circuit Devices (AREA)

Abstract

The present invention relates to a switching circuit (1) wherein the frequency generated when any one switch (2 or 21 or 22) is closed to always be at different values from the frequency generated when that switch (2 or 21 or 22) is opened and a different switch (2 or 21 or 22) is closed.

Description

Description A SWITCHING CIRCUIT
[0001] The present invention relates to a switching circuit.
[0002] In electronic cards, data input is generally done by either using an ADC (analog digital converter) channel of the microprocessor or by using the I/O (input/output) pins. When the ADC channel is used for data input and when the ADC channel reserved for data input is required for another process, either a different microprocessor has to be used or extra circuits are used to provide for the necessary requirements. When browsing method is used at least 3-4 I/O pins are set aside for data input. In electronic cards wherein I/O pin number is limited, setting aside 3-4 I/O pins for only this job leaves the card designers in a dilemma. Both conditions increase the cost of the electronic cards that will be produced.
[0003] In state of the art Japanese Patent Document No JP54016089, a circuit is defined wherein the process of data inputting from more than one channel is provided through an input terminal by producing a different analog signal when each switch is closed.
[0004] The object of the present invention is to design a switching circuit that does not use the ADC channels of the control unit and supplies data input by using a minimum number of 170 pins.
[0005] In the switching circuit designed to fulfill the objective of the present invention, explicated in the first claim and the respective claims thereof, as a result of sending analog signals from various inputs to the operational amplifier, the op-amp compares received analog signals with the reference voltage value received from the voltage divider circuit. As a result of the comparisons made in the op-amp, the quality of the received analog signals are changed to produce square wave numerical signals. Afterwards these numerical signals are directed to one pin of the control unit by the data input unit. The control unit calculates the differences of frequencies and chooses which switch is closed. Thus, a large quantity of data input can be made by using only one pin of the control unit and without taking into consideration which pin this is in the control unit. This provides considerable flexibility for the electronic card producers and also reduces the cost of chips used in the electronic cards.
[0006] At the outlet of the data input unit in the switching circuit, a resistor is provided for regulating the current delivered to the control unit. This resistor prevents the probable over-currents.
[0007] In another embodiment of the present invention, the numerical signals supplied as a result of comparisons are delivered to the input capture unit pin of the control unit. When the input capture unit is used, since there are some additional functions in this unit, the software to be used in the control unit of the switching circuit is reduced. Thus the cost of software decreases with the said unit.
[0008] The switching circuit designed to fulfill the objective of the present invention is il- lustrated in the following figure, where:
[0009] Figure 1 - is the schematic view of the switching unit. [0010] The elements illustrated in the figures are numbered as follows:
1. Switching circuit
2. 21, 22. Switch
3. 31, 32. Feed back resistor
4. Capacitor
5. Operational amplifier (op-amp)
6. Voltage divider circuit
7. Current limiting resistor
8. Data input unit
9. Control unit
[0011] The switching circuit (1) comprises,
- switches (2, 21, 22) used in data input with one ends connected to node ("C"),
- feed back resistors (3, 31, 32) in the same number as the switches (2, 21, 22), each one connected in series with one switch (2 or 21 or 22) and the end not connected to switches (2 or 21 or 22) being connected to node ("D"),
- a capacitor (4) with one end connected to node ("C") and the other end connected to the ground, being charged or discharged through the feed back resistor (3, 31, 32) when any one switch (2 or 21 or 22) is closed,
- at least one op-amp (5) that produces square waves, with one of the entrance ends (B2 or B3) connected to node "C", the other entrance end (B2 or B3) connected to node "E", and the exit end (Bl) connected to node "D",
- a voltage divider circuit (6) with one end connected to node "D", the other end to the ground, and
- a data input unit (8) having a current limiting resistor (8) positioned between node "D" and the exit end node "A", and
- a control unit (9) that controls data input and connected to the exit end "A" point of the data input unit (8).
[0012] If the switches (2, 21, 22) are closed, the feed back resistors (3, 31, 32) are in parallel position to each other. [0013] The voltage divider circuit (6) comprises two resistors (Rl, R2). The node ("E") wherein the resistors (Rl, R2) are connected to each other is also connected to one of the entrance ends (B2 or B3) of the op-amp (5).
[0014] The control unit (9) is a microcontroller or a microprocessor. [0015] The "C" node is the point where one end of the capacitor (4), one ends of the switches (2, 21, 22) and the entrance leg (B2 or B3) of the op-amp (5) join together. [0016] The "D" node is the point where the exit leg (Bl) of the op-amp (5), the feed back resistors (3, 31, 32), the voltage divider circuit (6) and the current limiting circuit (7) join together.
[0017] The "A" point is the point at which the data input unit (8) is connected to the control unit (9). Data input information is transferred to the control unit (9) with this end ("A") to be processed.
[0018] The data input unit (8) comprising the switches (2, 21, 22) , the feed back resistors
(3, 31, 31), the capacitor (4), the op-amp (5) and the voltage divider circuit (6) and the switching circuit (1) comprising the control unit (9) are positioned on an electronic card. The electronic card is used for the control of a device that requires data input.
[0019] If the op-amp (5) is fed with ±5 volt according to the requirements of the electronic device wherein the electronic card will be used, then ±5 volt is seen at node "D" (the op-amp feeds are not shown in the figure). When any one switch (2 or 21 or 22) is not closed in the device wherein the card will be used, the path leading to the capacitor (4) cannot be completed through the feed back resistor (3 or 31 or 32). Therefore, voltage is not produced in the leg (B2 or B3) of the op-amp (5) connected to the feed back resistors (3, 31, 32). Meanwhile, in the leg (B2 or B3) of the op-amp (5) connected to the voltage divider circuit (6) a voltage is produced that is regulated by the resistors (Rl, R2). When the voltage in the said two legs (B2, B3) of the op-amp (5) is compared, the voltage that will be delivered to the exit is reversed. (The op-amp (5) used here is an inverted op-amp) Thus a logic 1 (Logic high) signal is formed at the end of the op-amp (5) connected to node "D".
[0020] When one of the switches (2 or 21 or 22) is closed in the device wherein the card will be used, since the path leading to the capacitor (4) is completed over the feed back resistor (3 or 31 or 32), the capacitor (4) starts to be charged. When the capacitor (4) reaches a certain value, the output of the op-amp (5) connected to node "D" shifts state and the value becomes logic 0 (Logic low). This time the capacitor (4) starts to be discharged through the feed back resistor (3 or 31 or 32) which is in transmission during that time. After the capacitor (4) is discharged to reach to certain value, the op- amp (5) again shifts state and the value comes to logic 1 level. In other words, as long as the switch (2 or 21 or 22) remains closed, the switching circuit (1) functions as a standard square wave generator.
[0021] The feed back path is the path that joins the entrance (B2 or B3) and the exit (B 1) of the op-amp (5) by means of the switches (2, 21, 22) and the resistors (3, 31, 32).
[0022] When feed back resistors (3, 31, 32) of different values are used for each switch (2 or 21 or 22) on the feed back path, the square wave frequencies generated become different. When square wave of different frequencies is produced at the exit (Bl) of the op-amp (5), this difference is detected by a pin of the control unit (9).
[0023] In an embodiment of the present invention, an "input capture unit (ICP)" is provided in the control unit (9). If this feature of the control unit (9) is used, the exit end ("A") of the data input unit (8) is directly connected to the pin of the input capture unit. In this embodiment, the frequency can be calculated with a software. [0024] In an embodiment of the present invention, the exit ("A") of the data input unit (8) is connected to any pin of the control unit (9) and the required software is applied to the control unit (9) if the ICP pin is reserved for another task or if there is no such unit at the control unit (9) due to the requirements of the electronic card. Thus which switch (2 or 21 or 22) is closed can be detected.
[0025] The data input circuit (1) provides the frequency generated when any one switch (2 or 21 or 22) is closed to always be at different values from the frequency generated when that switch (2 or 21 or 22) is opened and a different switch (2 or 21 or 22) is closed. Then the different square wave frequencies produced by the data input circuit (1) is delivered to the control unit (9). These differences in frequency are calculated by the control unit (9) to easily detect which switch (2 or 21 or 22) is closed. Consequently without using the ADC channel of the control unit (9) and using any idle pin, any number of data input can be retrieved over the same pin accurately and inexpensively.

Claims

Claims
[0001] A switching circuit (1) comprising a data input unit (8) having - switches (2, 21,
22) used in data input with one ends connected to node ("C"), - feed back resistors (3, 31, 32) in the same number as the switches (2, 21, 22), each one connected in series with one switch (2 or 21 or 22) and the ends not connected to switches (2 or 21 or 22) being connected to node ("D"), - a capacitor (4) with one end connected to node ("C") and the other end connected to the ground, being charged or discharged through the feed back resistor (3, 31, 32) when any one switch (2 or 21 or 22) is closed, - and characterized by a data input unit (8) having - at least one op-amp (5) that produces square waves, with one of the entrance ends (B2 or B3) connected to node "C", the other entrance end (B2 or B3) connected to node "E", and the exit end (Bl) connected to node "D", -a voltage divider circuit (6) with one end connected to node "D", the other end to the ground, and - a data input unit (8) that produces square waves with a different value for each resistor (3 or 31 or 32) value by means of the operational amplifier (5) whereon the feed back resistor (3 or 31 or 32) of different values connected in parallel to each of the switches (2 or 21 or 22) is applied as input, and - a control unit (9) that controls data input and connected to the exit end "A" point of the data input unit (8).
[0002] A switching circuit (1) as in Claim 1, characterized by a data input unit (8) comprising a voltage divider circuit (6) having two resistors (Rl, R2) and one end connected to node "D" and the other end to the ground.
[0003] A switching circuit (1) as in Claim 1 or 2, characterized by a data input unit (8) comprising a current limiting control resistor (7) that is positioned between node "D" whereto the exit leg of the operational amplifier (5) is connected and the node "A", which is the exit end of the data input unit (8).
[0004] A switching circuit (1) as in any one of the above claims, characterized by a control unit (9) comprising an ICP pin whereto the exit (A) of the data input unit (8) is directly connected.
EP07848034A 2006-12-11 2007-12-11 A switching circuit Withdrawn EP2092645A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TR200607022 2006-12-11
PCT/EP2007/063641 WO2008071675A2 (en) 2006-12-11 2007-12-11 A switching circuit

Publications (1)

Publication Number Publication Date
EP2092645A2 true EP2092645A2 (en) 2009-08-26

Family

ID=39512130

Family Applications (1)

Application Number Title Priority Date Filing Date
EP07848034A Withdrawn EP2092645A2 (en) 2006-12-11 2007-12-11 A switching circuit

Country Status (2)

Country Link
EP (1) EP2092645A2 (en)
WO (1) WO2008071675A2 (en)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH031284A (en) * 1989-03-04 1991-01-07 Fujitsu Ten Ltd Constant setting device of microcomputer
FR2677832A1 (en) * 1991-06-11 1992-12-18 Alcatel Business Systems Method and device for generating digital data for programming circuits
US6603366B2 (en) * 2001-08-10 2003-08-05 Texas Instruments Incorporated Trimmable oscillator
GB2379754B (en) * 2001-09-13 2005-08-24 Nec Technologies An apparatus for harware revision identification using a R-C circuit
US7605723B2 (en) * 2004-12-14 2009-10-20 Cirrus Logic, Inc. Circuits and methods for implementing mode selection in multiple-mode integrated circuits

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2008071675A3 *

Also Published As

Publication number Publication date
WO2008071675A3 (en) 2008-12-11
WO2008071675A2 (en) 2008-06-19

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