EP2082485A2

EP2082485A2 - System for the flexible configuration of functional modules

Info

Publication number: EP2082485A2
Application number: EP07803360A
Authority: EP
Inventors: Udo Grittke; Axel Humpert; Dietmar FRÜHAUF; Romuald Girardey; Jürgen Becker; Katarina Paulsson; Michael HÜBNER
Original assignee: Endress and Hauser SE and Co KG
Current assignee: Endress and Hauser SE and Co KG
Priority date: 2006-10-17
Filing date: 2007-09-10
Publication date: 2009-07-29
Also published as: EP2113067A1; EP2082191A1; US20110025376A1; WO2008046696A3; US20110035576A1; WO2008046696A2; EP2113067B1; WO2008046694A1; US20110029254A1; US8271773B2; WO2008046695A1; EP2082191B1

Abstract

The invention relates to a system (1) for the flexible configuration of functional modules (2), said system (1) comprising the following components: a plurality of logic cells (3) in a hardwired FPGA / Standard ASIC structure, the logic cells (3) being configurable by means of configuration registers (4a) in such a manner that they execute elementary logic functions, a connection matrix (6) having a pluarlity of memory cells via which different logical interconnections of the logic cells (3) can be configured in defined complex interconnections by means of the configuration registers (4a, 4b), and a control unit (8) which partially dynamically configures the logic cells (3) and the connection matrix (6) via an internal bus (18) and via the configuration registers (4a, 4b), using a configuration bit stream, in such a manner that the hardwired FPGA / ASIC structure functionally behaves like a partially dynamically re-configurable logic unit.

Description

Description System for flexible configuration of function modules

The invention relates to a system for flexible configuration of functional modules, in particular for the flexible configuration of functional modules in a field device of process automation.

[0002] In automation technology, in particular in process automation technology, field devices are often used which serve to determine and monitor process variables. Examples of such field devices are level gauges, flowmeters, analyzers, pressure and temperature measuring devices, humidity and conductivity meters. The sensors of these field devices detect the corresponding process variables, e.g. level, flow, pH, substance concentration, pressure, temperature, humidity and conductivity.

Under the term 'field devices' but also actuators, z. B. valves or

Pumps, subsumed, via which, for example, the flow of a liquid in a pipeline or the level in a container can be changed. A large number of such field devices are offered and distributed by the Endress + Hauser Group.

As a rule, field devices in modern automation systems are connected via communication networks (HART-Mαltidrop, Profibus, Foundation Fieldbus, etc.) to a higher-level unit, which is referred to as a control system or control room. This higher-level unit is used for process control, process visualization, process monitoring as well as for commissioning or operating the field devices.

Necessary additional components for the operation of fieldbus systems that are directly connected to a fieldbus and that are used in particular for communication with the higher-level units are also often referred to as field devices. These additional components are, for. These include remote FOs, gateways, linking devices, and controllers.

It is also known to integrate fieldbus systems in corporate networks that operate on Ethernet basis. These enterprise-internal bus systems make it possible to access process or field device information from different areas of a company. In addition, it is state of the art that, for the purpose of worldwide communication, corporate networks with public networks, e.g. As the Internet, connected.

For operating and commissioning of the field devices are appropriate

Operating programs necessary. Well-known here are, for example, the operating program FieldCare from Endress + Hauser, the operating program AMS from Emerson and the operating program Simatic PDM from Siemens.

For controlling and monitoring systems with a variety of field devices are used Leitsysteme- applications such. Simatic S7 from Siemens, Freelance from ABB and Delta V from Emerson.

An essential aspect of open communication systems, such. As Profibus, Foundation Fieldbus or HART, is the interoperability and interchangeability of devices from different manufacturers. This allows sensors or actuators from different manufacturers to be used together in one system without any problems. It is also possible to replace a field device of a manufacturer by a functionally identical field device of another manufacturer, whereby the customer has maximum freedom in the configuration of his process plant.

Field devices are becoming increasingly complex in terms of their functionality. In addition to pure measured value processing, diagnostic tasks and, above all, communication tasks that field devices have to fulfill with regard to the bus systems used, are becoming more and more complex. Even more complex are the functionalities of field devices with Mαltisensorik, which are able to determine or monitor at least two process variables in parallel. In order to meet the increasing demands, a plurality of microcontrollers are usually provided in parallel in a field device. The advantage of using microcontrollers is that application-specific software programs that run in these microcontrollers, a variety of functionalities are feasible and program changes are relatively easy to carry out. Program-controlled field devices are therefore flexible to a great extent. However, this high flexibility is paid for by the disadvantage that the processing speed is slowed down by the sequential program execution.

In order to increase the processing speed, ASICs - Application Specific Integrated Circuits - are always used in the field devices, if it makes sense. The application-specific configuration allows these devices to process data and signals much faster than a software program can do. ASICs are particularly suitable for compute-intensive applications. A disadvantage of the application of ASICs is that the functionality of this

Blocks is fixed. A subsequent change in functionality is not possible with these blocks. Furthermore, the use of ASICs pays off only in very large quantities, since the development effort and the associated costs are relatively high.

In order to avoid the maladministration of the fixed predetermined functionality, a configurable field device is known from WO03 / 098154, in which a reconfigurable logic device is provided in the form of an FPGA. In this known solution, the logic module with at least one microcontroller, which is also referred to as an embedded controller, configured at system start. After the configuration is completed, the required software is loaded into the microcontroller.

The reconfigurable logic device required in this case must have sufficient resources - logic, wiring and memory resources - to meet the desired functionality. Logic devices with many resources have the disadvantage that they require a lot of energy, which complicates their use in process automation. A disadvantage in the use of logic devices with few resources and thus with a lower energy consumption is the significant limitation in the functionality of the corresponding field device.

In the simultaneously filed with this International application International patent application, the priorities of three German patent applications: DE 10 2006 049 509.8, DE 10 2006 049 501.2, DE 10 2006 049 502.0, filed on 17.10.2006 claims, The advantages of the partial, dynamic reconfigurability of logic modules for use in fieldbus devices are described in detail. There are several advanced technologies in the semiconductor market that combine the high flexibility in the design phase of FPGA architectures with the energy efficiency of final ASIC architectures. Examples of this are the technologies "HardCopy" by Altera or "EasyPath" by XILINX. With these technologies, power-saving, hard-wired architectures can be generated very quickly and cost-effectively. However, due to the fixed wiring, these architectures have the disadvantage that the suitability for reconfigurability, especially for partial and dynamic reconfigurability, is lost.

The invention is based, at least certain portions of a task electronic hardware structure, which in itself is not dynamically configurable, dynamically or partially dynamically configurable.

The object is achieved by a system comprising the following components: a plurality of logic cells in a hard-wired FPGA / standard ASIC structure, wherein the logic cells or the logic blocks are configurable by means of configuration registers so that they perform elementary logic functions; a link matrix having a plurality of memory cells via which different logical associations of the logic cells in defined complex associations are configurable by means of the configuration registers; and a controller which dynamically or dynamically couples the logic cells and the association matrix via an internal bus and via the configuration registers by means of a configuration bit stream partially dynamically configured so that the hard-wired FPGA / standard ASIC structure behaves functionally as a dynamic or partially dynamically reconfigurable standard logic device. The configuration can be referred to as static / dynamic co-design. The invention provides an architecture that combines all the advantages of partial, dynamic reconfigurability - as described in the above cited parallel International Patent Application - with those of hardwired architectures. These advantages are paramount: very short development times, cost reduction and energy savings. As an added benefit, a significantly faster reconfiguration is achieved.

The hard-wired FPGA / standard ASIC structure is preferably a hard-copy FPGA, an EASY path, a flash FPGA or an FPGA based on the anti-fuse technology.

In principle, any of these known FPGA technologies can be used to turn a rigid, configurable electronic architecture into a highly flexible, configurable electronic architecture. Generally speaking, according to the invention, a partially dynamic reconfigurable structure in a standard design process (e.g., Altera Structured ASIC, Xilinx Flex Path, Antifuse FPGA) is virtually mapped to a hardwired FPGA / ASIC structure through implementation and integration of a flexible FPGA model

The dynamically reconfigurable functional modules are, for example, microprocessors to A / D or D / A converter with different bit resolution, to signal filter with different filter functions to modems for connection to different bus systems to different power control units or different input / output units. A A preferred embodiment of the solution according to the invention provides that, in addition to the regions of the dynamically reconfigurable functional modules, at least one static region is provided in which at least one predefinable functional module is permanently configured. The permanently configured functional module may be, for example, a microprocessor with a given bus width.

The advantages of the solution according to the invention are diverse and extend far beyond what are previously known to be able to afford solutions:

- The configuration is based on a known technology and on

Standard processes;

- The variability and flexibility of the configuration is basically unlimited;

- Due to the hard-wired architecture, a high processing speed and thus a low processing time is achieved so that inventively configured systems work in real time;

- Due to the fixed wiring of the architecture, the power / energy consumption is low;

- Another power / energy saving is possible by the fact that only the currently required function modules are configured;

- It can achieve a high integration density.

In a preferred embodiment of the system according to the invention, a logic cell consists of an n-bit look-up table structure, wherein the n inputs via a multiplexer select an associated configuration register and so configure the desired elementary logic function. For example, the n inputs are two inputs A, B. The configurable elementary logic function of a logic cell is, for example, an AND, an OR, a NAND, NOR, ExOR or ExNOR link.

An advantageous development of the system according to the invention provides that each logic cell is associated with a flip-flop and that at the output of the logic cell, the output signal of the flip-flop is available. The integration of a flip-flop allows the integration of sequential logic, such as a finite-state machine.

As already explained in detail above, the system according to the invention is preferably used in field devices in the field of process automation. Field devices serve, as already stated, to determine or monitor a physical or chemical process variable. At the physical or chemical process size These are, for example, pressure, level, flow, turbidity, concentration of a chemical, viscosity, density, temperature, humidity, pH, or conductivity.

The impressive advantages of the solution according to the invention can be seen in particular in the high flexibility, the low energy consumption and the provision of measurement data in real time. The solution according to the invention makes it possible to configure the control and evaluation unit of any field device on the basis of a known ASIC (examples have already been mentioned above). Since the different field devices of a manufacturer can rely on one and the same hardware due to the inventive solution, the inventive solution is also cost-effective to implement, since the hard-wired FPGAs / standard ASICs are the more cost-effective, the higher the number of pieces to be manufactured. Furthermore, a field device can be easily reconfigured for any other use at any time. The solution according to the invention also offers great advantages in the field of molecular sensors, where a control / evaluation unit must be able to respond to different sensor types in parallel or intermittently. Since it is provided according to the invention that only the currently required function modules are dynamically or partially dynamically configured, the power supply is ensured even with very complex FPGA / ASIC structures.

Although the system according to the invention is always referred to in the embodiments in conjunction with a field device, the system can also be used in other areas, for example in the automotive or aircraft technology. With regard to its application possibilities, it can be used everywhere where hardwired FPGAs / standard ASICs are used and where energy saving makes sense. Thus, the use of the solution according to the invention is certainly also to be considered in commercial PCs into consideration.

The invention will be explained in more detail with reference to the following drawings. It shows:

1 shows the structure of a known ASIC, which is used for example in a pressure gauge,

2a shows a first embodiment of the partially dynamically configurable system according to the invention, which is also used in a pressure gauge,

2b shows a second embodiment of the dynamic or partially dynamically configurable system according to the invention, which is used in a pressure gauge,

Fig. 3. a schematic representation of an embodiment of the inventive virtual FPGA / ASIC structure,

FIG. 4 shows an exemplary representation of a logic cell which can be used in the system according to the invention and FIG

FIG. 5 shows an exemplary representation of a virtual linking matrix that can be used in the system according to the invention. FIG.

Fig. 1 shows the known structure of an ASIC, which is used for example in a pressure gauge. Pressure gauges can be used for different applications, for example for absolute, relative or differential pressure measurement, for determining the filling level of a product in a container or for determining the flow rate of a medium through a pipeline. In the case shown in Fig. 1, the pressure gauge is used for level measurement. Corresponding pressure gauges which can be used in different applications are offered and sold by the applicant.

The measured data receives the known control / evaluation unit 19, which is usually housed in a transmitter, from a not shown in Fig. 1 pressure sensor via the analog input 24. The analog input 24 is marked with IN. Since the ASIC is hard-wired, the control / evaluation unit 19 with the function modules 2 can be used exclusively in the predefined special application. In the case shown, the control / evaluation unit 19 is designed for a pressure gauge in the 'level measurement' application. The field device is subsequently used exclusively in a pressure measuring device which is used for level measurement and, moreover, transmits its data via a HART protocol to a higher-level control room, which is not separate in FIG. The corresponding data line 24 is labeled OUT.

In detail, Fig. 1 shows the following hard-wired system:

The analog measurement data are converted by an 8-bit A / D converter 12 into digital data, wherein the accuracy of the implementation depends crucially on the bit resolution of the A / D converter 12. Subsequently, the digital data in the filter 14 of a certain type 2 are filtered and evaluated in the evaluation unit 22. In this case, the determination of the fill level value L takes place via a functional dependency on P. Specifically, this is a polynomial P = f (p, T), which functionally depends on the pressure p and the temperature T. In the function module 23 then takes place the calculation of the corresponding level value. Subsequently, the digital value in the D / A converter / filter 13 becomes an analog measurement value implemented and filtered appropriately. Via a HART modem 15, which is likewise controlled by the microcontroller 11, the measurement data and status information are transmitted to the higher-level control room in accordance with the HART protocol. The control of the individual functional modules 2 is carried out by the microprocessor 11 via the control lines 26th

Fig. 2a shows a first embodiment of the dynamically or partially dynamically configurable system 1 according to the invention, which is used for example in a pressure gauge, but according to the invention can also be used for other applications.

The aim of the system 1 according to the invention is to make at least certain function modules 2 of a non-dynamic or partially dynamic hardware reconfigurable electronic ASIC architecture flexible. This is accomplished by mapping logic cells modeled in the hardware description language VHDL to a hardwired FPGA / ASIC standard structure in a standard design process. For example, the standard design process is Altera Structured ASIC, Xilinx FlexPath, or Antifuse FPGA.

The serious difference to the known solution shown in Fig. 1 consists in the high flexibility, which provides the solution according to the invention. It should be noted that certain functional modules 11, 22 may continue to have a hard-wired structure, and that only certain functional modules 2; 12, 13, 14, 15, 16, 23 are designed partially dynamically configurable. The control of the configurable configured function modules 12, 13, 14, 15, 23 via the controlled by the control unit 8 configuration bit stream, which is transmitted via the internal bus 25 to the individual functional modules 2 to be controlled. According to the invention, the configuration is such that the hard-wired FPGA / ASIC structure behaves functionally as a partially dynamically reconfigurable logic device. The logic module is preferably a standard FPGA.

Thus, any desired configuration of the individual configurable

Functional modules 2; 12, 13, 14, 15, 16, 23 with one and the same FPGA possible. The freedom in the selection of the different configurations of the functional modules 2 can be seen in FIG. 2 in that in each of the functional modules 2; 12, 13, 14, 15, 16, 23 different configurations are shown. Thus, both the A / D converter 12 and the D / A converter 13 may include different bit resolutions of 8bit, 12bit, 16bit or 21bit. Likewise, in the functional module 14 or in the function module 13 different types of filters are configured.

Due to the dynamic configuration of the functional module 23, it is possible to optimally tune the pressure sensor, which can work in different applications, such as level, flow and pressure, to the respective application. High flexibility is also provided in the area of data transmission to a higher-level control room - data line 24 marked OUT -. For example, a HART, a PA - Profibus PA - or an FF - Fieldbus Foundation - can be selected so that the data transmission can take place according to the selected protocol to the control room.

Fig. 2b shows a second embodiment of the dynamic configurable system 1 according to the invention, which can be used in a pressure gauge. With regard to the embodiment shown in FIG. 2a, this embodiment differs essentially in the insertion of the functional module 18, which is identified by 'linking matrix'. This function module 18 makes it possible to link the dynamically reconfigurable function modules 2 in a suitable manner. In addition to the possibilities to suitably connect logic cells 3 and wiring resources, according to a development of the system 1 according to the invention, it is thus also possible to dynamically reconfigurable function modules 2; 12, 13, 14, 15, 16, 23 partially dynamically link together to create such highly complex, temporary FPGA / ASIC structures.

Reference to the following figures Fig. 3, Fig. 4, Fig. 5, the concrete operation of the system 1 according to the invention will be described. 3 shows a schematic representation of an embodiment of the virtual FPGA / standard ASIC structure according to the invention. Roughly speaking, this structure corresponds to a virtual FPGA standard structure with a predefined set of resources: logic cells 3, wiring resources 6 and memory cells 10.

3 shows schematically a 7 × 5 grid structure of logic cells 3 and the linking matrix 6 of the virtual FPGA structure 1 according to the invention. The linking matrix 6 contains the appropriate links of the wiring resources. This structure 1 is preferably used together with hardwired functional modules 2; 11, 22 implemented on a chip. Technically, the flexible areas 2; 12, 13, 14, 15, 16, 23, as well as the hardwired areas 2; 11, 22 realized with predetermined fixed resources of the logic device FPGA used, but by the implementation and integration of the flexible FPGA solution, the logic cells 3 and the logic blocks and the wiring resources of the linking matrix 6 are kept flexible by using logic gates.

Fig. 4 shows an example of the structure of a selected from Fig. 3 logic cell 3 with a two-bit look-up table structure and with flip-flop 10. The two inputs A and B of the logic cell 3 via a Mαltiplexer 9 select the Configuration register 4a on. Thus, for example, in constellation A = I and B = I, the right configuration register 4a, which contains the logic 1, is selected and made available at the output Q_LUT. The selected logic cell 3 represents a logical AND function with two inputs. Furthermore, the signal of the clock-controlled flip-flop 10 is available at the output Q_FF. By integrating a flip-flop 10, the integration of sequential logic, such as that of a finite state machine, is enabled.

In the dynamic and partial dynamically reconfigurable virtual FPGA 1 according to the invention, the contents of the configuration register 4; 4a, 4b are manipulated via the configuration interface 5 by means of the configuration bit stream generated by the control unit 11. For example, by writing the sequence Ol l i into the configuration registers 4a, the logical OR function can be realized. The method thus allows any elementary logic functions to be represented. It goes without saying that the restriction to two inputs A, B is arbitrary and serves only the clarity of the drawn facts. In principle, it can be said that the design of the logic cells 3 is model-based and thus parameterizable. It goes without saying that all desired gate sizes can be implemented. In addition, other special logic functions can be integrated into the logic cells 3. The design of the links or gates occurs during the design process and is hardwired after chip integration.

More complex logic functions are realized according to the invention by means of a plurality or a combination of logic cells 3. For this to be possible, the logic cells 3 are designed to be coupled to each other. As in the case of known FPGA structures, in the case of the virtual FPGA structure 1 according to the invention this takes place via a linking matrix 6.

In Fig. 5 is a section of Fig. 3 can be seen. 5 shows, by way of example, the virtual linking matrix 6 used in the system 1 according to the invention for coupling a number of configurable elementary logic cells 3. In this schematic illustration, the wiring resources of the logic cells 3 are only partially shown; For reasons of clarity, only the two-bit inputs A, B of the adjacent logic cells 3 and their flexible interconnection via the linking matrix 6 have been shown. As in the case of the logic cells 3, in the case of the linking matrix 6, the inputs A, B are connected to the corresponding outputs via a programmable multiplexer structure-from the point of view of the linking matrix. By reconfiguration of the configuration register 4b, any interconnection of the inputs and outputs of the combination matrix 6 can take place, which leads to a flexible, time-adaptive coupling of logic cells 3. Like the configuration of the logic cells 3, the linking matrix 6 is also model-based and can be adapted to the requirements, in particular to the configurable logic cells 3, by parameterization in the design of the virtual FPGA 1. In addition, a heterogeneous virtual wiring structure can be realized, which enables optimized signal throughput behavior in different areas.

[0051] List of Reference Numerals

[0052] FIG. 1 system according to the invention

[0053] 2 functional module

3 logic cell / logic block

4 configuration register

4a configuration register logic cells

4b configuration register wiring resources

5 configuration interface

[0059] 6 linking matrix

7 memory cell

8 control unit

9 Maltiplexer

10 flip-flop / memory element

11 control unit / microprocessor

12 A / D converter

13 D / A converter

14 signal filters

[0068] 15 modem

[0069] 16 current control unit

17 input / output unit

18 function module 'link'

19 control / evaluation unit according to the prior art 24 data line 25 internal bus 26 control line

Claims

claims

1. System (1) for the flexible configuration of functional modules (2), wherein the

System (1) comprising the following components: a plurality of logic cells (3) in a hard-wired FPGA / standard ASIC structure, the logic cells (3) being configurable by means of configuration registers (4a) to perform elementary logic functions, a linking matrix ( 6) having a multiplicity of memory cells, via which different logical connections of the logic cells (3) in defined complex connections by means of the configuration registers (4a, 4b) are configurable, and a control unit (8) which controls the logic cells (3) and the logic matrix ( 6) is partially dynamically configured via an internal bus (25) and via the configuration registers (4a, 4b) by means of a configuration bit stream such that the hardwired FPGA / ASIC structure behaves functionally like a partially dynamically reconfigurable standard logic module.

2. System according to claim 1, wherein it is in the hard-wired FPGA / ASIC

Structure around a Fkrdcopy FPGA, an EASY Path, a Flash FPGA or an FPGA based on the AntiFuse Technology.

3. System according to claim 1, wherein a logic cell (3) from an n-bit look-up

Table structure consists, wherein the n inputs - in the case of n = 2, these two inputs A, B - via a multiplexer (9) select an associated configuration register (4a) and configure the desired elementary logic function.

4. System according to claim 1 or 3, wherein it is the configurable elementary logic function of a logic cell (3), for example, an AND, an OR, a NAND, NOR, ExOR or ExNOR linkage.

5. System according to claim 1, 3 or 4, wherein each logic cell (3) has a flip-flop

(10) and wherein at the output of the logic cell (3) the output signal (Q-FF) of the flip-flop (10) is available.

6. System according to claim 1 or 2, wherein it is in the dynamically reconfigurable function modules (2), for example, microprocessors

(11) or A / D converter (12) or D / A converter (13) with different bit resolution to different filter function filter (14) to different modems (15) for connection to different bus systems to different power control units (16) or different / Output units (17) acts.

7. System according to claim 1 or 6, wherein in addition to the areas of the dynamically reconfigurable function module (2) at least one static area (19) is provided in which at least one predetermined function module (20) is permanently configured.

The system of claim 7, wherein it is permanently configured

Function module (20), for example, to the microprocessor (11) with a predetermined bit resolution.

9. System according to claim 1, that it is in the system (1) to the measuring and

Control electronics of a field device for determining the monitoring of a physical or chemical process variable in the process automation is.

10. System according to claim 1 or 9, wherein the physical or chemical process variable is, for example, one of the following process variables: pressure, level, flow, turbidity, concentration of a chemical substance, viscosity, density, temperature, pH Value, conductivity.