Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/30098—Register arrangements
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/30003—Arrangements for executing specific machine instructions
  • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
  • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/30003—Arrangements for executing specific machine instructions
  • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
  • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/30098—Register arrangements
  • G06F9/30105—Register structure
  • G06F9/30109—Register structure having multiple operands in a single register
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/30098—Register arrangements
  • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
  • G06F9/30134—Register stacks; shift registers
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/30098—Register arrangements
  • G06F9/30141—Implementation provisions of register files, e.g. ports

Definitions

• the present application relates to programmable circuits, and more particularly to I/O circuitry with selectable data reordering for graphics.
• a vector processor or array processor is a CPU design that is able to run mathematical operations on multiple data elements simultaneously.
• a serial vector is a sequence of data held in registers that are processed by the same instruction. For example, a single instruction may cause four registers to be added to another four and the result written to a further four.
• a parallel vector holds several data items within the same register, each of which has the same instruction applied to it. Vector processing improves code density and allows optimizations that improve performance.
• a common problem suffered by vector processors is the need to organize data within the register file such that the same instruction may be applied to a series of registers.
• Register files generally only allow simultaneous access to a set of values aligned along a particular direction, i.e., along a row of the vector. Accordingly, a single instruction can access multiple values for a horizontal operation, but vertical operation requires either transposing the array being operated or performing separate access operations for each value in a different row. It is common to spend several instructions re-arranging data to make it suitable for vector processing and this overhead may obviate the benefits of using a vector.
• the inventions disclosed in the present application provide mechanisms to handle indirect register access without additional scoreboarding hardware, and can be further used to build a flexible FIFO access mechanism.
• the present application discloses a register file input/output configuration in which a variety of data transpositions are available at minimum power. Power is conserved by avoiding register-to-register data transfers; instead, the sequencer provides executable microinstructions which imply a variety of apparent data formats (as seen by the data channel), without unnecessary physical transfers of data.
• Various disclosed embodiments provide new ways for microprocessor register-files to be accessible, in multiple formats in order to reduce the number of program instructions required during byte, word and long word data refo ⁇ natting.
• the disclosed innovations in various embodiments, provide one or more of at least the following advantages:
• Figure 1 shows how four consecutive registers are viewed with byte- transpose enabled. Each row in the diagram represents one register as viewed by a program.
• Bvte-Transpose When Bvte-Transpose is enabled, the register file is effectively rotated by 90°, so that Register 0 contains all the low-bytes of the four registers, register 1 contains all the second-bytes of the four registers, and so on.
• Figure 2 shows how two consecutive registers are viewed with word- transpose enabled. Each row in the diagram represents one register as viewed by a program.
• Word-Transpose When Word-Transpose is enabled, the register file is effectively rotated by 90°, so that Register 0 contains all the low-words of the two registers, register 1 contains all the high-words of the two registers
• Figure 3 shows the data in register 0 being byte swapped in two different ways. The first is a full (DCBA) byte-swap, in which the original data-bytes are swapped within the entire 32-bit word, and the second shows a BADC byte-swap taking place, which swaps the bytes within each word.
• DCBA full byte-swap
• Figures 5a-5g are a set of related drawings.
• Figure 5a shows a sample hardware register configuration, in which the register is separated into multiple multiport RAMs, each having multiplexers connected to each of its data lanes.
• Figures 5b-5g show different states of operation of this register:
• Figure 5b shows the routing needed for a 32-bit word at address 0 without transpose;
• Figure 5c shows routing for address 1 without transpose;
• Figure 5d shows the routing needed for the first 32 bits of an eight bit transpose;
• Figure 5e shows the routing for the second 32 bits of an eight bit transpose;
• Figure 5f shows the routing for address 0 with a 16-bit transpose, in this sample implementation;
• Figure 5g shows routing for address 1 with a 16-bit transpose, in this sample implementation.
• the transposable register-file is a novel microprocessor register-file data organization scheme which overcomes many of the disadvantages of traditional data organization in microprocessor register-file, and which has the benefits of allowing a microprocessor register-file to be viewed in multiple formats with a reduction of the number of program instructions required during byte, word and long word data reformatting.
• the preferred embodiment supports both byte- transpose and word-transpose.
• Figure 1 shows how four consecutive registers are viewed with byte- transpose enabled.
• left hand side (110) illustrates those registers before transpose enabled
• right hand side (120) illustrates the same registers after transpose enabled.
• Each row in Figure 1 represents one register as viewed by a program.
• bottom row 211 shows Register 0 before transpose enabled.
• Each register in turn is composed of four bytes with the left most (for instance Oa) being the lowest byte and the right most (for instance Od) being the highest byte.
• Register 0 (121) contains all the low-bytes of the four registers
• Register 1 (122) contains all the second-bytes of die four registers, and so on.
• Word-transpose is similar to byte-transpose, except that the register data is rotated on a per word basis instead of per byte basis.
• Figure 2 shows how two consecutive registers are viewed with word-transpose enabled.
• left hand side (210) illustrates those registers before transpose enabled
• right hand side (220) illustrates the same registers after transpose enabled.
• Each row in Figure 2 represents one register as viewed by a program.
• bottom row (111) shows Register 0 before transpose enabled.
• Each register in turn is composed of two words with the left most (for instance Oa) being the low word and the right most (for instance Ob) being the high word.
• Oa the left most
• Ob for instance Ob
• the register file is effectively rotated by 90°, so that Register 0 (221) contains all the low-words of the four registers, Register 1 (222) contains all the high-words of the two registers.
• register-file byte-mapping and byte-masking functions add further flexibility to the novel microprocessor register-file data organization scheme.
• This feature of the disclosed inventions allows a program to arbitrarily reorganize the bytes within a register and has the benefits of further reduction of the number of program instructions required during byte, word and long word data reformatting.
• FIG. 3 shows two examples of byte- mapping on a register.
• left hand side (310) illustrates those registers before byte-mapping
• right hand side (320) illustrates the same registers after byte-mapping.
• Each row in Figure 3 represents one register as viewed by a program.
• bottom row (311) shows the Register before byte-mapping.
• Each register in turn is composed of four bytes with the left most (for instance Oa) being the lowest byte and the right most (for instance Ob) being the highest byte.
• the preferred embodiment supports both byte-mapping and byte-masking.
• Register-file byte masking is another novel microprocessor register-file data organization scheme that provides control over the bytes that are modified by an instruction in order to accelerate insertion of data into existing register.
• the program may specify a byte-mask both for source operands and destination operands. When byte-mask is specified for source operands, parts of a register may be forced to zero on input to an instruction. When byte mask is specified for destination operands, the result of an instruction can be written to parts of a destination register.
• the indirect register access has the benefits of providing indirect register access without additional scoreboarding hardware. It provides two types of instructions: one for moving data from one register to another register, and another for synchronization.
• the instruction format for moving data specifies the following parameters: a register that holds the source data, a register that holds either the destination register or the index of the destination register, and optionally a count of the number of registers to transfer. If the destination register is directly referenced in the instruction, those registers directly referenced in the instruction are scoreboarded when the instruction is executed. However, if the destination register is not directly referenced in the instruction, those registers indirectly referenced in the instruction are not scoreboarded when the instruction is executed and synchronization instruction will be used to ensure that the data in the register indirectly accessed is correct.
• a programmer uses a number of registers as scratchpad memory. Data is loaded into the scratchpad. If there is a switch from a direct to indirect access of register or vice versa, a synchronization instruction is issued to calculate an index into the scratchpad and the contents of the register at that index are copied into a known register. At this point all processing elements may use the same instruction to process data at the same register index. When the calculation is complete, the result may be copied back to the scratchpad and another synchronization instruction is issued to calculate the index.
• the invention allows the size of the FIFO (and thereby the number of reserved registers) to be changed under program control.
• Pixel data is often stored in what is called the RGB A8888 format, in which each pixel is made up of red, green, blue, and alpha components, each of 8 bits. All four components are packed into one 32-bit word for convenience of display.
• Sample assembler code for this algorithm is: mul tmp[0], src[0], src[3] mul tmp[l], src[l], src[3] mul tmp [2], src[2], src[3] add dst[0], tmp[0], dst[0] add dst[l), tmp [ 1 ] , dst[l] add dst[2], tmp [2], dst[2]
• the array indices refer to the byte position in the pixel.
• the code may be reduced if a parallel vector is used, but the alpha component must be repeated in each byte of a 32-bit register. This can be done using a byte swap mode: set byte swap mode for srcB to DDDD mul tmp, src, src reset byte swap mode for srcB to ABCD add dst, dst, tmp
• transpose srcA transpose srcB vector_3_mul tmp
• src src transpose dst vector_3_add dst, dst, tmp
• Transposing srcA causes all the red components to be in one register, all the green in another, and all the blue in a third.
• Transposing srcB causes all the alpha components to be in one register.
• Vector instruction of length three cause four pixels to be processed in 3 instructions (the stride of the srcB vector must be zero to use the same alpha value for each component).
• the register file is used for all storage within the processing element and holds a generous 256 registers, each 32-bits wide.
• the registers are perhaps more important to overall system performance than the ALU because they control the movement of data, and a SIMD array typically has high compute performance relative to data bandwidth.
• the register file can be large because it absorbs a number of FIFOs that would normally be needed to feed the ALU. All registers are preferably scoreboarded, so any instruction that attempts to read a register that has a write scheduled for it will stall until the write completes.
• the ALU may work on four 8-bit items at a time, or two 16-bit items, but the operation is always the same. This is similar to vector calculations, and when more than one item of data is held in a register it is referred to as a parallel vector (pvec as opposed to svec for vectors executed sequentially). Pvecs can boost performance if it is not too expensive to get data into an appropriate format.
• An example of using pvecs is to take four pixels of red, green, blue, and alpha, and re-group them such that common components are in the same register (so grouped as RRRR, GGGG, BBBB, AAAA).
• the register file supports zero-cost transposing for 8 or 16 bit pvecs. If the data type is 16 bits the register set is treated as being in pairs and the transposition takes place assuming two registers hold a 2x2 array of data. If the data type is 8 bits then four registers are assumed to hold a 4x4 array of data. Transposition is free because the register file is made up of four separate RAMs, which gives access to four different registers at the same time. The lower bits of the register address select the bytes to use, so registers to be transposed must be in sequential registers and must be aligned to the number of registers that will be transposed.
• Transposition also allows efficient memory access for 24 bit components. If data is stored byte-planar with four bytes of each component stored in the same 32 bit word the layout would be as shown in Figure 4. This is a useful way to store 24 bit data because there is no wastage but neither is there a difficult address calculation or nasty data shifting. In some algorithms it is convenient to process the components individually, but in others the whole pixel may be needed. Transposition allows this byte planar format to be converted into 32 bit pixels.
• the register file has, in principle, three read ports and two write ports. Two of the read ports are used by the ALU, as is one of the write ports. The remaining read and write ports are used to get memory data in and out of the registers. For best performance the RAM used to build the register file should have all five ports, but that will make it large. A compromise is possible in which one read and one write port are removed.
• the register file is made up of four separate RAMs for transposition, it is possible to arrange accesses to them so that while the ALU accesses one RAM another can be used for memory data.
• the vector operations result in the registers being accessed in a predictable pattern.
• the trick is to arrange the addressing so that memory accesses follow the same pattern as vector operations, but staggered so that they don't use the same RAM at the same time. This is not always possible when transposing because the ALU may need access to all four RAMs.
• the memory wins and the ALU stalls this is the cost of not having all 5 ports).
• Indirect register access allows the contents of one register to form the index to another. It is obviously useful for histograms, but also for FFT data shuffling and median filtering. It is difficult to implement because all PEs may access different registers, which breaks the SIMD model and requires additional scoreboarding hardware.
• the media processor imposes a slight restriction that avoids the hardware cost. Special instructions are used to copy data from one register to another; the register to copy from (or to) is specified in another register.
• the restriction is that while indirection is in use any register that may be indirectly accessed must not be used directly. This removes the need to Scoreboard the indirectly accessed register, while the directly accessed register is scoreboarded to ensure correct operation.
• the cost is an extra instruction per indirection. Details of Sample Hardware Implementation
• Figures 5a-5g are a set of related drawings, which collectively show a sample hardware implementation and its various operational modes.
• Figure 5a shows a sample hardware register configuration, in which the register is separated into multiple multiport RAMs 510, each having multiplexers 520 connected to each of its data lanes.
• RAMs may be connected to support transposing.
• Each RAM is 32 bits wide and shows four bytewide lanes.
• Each RAM holds every fourth entry in the register file.
• the dotted boxes are multiplexers that switch between the two inputs.
• the multiplexers can be, for example, simple by-8 circuits having two states, selected by a single control bit (per multiplexer). These control bits can be set, for example, by appropriate configuration instructions.
• Figures 5b-5g show different states of operation of this register. In these diagrams, only the active inputs to active multiplexers 520 are shown.
• Figure 5b shows the routing needed for a 32-bit word at address 0 without transpose, in this sample implementation.
• Figure 5c shows routing for address 1 without transpose, in this sample implementation.
• Figure 5d shows the routing needed for the first 32 bits of an eight bit transpose; the lower byte of each RAM is connected to a different byte lane, in this sample implementation.
• Figure 5e shows the routing for the second 32 bits of an eight bit transpose, in this sample implementation.
• Figure 5f shows the routing for address 0 with a 16-bit transpose, in this sample implementation.
• Figure 5g shows routing for address 1 with a 16-bit transpose, in this sample implementation.
• This hardware implementation can of course be varied, but this shows how an extremely versatile set of output reordering options can be achieved by multiplexing, WITHOUT unnecessary register-to-register transfers (which consume power).
• a method of selectably transposing data accessed in a register comprising the actions of: storing data in n memory segments, each having n data lanes at the output thereof; and selectably connecting each of n data bus segments to a respective one of said n 2 data lanes; whereby a desired data transposition is provided at the time of register access without register-to-register transfers.
• An electronic system comprising: a logic unit; and at least one I/O register, comprising multiple memory segments each holding a respective fraction of a data set, said data set being distributed across said segments in a consistent pattern, and each said memory segment providing multiple lanes of data path; and multiple multiplexers, each connected to connect a respective output bus segment to a respective data path of a respective one of said memory segments.
• the multiple access modes provided by the disclosed embodiments are particularly useful for graphics and image processing, they can also be especially useful for data which has internal 3-D or 4-D structure (e.g. a time series of voxel images).
• the capability for customized data transpositions can help with filtering and transformations.
• a flexible register can optionally implement some but not all of the transpositions described above, and/or can implement additional transpositions besides those listed.
• the disclosed hardware implementation uses byte-wide "lanes", but alternatively and less preferably a different fineness can be used. If fast nibble transpositions are desired, 8 RAMs could be used instead of four, with 8 lanes instead of four on each RAM, and 8 output busses instead of four. Note, however, that the number of multiplexers would quadruple if this were done.
• more logic can be added into the multiplexers if desired.
• the multiplexers can be given additional states wherein the 8-bit output is not only connected to a selected input (or none), but wherein the bits of the input can be permuted, pairwise exchanged, complemented, ANDed, etc. Additional control bits would preferably be routed to the multiplexers in such cases.

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• 2006
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