EP2074649A2

EP2074649A2 - A multi-transistor based non-volatile memory cell with dual threshold voltage

Info

Publication number: EP2074649A2
Application number: EP07826550A
Authority: EP
Inventors: Michiel Slotboom; Michiel J. Van Duuren; Nader Akil; Robertus T.F. VAN SCHAIJK; Almudena Huerta
Original assignee: NXP BV
Current assignee: NXP BV
Priority date: 2006-09-29
Filing date: 2007-09-26
Publication date: 2009-07-01
Also published as: WO2008038236A3; WO2008038236A2; CN101523580A

Abstract

A multi-transistor based non- volatile memory cell Ml arranged on a semiconductor substrate 1 includes at least one access transistor ATI; AT2; AT2'; AT2' and at least one memory transistor TM2a; TM2b; TM2c; TM2d. The at least one access transistor is a 'normally-off ' transistor and includes first and second diffusion regions Sl, S2, an access channel region Rl, and an access gate AG. The access channel region is intermediate the first and second diffusion regions. The at least one memory transistor includes third and fourth diffusion regions S2, S3, a channel region R2, a charge trapping element O1-N-O2 and a control gate CG. The channel region is intermediate the third and fourth diffusion regions, and the charge trapping element is above the channel region with the control gate being arranged above the charge trapping element. The semiconductor substrate is of a first conductivity type. The at least one memory transistor is provided with a memory threshold voltage window with an upper limit above and a lower limit below zero Volt.

Description

A MULTI-TRANSISTOR BASED NON- VOLATILE MEMORY CELL WITH

DUAL THRESHOLD VOLTAGE

FIELD OF THE INVENTION

The present invention relates to a multi-transistor based non- volatile memory cell and to a method for manufacturing such a non- volatile memory cell.

BACKGROUND OF THE INVENTION

Multi-transistor based non- volatile memory cells relate to non- volatile memory cells which comprise at least one access transistor and at least one memory transistor. An example is the well-known 2T non- volatile memory cell which consists of one access transistor in series with one memory transistor.

The access transistor comprises diffusion regions which can act as source or drain, an access channel region, and an access gate. The access channel region is arranged intermediate the diffusion regions of the access transistor. The memory transistor comprises diffusion regions which can act source or drain, a channel region, a charge trapping element and a control gate. The channel region is arranged intermediate the diffusion regions. The charge trapping element is located above the channel region and is arranged for storing electric charge. The control gate is arranged above the charge trapping element. Typically, the charge trapping element comprises a stack of layers comprising a first insulating layer, a charge storage layer and a second insulating layer in which the first insulating layer is arranged intermediate the channel region and the charge storage layer, and the second insulating layer is arranged intermediate the charge storage layer and the control gate.

Under control of the gate voltage of the memory transistor (i.e., the control gate voltage) the charge trapping element can be programmed and erased.

In SONOS (Semiconductor Oxide-Nitride-Oxide Semiconductor) memory cell devices, the charge trapping element comprises a stack of a bottom silicon dioxide layer, a charge trapping silicon nitride layer and a top silicon dioxide layer, also known as an ONO stack. In these non- volatile semiconductor devices having an ONO layer stack, programming, i.e., storing charge in the silicon nitride layer, is done by means of tunneling (either Fowler-Nordheim or direct tunneling) of electrons through the bottom silicon dioxide layer (tunnel-oxide layer) from the current carrying channel to the silicon nitride layer or alternatively by hot carrier injection.

Disadvantageously, an NMOS SONOS memory device (based on an n-type channel enhancement or "normally off transistor) suffers from read disturb and erase saturation, which can adversely affect the threshold voltage window of the SONOS memory device. The so-called erase saturation effect relates to erasure of charge (electrons) in the charge trapping layer which is done by tunneling of holes through the bottom insulating layer and the recombination of the tunneled holes with the electrons in the charge trapping layer, driven by a negative gate bias. During erasure, a parasitic electron current flowing from the gate through the top insulating layer to the nitride may be generated, and relatively large currents may flow through the bottom and top insulating layer, which can cause the bottom and top insulating layers to deteriorate. Moreover, this unwanted electron injection into the nitride counter-acts the erasing action of the injected holes, thus leading to a slowdown of the erasure process, generally known as "erase saturation". Due to the erase saturation, the threshold voltage of the memory cell after erasure is not as low as desired. Over the lifetime of the memory device, the repeated exposure to erase saturation creates defects (for instance deep traps) that accumulate in the insulating layers. As a consequence the level of the threshold voltage, which defines the memory state, or bit value, of the memory device (being either 'O' or ' 1 ', depending on the actual voltage of the memory device being below or above the threshold voltage) tends to increase gradually over the lifetime of the device. Clearly, the erase-induced change of the threshold voltage has an harmful effect on read actions of the memory device.

The read disturb effect relates to the application of a voltage (read voltage) on the control gate during reading of the memory transistor, in which the read voltage is between the threshold voltage for the erased state and the threshold voltage for the programmed state. Using such a read voltage value on the control gate causes a gradually change of the memory cell to the programmed state ("soft programming").

SUMMARY OF THE INVENTION It is an object of the present invention to provide a multi-transistor based nonvolatile memory cell in which the effects of erase saturation and read disturb are substantially reduced or avoided in comparison with the prior art.

This object is achieved by a multi-transistor based non-volatile memory cell arranged on a semiconductor substrate comprising: at least one access transistor and at least one memory transistor; the at least one access transistor comprising first and second diffusion regions, an access channel region, and an access gate, the access channel region being arranged intermediate the first and second diffusion regions; - the at least one memory transistor comprising third and fourth diffusion regions, a channel region, a charge trapping element and a control gate; the channel region being arranged intermediate the third and fourth diffusion regions, the charge trapping element being arranged above the channel region and being arranged for storing electric charge, the control gate being arranged above the charge trapping element; the semiconductor substrate having a first conductivity type; the at least one access transistor being a "normally-off ' transistor; the at least one memory transistor being provided with a memory threshold voltage window, the memory threshold voltage window having an upper limit above and a lower limit below zero Volt.

By using a memory transistor with the above characteristics of the memory threshold voltage window, advantageously the occurrence of erase saturation is prevented. Moreover, in the memory transistor, the read voltage level can be at (or close to) zero Volt, which advantageously avoids or strongly reduces the read disturb effect. In one aspect, the invention relates to a multi-transistor based non- volatile memory cell as described above, wherein the gate length of the memory transistor is shorter than the gate length of the access transistor.

In a second aspect, the invention relates to a multi-transistor based nonvolatile memory cell as described above, wherein only the access channel region of the access transistor comprises a threshold- voltage-adjustment implantation region of the first conductivity type.

In a third aspect, the invention relates to a multi-transistor based non- volatile memory cell as described above, wherein the memory transistor comprises a implantation zone of a second conductivity type in the channel region and the access transistor comprises an implantation zone of the first conductivity type in the access channel region, the second conductivity type being electrically opposite to the first conductivity type.

In a fourth aspect, the invention relates to a multi-transistor based non- volatile memory cell as described above, wherein the memory transistor comprises an implantation zone of the second conductivity type in the channel region, the access transistor comprises an implantation zone of the first conductivity type in the access channel region, the access gate is of the first conductivity type, and the control gate is of the first conductivity type.

Also, the present invention relates to a method for manufacturing a multi- transistor based non- volatile memory cell arranged on a semiconductor substrate comprising at least one access transistor and at least one memory transistor, comprising: providing the semiconductor substrate, the substrate being of a first conductivity type; providing the at least one access transistor, the at least one access transistor comprising first and second diffusion regions, an access channel region, and an access gate, the access channel region being arranged intermediate the first and second diffusion regions; providing the at least one memory transistor, the at least one memory transistor comprising third and fourth diffusion regions, a channel region, a charge trapping element and a control gate, the channel region being arranged intermediate the third and fourth diffusion regions, the charge trapping element being arranged above the channel region and being arranged for storing electric charge, the control gate being arranged above the charge trapping element; arranging the at least one access transistor to be a "normally-off ' transistor; arranging the at least one memory transistor to have a memory threshold voltage window, such that the memory threshold voltage window has an upper limit above and a lower limit below zero Volt.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be explained in more detail below with reference to drawings in which illustrative embodiments of the invention are shown.

Fig. 1 shows an example diagram of a measurement of the threshold voltage transient during programming and erasing;

Fig. 2 shows a cross-section of a 2-transistor non- volatile memory cell according to a first embodiment of the present invention; Fig. 3 shows an example diagram of a measurement of threshold- voltage as a function of transistor gate length;

Fig. 4 shows a cross-section of a 2-transistor non- volatile memory cell according to a second embodiment; Fig. 5 shows a cross-section of the 2-transistor non-volatile memory cell of

Fig. 4 during a manufacturing step;

Fig. 6 shows a cross-section of the 2-transistor non-volatile memory cell of Fig. 4 during a next manufacturing step;

Fig. 7 shows a cross-section of the 2-transistor non-volatile memory cell of Fig. 4 during a subsequent manufacturing step;

Fig. 8 shows a cross-section of the 2-transistor non-volatile memory cell of Fig. 4 during a further manufacturing step;

Fig. 9 shows a cross-section of the 2-transistor non-volatile memory cell of Fig. 4 during a still further manufacturing step; Fig. 10 shows a cross-section of a 2-transistor non- volatile memory cell according to a third embodiment;

Fig. 11 shows a cross-section of the 2-transistor non-volatile memory cell of Fig. 10 during a manufacturing step, and

Fig. 12 shows a cross-section of a 2-transistor non-volatile memory cell according to a fourth embodiment.

DETAILED DESCRIPTION

The non- volatile memory cell according to the present invention provides a dual threshold voltage, i.e., the at least one access transistor is provided with a threshold voltage window corresponding to that of an enhancement-type transistor, while the at least one memory transistor is provided with a natural threshold voltage that differs from that of the access transistor and results in a threshold window that has an upper limit above and a lower limit below zero Volt. Fig. 1 illustrates the measured threshold voltage transients during programming and erasing of a first type SONOS based memory transistor and of a second type SONOS based memory transistor, respectively as a function of time. These graphs are generally referred to as "program and erase characteristics". The differences between the first and second type of memory transistors are in the gate material and the channel doping. The first type has an n-type poly silicon gate and a channel doping resulting in a positive neutral V_T (enhancement or "normally off transistor) whereas the second type has a p-type poly silicon gate and a channel doping resulting in a negative neutral V_T (depletion or "normally- on" transistor). The first type SONOS based memory transistor has characteristics typical for an enhancement-type transistor with a threshold voltage window as shown in the upper part of the graph by curves VPl and VEl. Curve VPl depicts the threshold voltage for programming and curve VEl depicts the threshold voltage for erasure as a function of time. In this first type transistor a relatively high read voltage VRl is required for detecting the state of the charge trapping element of the first type memory transistor (for instance, VRl could be in between VPl and VEl at t= 10⁴ s. Note that VPl and VEl may have been determined at a start of the measurement, t = 0).

Typically, the window (difference between VEl and VPl) is determined by a combination of the program/erase voltage and the duration of its application. In general, a larger program/erase voltage results in a larger window. Similarly, a longer duration of a program or erase operation typically results in a larger window. Typically, the duration of a program operation is between about 1 and about 10 ms, while the duration of an erase operation is between about 10 and about 100 ms. In the example shown in Fig. 1, the first type transistor would thus have a threshold voltage after programming of about 3.8 Volt (at 10 ms) and a threshold voltage of about 0.4 Volt after erasing (at 100 ms). In this case, a suitable read voltage VR is between 2 and 2.5 Volt.

The second type SONOS based memory transistor typically has a threshold voltage window as shown in the lower part of the graph by curves VP2 and VE2. Curve VP2 depicts the threshold voltage for programming and curve VE2 depicts the threshold voltage for erasure as a function of time. In comparison to the first type memory transistor, the second type memory transistor has a threshold voltage window around a threshold voltage V_T at (or close to) zero Volt, the threshold voltage for erase VE2 as a function of time decreases continuously and at a given point even becomes negative with much less saturation than for the first type transistor as described above. The lower threshold voltages in the second type memory transistor is caused by the different channel implants, causing depletion ("normally- on") behavior instead of enhancement ("normally-off ') behavior. The reduction of the saturation effect in the erase characteristic VE2 (compared to VEl) is caused by the use of a p-type poly-silicon gate instead of an n-type gate. By using a memory transistor with characteristics of the second type memory transistor as discussed here, advantageously the occurrence of erase saturation is prevented. In the second type memory transistor, the read voltage level VR2 can be at (or close to) zero Volt, which advantageously avoids or strongly reduces the read disturb effect. Obviously, in a multi-transistor based SONOS memory cell which comprises at least one second type memory transistor TD and at least one access transistor, the at least one access transistor should be an enhancement-type transistor to warrant bit selectivity (in an array) and safety against punch-through.

To obtain a memory transistor with characteristics VP2, VE2, VR2 as shown in the lower part of Fig. 1 in combination with an enhancement type access transistor the present invention can be embodied in various ways, as will be described below in more detail.

Fig. 2 shows a cross-section of a 2-transistor non- volatile memory cell according to a first embodiment of the present invention. The non-volatile memory cell Ml shown in Fig. 2, comprises two transistors, an access transistor ATI and a memory transistor TM2a of the second type as described above with respect to Fig. 1.

On a semiconductor substrate 1 , first, second and third diffusion regions S 1 , S2 and S3 are arranged which may serve as source and/or drain regions. On a first channel region Rl of the semiconductor substrate between the first and second diffusion regions Sl, S2, the access transistor ATI is located. The access transistor comprises a first gate oxide Gl, which is arranged on the surface of the first channel region Rl between diffusion regions Sl and S2, an access gate AG which is located above the first gate oxide Gl, and spacers SP which form insulating sidewalls of the access transistor ATI.

On a second channel region R2 of the semiconductor substrate between a third and fourth diffusion regions S2, S3, the non-volatile memory transistor of the second type TM2a is located. Note that the third diffusion region of the memory transistor is in common with the second diffusion region of the access transistor. The memory transistor TM2a comprises a charge trapping element, which comprises on the surface of the second semiconductor region R2 between diffusion regions S2 and S3, a stack of a first insulating layer 01, a charge storage layer N and a second insulating layer 02. Above the charge trapping element, a control gate CG is located. In the stack the first insulating layer Ol is arranged intermediate the second channel region R2 and the charge storage layer N, and the second insulating layer 02 is arranged intermediate the charge storage layer N and the control gate CG.

Typically, the charge trapping element can consist of an ONO stack, in which the first insulating layer Ol comprises silicon dioxide, the charge storage layer N consists of silicon nitride and the second insulating layer 02 comprises silicon dioxide.

It is noted that the skilled person will appreciate that various other alternative charge trapping stacks may exist. The bottom and/or top silicon dioxide layer may alternatively comprise an high K material. Such high K materials comprise hafnium silicate (optionally nitrided), zirconium silicate, hafnium oxide, zirconium oxide, tantalum oxide, aluminium oxide. Also, the charge trapping silicon nitride layer may be replaced by for example a layer of silicon nano-crystals.

Spacers SP are arranged to form insulating sidewalls of the memory transistor TM2a. The outer two diffusion regions Sl, S3, the access gate AG as well as the control gate CG of the non- volatile memory transistor TM2a are typically provided with a respective electrical contact. For reason of clarity of the drawing such contacts are not shown here.

In the first semiconductor region Rl a first channel region is located which during operation of the non- volatile memory cell Ml is capable of conducting a current. The first channel has a first channel length Ll. Similarly, in the second semiconductor region R2 a second channel region is located. The second channel region has a second channel length L2.

In the semiconductor substrate 1 a p-well region PW, an anti-punch-through region APT and threshold voltage adjust regions are present. The p-well region PW is located at the relatively deepest location in the semiconductor substrate 1 , the anti-punch-through region APT is located above the p-well region PW, but below the diffusion regions Sl, S2, S3. The threshold voltage adjust regions are located substantially in the channel regions Rl and R2. In addition to these implants, other implants may be present as well (for instance a buried N-well below the P-well).

In the first embodiment the second channel length L2 is shorter than the first channel length Ll. As will be explained with reference to Fig. 3, the threshold voltage levels of a (memory) transistor depend on the channel length of that transistor. Fig. 3 shows an example diagram of threshold- voltage as a function of transistor gate length for individual transistors with various gate lengths.

The threshold voltage of a transistor is dependent on the gate length GL; Ll; L2. The threshold voltage decreases for shorter gate length. Due to shorter distance between the diffusion regions, the voltage on the gate that is required to create an inversion zone under the gate, is reduced. This effect is known as V_T roll-off. Normally, this effect is counteracted by implantation of p-type halos or pockets below the channel region. In this embodiment of the present invention, halo or pocket implantations are omitted for the memory transistor TM2a and only created in the channel region Rl of the access transistor ATI . Alternatively, the halo or pocket implantations may also be omitted in the channel region Rl of the access transistor ATI, in which case a suitable gate length of the access transistor ATI can cause the threshold voltage of the access transistor ATI to have a comparatively high value.

The memory transistor TM2a is arranged to have a shorter gate length L2 than a gate length Ll of the access transistor ATI .

It is noted that the channel length Ll of the access transistor ATI is hardly scalable due to the fact that the access transistor has to be safe for punch through (for example with a gate oxide thickness of at least 6 nm, it must be capable of withstanding an inhibit voltage of about 5 Volt) and for bit selectivity. For this reason the channel length Ll of the access transistor needs to be of the order of 0.2μm. The requirement for the memory transistor TM2a is less stringent since it is only required that a clear modulation of the read current (i.e., the current in the second channel region R2 when the read voltage VR2 is applied) with respect to a ' 1 ' and a '0' bit value can be obtained. From Fig. 3 it can be seen that for the example technology shown here, the threshold voltage difference between a first gate length Ll of 0.24 μm and a second gate length L2 of 0.18 μm already is about 200 mV. The threshold voltage difference can become larger for more advanced generations with shorter second gate length L2, due to the fact that the difference between the first and second gate length increases ( i.e., L2 scales down from one device generation to a next one, while Ll remains virtually equal, or at least scales down at a much slower pace). A memory transistor TM2a with a threshold voltage window centered around zero Volt can thus be created next to an enhancement-type access transistor ATI with enhancement-type threshold voltage level.

Figs. 4a and 4b each show a cross-section of a 2-transistor non- volatile memory cell according to a second embodiment. In the second embodiment, a non-volatile memory cell M2 comprises two transistors, an access transistor AT2 and a memory transistor TM2b of the second type as described above with respect to Fig. 1. In Figs. 4a and 4b entities with the same reference number refer to the same entities as shown in the preceding Figures. To obtain a difference in threshold voltage between the access transistor AT2 and the memory transistor TM2b, a V_T adjust process is carried out during manufacturing of these transistors AT2, TM2b in such a way that a local V_T adjust implantation VAR is carried out in the channel region Rl of the access transistor AT2. This implantation layer is not present under the memory transistor TM2b. By this procedure, the threshold voltage window of the memory transistor

TM2b is around zero Volt, the threshold voltage window of the access transistor AT2 is such that the access transistor AT2 is an enhancement-type transistor. The manufacturing process for the non- volatile memory cell M2 according to the second embodiment will be explained with reference to Figs. 5 - 9. In the semiconductor substrate 1 a p-well region PW, an anti-punch-through region APT and threshold voltage adjust regions are present. The p-well region PW is located at the relatively deepest location in the semiconductor substrate 1 , the anti-punch-through region APT is located above the p-well region PW, but below the diffusion regions Sl, S2, S3. The threshold voltage adjust regions are located in the channel regions Rl and R2. In Fig. 4a the APT region is located substantially below the access transistor

AT2. In Fig. 4b the APT region is located under the access transistor AT2 and the memory transistor TM2b. By omitting the formation of the APT region below the memory transistor TM2b, the threshold voltage of the control gate can be further reduced, although this may affect the short channel behavior of the memory transistor TM2b. This trade-off may be acceptable in some cases as will be appreciated by the skilled person.

Fig. 5 shows a cross-section of the 2-transistor non-volatile memory cell of Fig. 4a or Fig. 4b during a manufacturing step.

In an initial manufacturing step, the first insulating layer Ol is deposited or grown on the semiconductor substrate 1. Next, the charge trapping layer N is deposited on the first insulating layer 01. Then, the second insulating layer 02 is deposited.

It is noted that in a preceding step a blanket ion-implantation process may be carried out to create the p-well region PW in the substrate 1 for both access transistor AT2 and memory transistor TM2b. In case of the embodiment shown in Fig. 4a, also a blanket ion- implantation process to create the APT region (not shown here) for both access transistor AT2 and memory transistor TM2b was carried in a step preceding the step shown in Fig. 5.

Fig. 6 shows a cross-section of the 2-transistor non-volatile memory cell of Fig. 4 during a next manufacturing step.

In this manufacturing step, a mask layer ML is created on top of the stack of the first insulating layer 01, the charge trapping layer N and the second insulating layer 02 that was formed in a preceding step. The mask layer ML is patterned in such a way that it covers at least a region where at a later stage the memory transistor TM2b will be formed. At the region where the access transistor AT2 is to be formed, the mask layer ML is removed by means of a standard lithographic process.

Next, an etching process is carried out to remove portions of the second insulating layer 02 and the charge trapping layer N that are not covered by the mask layer ML. Fig. 7 shows a cross-section of the 2-transistor non- volatile memory cell of

Fig. 4 during a subsequent manufacturing step.

In this step, an ion-implantation process Qp is carried out to implant p-type species (such as boron (B), indium (In)) in the region Rp of the semiconductor substrate 1 that is not covered by the mask layer ML. In case of Fig. 4b, preceding or directly after this step, an ion-implantation step is carried out for creating a local APT region (not shown here) only below the open substrate 1 by using the mask layer ML.

Fig. 8 shows a cross-section of the 2-transistor non-volatile memory cell of Figs. 4a or 4b during a further manufacturing step.

First, the mask layer ML is removed. Next, the first insulating layer Ol is optionally removed in part or completely by etching. (Removal of Ol may be considered for reason of quality of the oxide or controllability of the thickness of the access gate oxide). Next, an oxidation process is carried out to form a silicon-dioxide layer G in the surface of the substrate. During the oxidation process the charge trapping layer N serves as a hard mask to prevent further oxidation of the tunnel oxide Ol beneath. Preferably, the oxidation process is a so-called dry oxidation process, which does not adversely affect the charge trapping layer N by re-oxidation of the nitride.

The silicon dioxide layer G will be used as gate oxide layer for the access transistor AT2 to be formed. It is noted that due to the high temperature of the substrate during the oxidation process some redistribution of the implanted p-type species may occur.

Fig. 9 shows a cross-section of the 2-transistor non-volatile memory cell of Figs. 4a or 4b during a still further manufacturing step. In this step, a poly-Si layer 2 is deposited over the structure as shown in Fig. 8.

Poly-Si layer 2 can either be un-doped, doped with n-type impurity or doped with p-type impurity. If needed, the poly layer can be provided with a capping layer (not shown) of for instance silicon oxide or silicon nitride.

If needed, the poly-Si layer 2 may be planarised. Next, a mask layer is deposited on the poly-Si layer 2 and subsequently patterned. A first mask portion MTl is located over the region where the access transistor AT2 is to be formed. A second mask portion MT2 is located over the region where the memory transistor TM2b is to be formed.

Then, an etching process is carried out to remove the poly-Si layer and ONO stack outside of the first and second mask portion MTl, MT2. The masked portion of the poly-Si layer that remains under the first mask portion MTl will form the access gate AG of the access transistor AT2. The masked portion of the poly-Si layer and ONO stack that remains under the second mask portion MT2 will form the control gate CG and charge trapping element respectively of the memory transistor TM2b. After removal of the mask portions MTl, MT2, spacers SP are formed on the sidewalls of the masked portions of the poly-Si layer 2 and the ONO stack.

The structure M2, resulting from the aforementioned steps is shown in Fig. 4a or Fig. 4b (depending on the shape of the APT region).

Fig. 10 shows a cross-section of a 2-transistor non- volatile memory cell according to a third embodiment.

In the third embodiment, a non- volatile memory cell M2 comprises two transistors, an access transistor AT2' and a memory transistor TM2c of the second type as described above with respect to Fig. 1. In Fig. 10 entities with the same reference number refer to the same entities as shown in the preceding Figures. The channel region R2 of the memory transistor TM2c comprises an implant region DR, to make the memory transistor TM2b a depletion-type (= "normally on") transistor. In case of an NMOS transistor in the p-type substrate an implant region DR is formed by n-type ion-implantation. For example, arsenic (As) is used as n-type impurity species in the n-type implant region DR. Preferably, the ion-implantation process for creating the implant region DR is carried out as a blanket process in which the regions of the surface where the access transistor and the memory transistor are to be created, are both exposed to the n-type implantation ion beam. Due to exposing the access transistor region where the access transistor AT2' is to be created, to the n-type implantation ion beam, the access transistor region would also comprise a depletion-type Vτ-adjust implant and the access transistor AT2' would be a depletion-type transistor. However, to obtain an enhancement-type access transistor AT2', a p-type compensation ion-implantation process is performed in the region where the access transistor is to be created. After the compensation ion- implantation process, the region where the channel region Rl of the access transistor AT2' is to be formed, comprises a p-type compensation region OV, in which an excess amount p-type impurity species is located in such a way that the n-type impurity species DR in channel region Rl is over-compensated. As a result, the channel region Rl acts as a p-type impurity region. The way to apply this selective Vt adjust implant OV only under the access gate AG is similar to the approach followed in the previous embodiment.

Figs. 11a, l ib l ie and 1 Id show a cross-section of the 2-transistor nonvolatile memory cell of Fig. 10 during a manufacturing step.

The manufacturing process of the 2-transistor non- volatile memory device according to the third embodiment is to a large extent similar to that of the device according to the second embodiment.

In Fig. 11a, first, a blanket ion- implantation process is performed defining p- well region PW, APT (anti-punch-through) implants APT and n-type Vτ-adjust implant region DR. Besides, other implant can be present as well, for instance a buried N- well. Then, as shown in Fig. 1 Ib, the ONO stack 01, N, 02 is created on the surface of the semiconductor substrate. A mask layer ML is deposited on the ONO stack 01, N, 02 and patterned. Using the patterned mask layer ML, the ONO stack is removed in the region where the access transistor is to be created. Next, a p-type compensation implant process is performed in the region where the access transistor is to be created. After the compensation implant process, the region where the channel region Rl of the access transistor AT2' is to be formed, comprises a p-type compensation region OV, in which an excess amount p-type impurity species is located in such a way that the n-type impurity species DR in channel region Rl is over-compensated. As a result, the channel region Rl acts as a p-type impurity region. Alternatively, as described with reference to Figs, l ie and 1 Id, the APT region can be formed in such a way that the APT region is located only below the region where the access transistor is to be formed.

In Fig. l ie, first, a blanket ion- implantation process is performed defining p- well region PW, and n-type implant region DR.

Then, as shown in Fig. 1 Id, the ONO stack 01, N, 02 is created on the surface of the semiconductor substrate. A mask layer ML is deposited on the ONO stack 01, N, 02 and patterned. Using the patterned mask layer ML, the ONO stack is removed in the region where the access transistor is to be created. Next, an ion-implantation process is performed in the region where the access transistor is to be formed to create a local APT region. Then, a p- type compensation ion-implantation process is performed in the region where the access transistor is to be created. Alternatively, the order of the APT and compensation implants can be swapped. After the compensation ion- implantation process, the region where the channel region Rl of the access transistor AT2' is to be formed, comprises a p-type compensation region OV, in which an excess amount p-type impurity species is located in such a way that the n-type impurity species DR in channel region Rl is over-compensated. As a result, the channel region Rl acts as a p-type impurity region.

As p-type impurity species for example Boron (B) or Indium (In) may be used.

The further course of the manufacturing of the 2-transistor non- volatile memory device is illustrated by processes similar to those shown in Figs. 7-9.

In this third embodiment, the access gate AG and control gate CG are gates consisting of an un-doped material or an n-type material such as n-doped poly-Si.

Fig. 12 shows a cross-section of a 2-transistor non-volatile memory cell M2' according to a fourth embodiment. In the fourth embodiment, the non- volatile memory cell M2' has a layout similar to the non- volatile memory cell according to the third embodiment as shown in Fig. 10, comprising an access transistor AT2" and a memory transistor TM2d of the second type as described above.

In the fourth embodiment, the access gate AG of the access transistor AT2" and the control gate CG of the memory transistor TM2d are p-type gates consisting of a p- type material such as p-doped poly-Si. As already discussed with reference to Fig. 1, the use of p-type gates is beneficial in the sense that it reduces the erase saturation.

However, by creating a p-type access gate AG, the threshold voltage window of the access transistor AT2" is increased by about +1 Volt in comparison to an n-type access gate. Advantageously, this increase of the threshold voltage window relaxes the requirement for over-compensating the blanket n-type ion implantation (as described above with reference to Figs. 10 and 11) by a p-type ion implantation. In comparison to the third embodiment, the concentration of the p-type ion in the p-type compensation region RE can be reduced in this fourth embodiment.

Due to the application of the p-type control gate CG instead of an n-type control gate, the erase saturation phenomenon is counteracted, but at the same time the threshold window of the memory transistor TM2d increases by about +1 Volt (compared to the n-type control gate). As a result, the threshold voltage for erasure of the memory transistor TM2d can be at a substantially similar level than the threshold for erasure of an n- type memory transistor as described above; the threshold voltage window can still be roughly centered around zero Volt. If needed, the depletion-type V_T implantation can be adapted to fine-tune the position of the V_T window.

In addition, it is noted that the multi-transistor based non- volatile memory cell is not limited to memory cells that comprise a SONOS memory cell. Alternatively, the charge storage element may be a floating gate element, a high-K material/silicon nitride/silicon dioxide stack, a high-K material/silicon nitride/high-K material stack, a silicon dioxide/high- K material/silicon dioxide stack, a nano-dot element or an NROM element. Note that instead of the charge trapping silicon nitride layer an alternative charge trapping material may be used.

Also, it is noted that the multi-transistor based memory cell as described above can be implemented in various memory array configurations, such as NAND, NOR, AND, 2T and virtual ground type memory arrays.

It will be appreciated by the person skilled in the art that other alternative and equivalent embodiments of the invention can be conceived and reduced to practice without departing from the true spirit of the invention, the scope of the invention being limited only by the appended claims.

Claims

CLAIMS:

1. A multi-transistor based non- volatile memory cell (Ml) arranged on a semiconductor substrate (1) comprising: at least one access transistor (ATI; AT2; AT2'; AT2") and at least one memory transistor (TM2a; TM2b; TM2c; TM2d); - the at least one access transistor comprising first and second diffusion regions

(Sl, S2), an access channel region (Rl), and an access gate (AG), the access channel region being arranged intermediate the first and second diffusion regions; the at least one memory transistor comprising third and fourth diffusion regions (S2, S3), a channel region (R2), a charge trapping element (Ol-N-02) and a control gate (CG); the channel region being arranged intermediate the third and fourth diffusion regions, the charge trapping element being arranged above the channel region and being arranged for storing electric charge, the control gate being arranged above the charge trapping element; - the semiconductor substrate being of a first conductivity type; the at least one access transistor being a "normally-off ' transistor; the at least one memory transistor being provided with a memory threshold voltage window, the memory threshold voltage window having an upper limit above and a lower limit below zero Volt.

2. A multi-transistor based non- volatile memory cell according to claim 1, wherein the gate length (L2) of the memory transistor (TM2a) is shorter than the gate length (Ll) of the access transistor (ATI).

3. A multi-transistor based non- volatile memory cell according to claim 1, wherein only the access channel region (Rl) of the access transistor (AT2) comprises a threshold- voltage-adjustment implantation region (VAR) of the first conductivity type.

4. A multi-transistor based non- volatile memory cell according to claim 1, wherein the memory transistor (TM2c) comprises a implantation zone (DR) of a second conductivity type in the channel region (R2) and the access transistor (AT2') comprises an implantation zone (DR+OV) of the first conductivity type in the access channel region (Rl), the second conductivity type being electrically opposite to the first conductivity type.

5. A multi-transistor based non- volatile memory cell according to claim 3 or 4, wherein the access gate is a gate of the second conductivity type comprising material of the second conductivity type.

6. A multi-transistor based non- volatile memory cell according to claim 3 or 4 or

5, wherein the control gate is a gate of the second conductivity type comprising material of the second conductivity type.

7. A multi-transistor based non- volatile memory cell according to claim 1, wherein the memory transistor (TM2d) comprises an implantation zone (DR) of the second conductivity type in the channel region (R2), the access transistor (AT2") comprises an implantation zone (DR+OV) of the first conductivity type in the access channel region (Rl), the access gate is of the first conductivity type, and the control gate is of the first conductivity type.

8. A multi-transistor based non- volatile memory cell according to any one of the preceding claims, wherein the first conductivity type is p-type and the second conductivity type is n-type.

9. A multi-transistor based non- volatile memory cell according to any one of the preceding claims, wherein the first conductivity type is n-type and the second conductivity type is p-type.

10. A multi-transistor based non- volatile memory cell according to claim 3 or 4 or

6, wherein an anti-punch-through implantation region (APT) is located only below the access transistor (AT2; AT2'; AT2").

11. A multi-transistor based non- volatile memory cell according to claim 1 , wherein the charge trapping element is one of a floating gate element, a silicon dioxide/silicon nitride/silicon dioxide stack, a high-K material/silicon nitride/silicon dioxide stack, a high-K material/silicon nitride/high-K material stack, a silicon dioxide/high-K material/silicon dioxide stack and a nano-dot element.

12. A memory array comprising at least one multi-transistor based non- volatile memory cell (Ml), the multi-transistor based non-volatile memory cell arranged on a semiconductor surface (1) comprising: - at least one access transistor (ATI; AT2; AT2'; AT2") and at least one memory transistor (TM2a; TM2b; TM2c; TM2d); the at least one access transistor comprising first and second diffusion regions (Sl, S2), an access channel region (Rl), and an access gate (AG), the at least one access channel region being arranged intermediate the first and second diffusion regions; - the at least one memory transistor comprising third and fourth diffusion regions (S2, S3), a channel region (R2), a charge trapping element (Ol-N-02) and a control gate (CG); the channel region being arranged intermediate the third and fourth diffusion regions, the charge trapping element being arranged above the channel region and being arranged for storing electric charge, the control gate being arranged above the charge trapping element; the semiconductor substrate being of a first conductivity type; the at least one access transistor being a "normally-off ' transistor; the at least one memory transistor being provided with a memory threshold voltage window, the memory threshold voltage window having an upper limit above and a lower limit below zero Volt.

13. Memory array according to claim 12, wherein the memory array is one of the NAND, 2T, NOR, AND, and virtual ground type.

14. Semiconductor device comprising at least one multi-transistor based nonvolatile memory cell according to claim 1.

15. Method for manufacturing a multi-transistor based non- volatile memory cell

(Ml) arranged on a semiconductor substrate (1) comprising at least one access transistor (ATI; AT2; AT2'; AT2") and at least one memory transistor (TM2a; TM2b; TM2c; TM2d), comprising: - providing the semiconductor substrate, the substrate being of a first conductivity type; providing the at least one access transistor, the at least one access transistor comprising first and second diffusion regions (Sl, S2), an access channel region (R2), and an access gate (AG), the access channel region being arranged intermediate the first and second diffusion regions; providing the at least one memory transistor, the at least one memory transistor comprising third and fourth diffusion regions (S2, S3), a channel region (R2), a charge trapping element (Ol-N-02) and a control gate (CG), the channel region being arranged intermediate the third and fourth diffusion regions, the charge trapping element being arranged above the channel region and being arranged for storing electric charge, the control gate being arranged above the charge trapping element; arranging the at least one access transistor to be a "normally-off ' transistor; arranging the at least one memory transistor to have a memory threshold voltage window, such that the memory threshold voltage window has an upper limit above and a lower limit below zero Volt.