EP2067286A2

EP2067286A2 - Apparatus and method for de-serialisation of data stream

Info

Publication number: EP2067286A2
Application number: EP06794611A
Authority: EP
Inventors: Graham Butler
Original assignee: Telefonaktiebolaget LM Ericsson AB
Current assignee: Telefonaktiebolaget LM Ericsson AB
Priority date: 2006-09-29
Filing date: 2006-09-29
Publication date: 2009-06-10
Also published as: WO2008037944A2; WO2008037944A3

Abstract

An apparatus (100) for de-serialisation of a framed data stream, each frame being M-bits long and comprising a fixed frame alignment word, said apparatus comprising one first-order K:1 down-converter (102), K second-order L:1 down-converters (104-110), each connected to one of the outputs of the first-order down-converter and K slice aligners (112-118), each connected to outputs of the second-order down-converters (104-110). The apparatus further comprises a combiner (120) for combining all data streams from the slice aligners (112-118) into one data stream of width of K⋅L bits, wherein M is divisible by K⋅L and said first-order down converter (102) is adapted to form K different alignment slices from the frame alignment word by taking every Kth bit of said frame alignment word, wherein each of the slice aligners searches for one of the K alignment slices in the received data stream and generates a marker indicating a bit sequence in the data stream that matches the sought alignment slice. The combiner (120) assembles the contiguous K⋅L bit wide data stream if within two adjacent clock cycles all K slice aligners generate said markers for K different alignment slices.

Description

APPARATUS AND METHOD FOR DE-SERIALISATION OF DATA STREAM

Field of the Invention ' The present invention relates in general to digital data communication systems, and in particular, to a method and a device for detecting repetitive patterns in deserialised data stream.

Background of the Invention Modern communication systems often process serial data streams that are too fast to handle at their native bit rate. Receivers of such streams often employ a de-serialisation process to convert this high-speed serial data into a parallel stream at a reduced sampling rate. This first "down conversion" is often sufficient to get the data into a processing device (ASIC, FPGA) but still has a sampling rate, which is too high to allow complex operations to be performed on it.

A disadvantage of the solutions known in the art is that they require additional hardware, external to the processing device, which provides a training pattern injection mechanism, which allows for synchronisation of the receiver with the transmitter of the data. Such hardware has to operate at particularly high speeds and therefore adds significant cost and complexity to the system.

Hence, an improved apparatus and method would be advantageous and in particular one that can synchronise receiver of the de-serialised data with the transmitter without the complex external hardware.

Summary of the Invention

Accordingly, the invention seeks to preferably mitigate, alleviate or eliminate one or more of the disadvantages mentioned above singly or in any combination. Solution according to the present invention requires two hierarchical levels of de-serialisation, which present a unique and difficult problem: that of sorting out the chronological bit order of the final parallel samples.

According to a first aspect of the present invention there is provided an apparatus for de-serialisation of a framed data stream as defined in claim 1.

According to the first aspect of the present invention the apparatus for deserialisation of a framed data stream, each frame being M-bits long and comprising a fixed frame alignment word, comprises one first-order K: 1 down-converter for splitting received data stream into K data streams and K second-order L:l down-converters, each one for splitting received data stream into L data streams. Each of said K second-order L:l down-converters is connected to one of the outputs of the first-order K:l down- converter. The apparatus also comprises K slice aligners, each connected to outputs of one of the second-order L:l down-converters. The apparatus further comprises a combiner for combining all data streams from the slice aligners into one contiguous data stream of width of K-L bits, wherein M is divisible by K-L. Said first-order down- converter is adapted to form K different alignment slices from the frame alignment word by taking every K¹ bit of said frame alignment word, wherein each of the slice aligners is adapted to search for one of the K alignment slices in the received data stream. Each of the slice aligners is also adapted to generate a marker indicating a bit sequence in the data stream that matches the sought alignment slice and the combiner is adapted to assemble the contiguous K-L-bit wide data stream if within two adjacent clock cycles all K slice aligners generated said markers for K different alignment slices.

Preferably, in data streams in which each frame further comprises a multi-frame alignment word and said multi-frame alignment word is adapted to change its value periodically in accordance with a predefined algorithm, said first order down-converter of the apparatus is adapted to add to every of said K alignment slices at least one bit taken from the multi-frame alignment word. Said first order down-converter is adapted to take every K^th bit from said multi-frame alignment word in order to add said at least one bit to said alignment slice, and said slice aligners are adapted to check if the bits added to the K alignment slices change their values in accordance with said predefined algorithm.

According to a second aspect of the present invention there is provided a method of de-serialisation of a framed data stream as defined in claim 16.

According to the second aspect of the present invention the method of de- serialisation of a framed data stream, each frame being M-bits long and comprising a fixed frame alignment word, comprises the following steps:

- a first-order down-converting of the input data stream to K first-order data streams and said first-order down converting includes forming K different alignment slices from the frame alignment word by taking every K^th bit of said frame alignment word;

- a second-order down-converting in which each one of the K first-order data streams is down-converted to L second-order data streams;

- transmitting the second order data streams from the K second-order down- converters to K slice aligners, wherein one slice aligner receives second order data streams from one second-order down-converter;

- searching for K alignment slices formed from the frame alignment word, wherein M is divisible by K-L, and the search is carried out by K slice aligners and each of said slice aligners searches for a different one of the K alignment slices; - generating by a slice aligner a marker indicating a bit sequence in the data stream that matches the sought alignment slice;

- assembling in a combiner a contiguous K-L-bit wide data stream if within two adjacent clock cycles all K slice aligners generated said markers for K different alignment slices. Preferably, in data streams in which each frame further comprises a multi-frame alignment word and said multi-frame alignment word changes its value periodically in accordance with a predefined algorithm, the method further comprises adding to every of said K alignment slices at least one bit taken from the multi-frame alignment word, wherein said first order down-converter takes every K^th bit from said multi-frame alignment word in order to add said at least one bit to said alignment slice. Said slice aligners check if the bits added to the K alignment slices change their values in accordance with said predefined algorithm.

Further features of the present invention are as claimed in the dependent claims.

The advantages of the present invention include:

• ability to synchronise of the receiver at any time during transmission without the need for support from external devices; • the present invention offers a "recovery time" advantage as it can re-train at any time, usually within a few milliseconds;

• the present invention does not require any substantial software support, other than a simple monitor to check that it has trained, whereas the prior art technique requires software to control and sequence the external devices mentioned above;

• the present invention offers a cost advantage as there are no external devices needed.

Brief description of the drawings The present invention will be understood and appreciated more fully from the following detailed description taken in conjunction with the drawings in which:

FIG. 1 is a block diagram illustrating an apparatus for de-serialisation of a framed data stream in one embodiment of the present invention; FIG. 2 is a flow diagram illustrating a method of de-serialisation of a framed data stream in one embodiment of the present invention;

FIG. 3 is a flow diagram illustrating a method of de-serialisation of a framed data stream in one embodiment of the present invention;

FIG. 4 is a diagram illustrating ITU-T G.709 data frame;

FIG. 5 is a diagram illustrating MFAS structure of ITU-T G.709 data frame;

FIG. 6 is a histogram displaying training times in milliseconds obtained in experiments in accordance with embodiments of the present invention.

Description of embodiments of the invention The present invention is discussed herein below in the context of ITU-T G.709 data stream. However, it should be understood that it is not limited to ITU-T G.709, but applies to any protocol of transmitting data (this includes voice, video and multimedia) in form of packets or frames of a constant size and comprising within the packet or frame a word that has fixed length and value.

The term "frame" herein below refers to a packet of data of a constant size and used for transmission of that data over a transmission link.

The term "frame alignment word" herein below refers to any word that has fixed length and value and is repeated in the same position of every frame.

With reference to FIG. 1 an apparatus for de-serialisation of a framed data stream is presented. For the sake of clarity the drawings present the invention in a very schematic way with elements and lines not essential for understanding the invention omitted. The block diagram shown in FIG. 1 illustrates an apparatus for de-serialisation of a framed data stream comprising one first-order 4:1 down converter, 102, followed by four second-order 4:1 down converters 104 - 110. The down-converters 102 - 110 work by taking every fourth bit of the received data stream and sending it to one of the four outputs. If, for example, the input stream to the first-order down-converter 102 contains bits BO, Bl, B2, B3, B4, B5, B6, B7 and so on, the bits are distributed over the outputs 150 - 180 as follow:

Output 150: BO, B4, B8 and so on Output 160: Bl, B5, B9 and so on

Output 170: B2, B6, BlO and so on Output 180: B3, B7, Bl 1 and so on

However it may not be that the BO bit goes to the top output 150. BO, being the first chronologically bit in the sequence can be at any of the four outputs, e.g.

Output 150: B2, B6, BlO and so on Output 160: B3, B7, BIl and so on Output 170: BO, B4, B8 and so on Output 180: B 1 , B5, B9 and so on

The different possible arrangements of bits at the outputs of the down-converters will be referred to as "bit orientation" in the following description.

The same operations are performed in the second-order down-converters 104 —

110. This results in lόbit wide data samples at one sixteenth of the native serial data rate. The diagram illustrated in FIG. 1 shows the data paths but not the clocks and control signals.

Blocks 112 - 118 are four identical slice aligners. Each slice aligner inspects every fourth bit of the incoming data stream and independently locks on to its frame structure. It reports when it has found alignment and also generates a marker, which indicates the start of each repetitive frame. It indicates which of the four possible slices that it has identified.

Block 120 is a combiner. It takes all four 4-bit streams and combines them into a single, contiguous, 16-bit wide stream. Piecing together the four separate chunks is like locking together the pieces of a jigsaw. The combiner 120 takes account of the markers generated by the slice aligners. It introduces compensation delays, as required, to temporally align all four data chunks. It also uses the slice identification code to decide which section of the final 16-bit data word shall be built from the particular 4-bit data chunk. If the markers are too far apart then it considers the alignment process to be invalid and will trigger realignment.

If we consider the case of a stream carrying ITU G.709 OTUl data then the frame alignment word (or FAS - Frame Alignment Signal for ITU G.709) is the 48-bit pattern "F6F6F6282828" with time travelling from left to right. The same in binary representation:

1111 0110 1111 0110 1111 0110 0010 1000 0010 1000 0010 1000

From the 48 bit long alignment word every one of the slice aligners, 112 - 118, sees every fourth bit, which means that the FAS, even if sliced, still can be used as alignment word (which will be referred herein below as an alignment slice) as every of the slices (alignment slices) has a well defined and fixed pattern. The slice aligner, 112 - 118, will either see bits 1, 5, 9 ...or 2, 6, 10...or 3, 7, 11... or 4, 8, 12.... Each frame alignment slice therefore contains only 12 bits:

Slice 1 : 101010 010101 Slice 2: 111111 000000

Slice 3: 111111 101010 Slice 4: 101010 000000

Each individual slice aligner, 112 - 118, only sees every fourth bit of the incoming data stream (and thus the frame alignment word as well). Furthermore, the A- bit input chunk has an unknown bit orientation relative to the start of the frame alignment word.

As it was explained earlier, in the first-order down-converter 102 the data stream is split into four data streams and the chronologically first bit may go via any of the four outputs. This means that each one of the alignment slices denoted above as "slice 1 - 4" maybe input to any of the four second-order down converters. Once in the second-order down-converter, 104 - 110, the chronologically first bit of the alignment slice may go to any of the four outputs. This results in a situation that one slice aligner may receive any one of four alignment slices and there are four possible bit orientations of the alignment slice at the input of the slice aligners.

There are therefore:

- four different possible "slices" of the frame alignment word to search for.

- four different bit orientations to consider.

This gives 4x4 = 16 possible search arrangements, of which only one will yield satisfactory synchronisation.

In one clock cycle one slice aligner, 112 - 118, takes a 4-bit chunk and as the whole 48-bit FAS is divided into 4 alignment slices, each one 12-bit long, it takes 3 clock cycles to collect chunk big enough to be of a size of the alignment slice.

In the case of the ITU G.709 OTUl protocol, the alignment slice shall be seen once every 8160 received 4bit samples. The slice aligner compares the received data in 12-bit chunks with data stored in 12-bit history store. In one embodiment the history store is a memory for storing data previously received and said data is arranged in 4 groups of 12-bit samples, wherein one group contains data received by one of slice aligners (112 - 118). In general, the length of the data samples stored in particular group of the memory must be of the length of the alignment slice in the slice aligner associated with that group. In one embodiment the memory is a separate module that serves all slice aligners. Alternatively, each of the slice aligners has its own memory module that operates as the 12-bit history store.

In one embodiment the size of the memory is equal to the size of one frame of the framed data stream. However, in alternative embodiments the memory module is bigger than the size of one frame.

If the content of the history store (i.e. one of the 12 bit samples) matches the current choice its position is remembered. The alignment slice, if this is a real match, must be repeated periodically every 81604-bit samples received by the slice aligners. Additionally, if this is a real match, the remaining three slice aligners also had to find matching samples in the respective groups of the history store.

If the same match is found again and the spacing between the two matches is 8160 4-bit samples it means that it is likely that it is alignment slice. Once three consecutive patterns have been seen correctly then the circuit shall remain in the aligned state unless externally reset. In one embodiment the slice aligner generates the alignment marker if said slice aligner found a bit pattern of one of the four alignment slices three times consecutively and the spacing between said three consecutive findings is 8160 4-bit samples. However in alternative embodiment the slice aligner generates the marker each time the matching bit pattern is found and the combiner 120 determines if there were three markers spaced apart by 8160 4-bit samples and received from the same slice aligner. The 4-bit output shall be bit aligned, being fed from the output of the input barrel shifter. The slice identification code (i.e. Slice 1, Slice 2, Slice 3 or Slice 4) and the start of frame position shall be reported. In practice it means that the combiner 120 has the information necessary to assemble the received data into one contiguous 16-bit wide data stream. Once the alignment slices are identified in the data streams we know where the frame starts and in what order the data must be read from the slice aligner outputs in order to combine them into one contiguous data stream.

If the chosen pattern is not seen for just over a frame (in one embodiment the figure of 8192 4-bit samples (2¹³) received by one slice aligner can be chosen) then the next search arrangement is selected. When this happens the bit orientation position is incremented. It means that the slice aligner continues to search for the same alignment slice but with changed (incremented) bit orientation. When all four bit orientation positions have been tried then the next alignment slice is chosen. The search arrangement state may be thought of as a 4-bit binary number. The two least significant bits drive the input barrel shifter (bit orientation position) and the two most significant bits select the identification code of 12-bit frame alignment slice to search for.

Once all four slice aligners 112 - 118 have reported, by sending the markers, that they have aligned, i.e. that they have found patterns matching the alignment slices, then the combiner 120 shall inspect the four individual markers. When any such marker is found then the remaining three shall be active either in the same or the adjacent clock cycle. Failure to meet these criteria shall result in a full reset of the four slice aligners, 112 - 118, as it indicates a rare but theoretically possible false alignment. If the frame markers span two clock cycles then the data from the aligners that present an "earlier" pulse shall be delayed by exactly one clock cycle. It can be demonstrated that genuine data that is correctly aligned would have frame start pulses that never differ in position by more than one clock cycle.

The final contiguous 16-bit samples are assembled from the four incoming 4-bit samples. They are already bit aligned within themselves but still need to be slotted together in an order which depends on the slice identification code supplied from each slice aligner. If two or more aligners appear to lock onto the same slice then this is clearly an error condition, which results in a full reset as described above. One possible implementation of the frame marker span checker is to have a 4-bit quantity representing the individual markers from the four slice aligners. At each clock cycle, the current quantity and the previous quantity are stored. If the four bits are numbered 0 to 3 then a marker found condition is given by:

a) Previous(O) OR Previous(l) OR Previous(2) OR Previous(3)

The only situation that yields value false is when no markers were received in the particular clock cycle. If all four markers were received in the previous clock cycle or if at least one of the markers was detected in the previous clock cycle the value of the condition a) is true.

On the first clock cycle where a marker is found, a valid condition is given by:

b) (Previous(O) OR Current(O)) AND (Previous(l) OR Current(l)) AND

(Previous(2) OR Current(2)) AND (Previous(3) OR Current(3))

If the condition a) was true with all four markers received condition b) is also true. If the condition a) was true with less then four markers received condition b) will be true only if the markers not received in the previous clock cycle are received in the current clock cycle.

If condition b) is true then a valid alignment condition has been found.

If condition b) is false then an invalid alignment condition has been found.

With reference to FIG. 4 and FIG. 5 a preferred embodiment of the present invention, when applied to ITU G.709 transmission protocol, will be discussed. In FIG. 4 a simplified structure of a ITU G.709 frame is depicted. What is important for the preferred embodiment is that the frame in addition to the frame alignment word (or Frame Alignment Signal - FAS) also contains a multiframe alignment word (or Multiframe Alignment Signal - MFAS). MFAS is a single byte word that is not fixed and changes its value from frame to frame. MFAS in ITU G.709 frame is scrambled and cycles modulo-256, which means that it returns to its original value every 256 frames. One G.709 multiframe contains 256 frames. Since the MFAS is scrambled it counts down rather than up and the values of the bits in MFAS changes their value as it is illustrated in FIG. 5.

As it was explained earlier the first- and second-order down-converters generate four 4-bit wide data streams, which, in turn, are passed into four slice aligners, 112 — 118. If the original serial data stream is described by bits BO, Bl, B2, B3, B4 (and so on) then each slice aligner will only see every fourth bit. For example:

Slice aligner 112 may see bits B2, B6, BlO, Bl 4, Bl 8 and so on. Slice aligner 114 may see bits B3, B7, BI l, B15, B19 and so on. Slice aligner 116 may see bits BO, B4, B8, B 12, B 16 and so on.

Slice aligner 118 may see bits Bl, B5, B9, B13, B17 and so on.

As explained before there are four possible combinations, depending on which slice aligner, 112 - 118, sees BO, the chronologically first bit in the sequence.

The slice aligners look for a particular "slice" of the frame alignment word and its following MFAS (multi-frame alignment sequence). A complete frame alignment word plus MFAS occupies 56 bits in total:

1111 0110 1111 0110 1111 0110 0010 1000 0010 1000 0010 1000 hgfedcba

where "hgfedcba" are the individual bits of the MFAS, with "a" being the least significant. In one embodiment each slice aligner can be programmed to look for a particular alignment slice, depending on the value of N in the range 0 to 3. Note that the upper bits of the MFAS "hgfe" toggle too slowly and are therefore ignored in the search process. Note also that each of said alignment slices has two bits from MFAS that follow the 12 bits of FAS and that only the bits "dcba" are checked as they toggle frequently enough to be checked:

N=O: aligner looks for:101010000000*a(a toggles every frame); N=I: aligner looks for :111111101010*b(b toggles every other frame); N=2: aligner looks for:111111000000*c(c toggles every fourth frame); N=3: aligner looks for : 101010010101 * d (d toggles every eighth frame).

The asterisk (*) marks the position of the upper MFAS bit which is ignored.

Since each slice aligner, 112-118, receives 4-bit data samples, and the start position of the frame alignment sequence is unknown, four parallel searches are performed. This is much faster than the alternative technique of cycling periodically round the four possible scenarios.

Each slice aligner, 112-118, can be in one of five states, namely unaligned, found 1, found 2, found 3 and aligned. An inspection interval occurs once every 2^N frames.

This means that if sequence 101010000000 is found by one of the slice aligners it is expected that it will be followed by "*a" bits from MFAS. Presence of bit "a" is verified with N=O as it is explained above, which means that inspection interval for verifying presence of bit "a" that follows the sequence 101010000000 is 2° = 1 frame. If sequence 111111101010 is found by another slice aligner it is expected to be followed by bits "*b" and this is verified with N=I, which gives inspection interval of 2 frames.

If sequence 111111000000 is found by yet another slice aligner it is expected to be followed by bits "*c" and this is verified with N = 2, which gives inspection interval of 4 frames.

If sequence 101010010101 is found by yet another slice aligner it is expected to be followed by bits "*d" and this is verified with N = 3, which gives inspection interval of 8 frames.

The following algorithm applies to the alignment process:

Unaligned

The circuit searches, 302, for the very first occurrence of the 12-bit sequence from FAS. When found, it starts a sample counter and remembers, 304, the current value of the a, b, c or d bit. It then passes to Found 1 state.

Found 1

The 12-bit FAS slice is checked exactly one inspection interval later, 306, (i.e.1 frame for slice aligner where bit "a" is expected, 2 frames where bit "b", 4 frames where bit "c" and 8 frames where bit "d"). If it matches exactly, 308, and the a/b/c/d bits are the inverse, 310, of the stored value then it advances to Found 2. If the test fails, the circuit reverts to the Unaligned state.

Found 2

The 12-bit FAW slice is checked exactly one inspection interval later, 312, . If it matches exactly, 314, and the a/b/c/d bits are the same as the stored value, 316, then it advances to Found 3. If the test fails, the circuit reverts to the Unaligned state. Found 3

The 12-bit FAW slice is checked exactly one inspection interval later, 318. If it matches exactly, 320, and the a/b/c/d bits are the inverse, 322, of the stored value then it advances to Aligned. If the test fails, the circuit reverts to the Unaligned state.

Aligned

The circuit will 'jam' in the Aligned state, 324, unless a circuit reset is issued. Table 1 below illustrates the basis of the algorithm of verifying the presence of the a/b/c/d bits.

10

Table 1

The second column shows values of the a/b/c/d bits stored after match of the 12- bit FAS slices was found (four "zeros" in this example). In each row of the table in bold

15 and underlined are marked bits that are inspected every inspection period (1 frame for bit "a" and 8 frames for bit "d"). The bits in table 1 toggle in exactly the same way as it is illustrated in FIG. 5. Therefore if the bits that follow the 12-bit alignment slices on positions of bits a/b/c/d/ change their value as it is illustrated in table 1 and in FIG. 5 the algorithm described above allows for verifying if the found alignment slices are genuine

20 ones.

When the circuit reverts to the unaligned state after a match failure then it masks out any detected patterns for a pseudo-random interval of between 0 and 1 G.709 frames. In one embodiment a 25-bit pseudo-random binary sequence (repeating after 25 2²⁵ - 1 clock cycles) is used to generate this interval. An overall controlling algorithm, taking account of all four slice aligners, 112 - 118, shall operate as follows. It can be in one of four states, namely searching, consolidating, verifying and fully aligned:

Searching

All four slice aligners are set to N = 0. When one of them becomes aligned then the circuit advances to Consolidating.

Consolidating The aligner that is already aligned keeps its N = 0 value. The remaining three have N set to 1, 2 and 3 in a cyclical sense. A timer is started. When all four slice aligners 112 - 118 become aligned then the circuit advances to Verifying. If the timer expires (about 25 milliseconds) before this happens then all four aligners are reset and the circuit reverts to Searching. The time of 25 milliseconds is not to be of a limiting nature. It is used in the description of the embodiments of the present invention to demonstrate that the present invention will work with such expiry time of the timer. It is clear that other values of the timer expiry time can also be used. The simulated results for the method (using MFAS) give a mean training time of either 1.79 ms or 5.58 ms, depending on the nature of the data being supplied and its bit error rate. A time-out figure of 25 ms was arrived at by "judgement" rather than calculation, being sufficiently long to ensure that a very high proportion (well over 99%) of genuine training would take place before this time expires.

Verifying The position of the start-of-frame is checked for all four aligners. If they all agree within one clock cycle then the circuit advances to Fully Aligned. Otherwise all four aligners are reset and the circuit reverts to Searching.

Fully Aligned The circuit will 'jam' in the Fully Aligned state unless a circuit reset is issued. A More General Case

In general, consider a K-bit data stream transmitted from the first-order down- converter to the remaining parts of the processing device. Each bit is too fast to process as a serial stream so it is widened out to an L-bit stream. The output from the final com- biner, 120, is then K-L (K times L) bits wide. Whilst K and L would traditionally be exact powers of two (2, 4, 8, 16 and so on), they could be any natural number greater than 1. If the framed data stream contains a fixed frame alignment pattern once every M bits then K and L must be constrained such that M is exactly divisible by K-L. This constraint arises from the fact that each slice aligner, 112 - 118, must see the same part of the frame alignment pattern on each successive frame. If the frame alignment pattern is P bits long then each slice aligner only sees P/K bits at a time. To make use of all available frame alignment bits (advisable but not mandatory) then P should be exactly divisible by K. Each slice aligner has to identify one of K possible frame alignment slices. Its barrel shifter has to produce an L-bit wide stream and therefore has L degrees of freedom. There are therefore K-L possible scenarios to cycle round before finding the correct one.

In the embodiments in which each frame also comprises a multi-frame alignment word, which changes its value periodically in accordance with a predefined algorithm the slice aligners see also parts of the multi-frame alignment word. The process of first-order down-conversion comprises adding to every of said K alignment slices at least one bit taken from the multi-frame alignment word. Exacltly as in case of the frame alignment word said first order down-converter takes every K^th bit from said multi-frame alignment word in order to add said at least one bit to said alignment slice. Since it is known, which bit (or bits) of the multi-frame alignment word should follow which alignment slice said slice aligners check if the bits on the positions where the multi-frame alignment word bit (bits) are expected change their values in accordance with said predefined algorithm. If they change their value in accordance with said predefined algorithm it is an indication of a genuine match. In one embodiment only part of said slice aligners check if the bits expected to be part of the multi-frame alignment word change their values in accordance with said predefined algorithm. In this embodiment the check is performed on data streams with a highest periodicity of change of said bit (bits) from the multi-frame alignment word.

Training Time

In an ideal world, data would never be confused with frame alignment words. In this case, training would take at most K-L frames. In reality, the search would have to run for just slightly longer than a complete frame before switching to the next scenario to allow for the barrel shifter to fill up with new data on each change. So it would take at most (1 + e)-K-L where e is a small number (typically 0.01 to 0.05).

The Principle ofFalsing

Real data usually looks very much like a random sequence of O's and l's. If the data being carried does not look random then it is usually scrambled to give it random- like properties. Now patterns within that pseudorandom data stream can easily mimic those of the frame alignment word slices. In these cases, there is no way to differentiate between the two. This is called falsing.

If we are looking for P/K bits of a frame alignment pattern then the probability of random data mimicking this at any particular bit position is 2^'s where S = P/K. Now each frame contains (M-P) data bits of which (M-P)/K are seen by each slice aligner 112 - 118. If the probabilities are small then the chance of seeing a false alignment pattern in any complete data frame is given by:

2^"s -(M-P)/K

On average, there will be one half of a frame of data before seeing the real frame alignment pattern so the chance of seeing the false one before the real one is one half of this:

2^"(s+1) (M-P)/K When a false alignment pattern is seen then the circuit needs to wait one whole frame before the re-check confirms that it is a false one. This clearly lengthens the training time. There is, of course, a slight chance of seeing two consecutive false alignments:

2-s ₂-^(S+ⁱ⁾ _(M.py_{K =} 2-^(2S+1)(M-P)/K

Three consecutive false alignments are rarely seen with a probability of:

2^"(3S+1)(M-P)/K

Bit Error Rates

Real data that has been transmitted through optical fibres or radio links often experiences transmission errors. The Bit Error Rate (BER) is a measure of the probability that any received bit has been corrupted during its path from the transmitter. Many communications systems use Forward Error Correction to remove such errors, allowing links to operate at BER as high as 0.001 without the customer's data suffering any degradation. Unfortunately, we require to train the incoming data before the error correction has been performed (known as pre-FEC). Consequently, we have to train the apparatus in the presence of such errors.

The presence of a finite bit error rate has no effect on the statistics of the signal itself, since a pseudorandom data stream with noise is just another pseudorandom data stream. The difference is noticed when the slice aligner tries to lock on to the subset of the frame alignment pattern. Since the search pattern is P/K bits long it follows that if the bit error rate is B then the chance of a good pattern being correctly observed as an alignment pattern is:

(1- B) ^P/K

At this point in the analysis it becomes clear that the mathematics of the training time, taking into account both falsing and a finite bit error rate, is particularly complex. A more realistic approach would be to simulate the behaviour using a computer- based application.

Sample Simulation Results

The simulation involves data formatted in accordance with ITUG.709 OTUl international standard. This data transmission protocol uses frames which are 130560 bits long, containing a frame alignment word which is 48 bits long. Since the frame is long and the alignment word is short, this scenario is a particularly challenging one for the training apparatus. We supply the data from the first-order down-converter 102 to the remaining parts of the device as a 4-bit wide stream (at about 666 M samples/second) and convert it into a 16-bit wide stream (at about 155 M samples/second). Hence:

K =4; L = 4; M= 130560; P = 48; S =12.

One frame has duration of 48.971 microseconds. We are simulating a particularly high bit error rate (1/256), making the challenge even more difficult. Hence:

B = 0.003906.

The following data present 30 training times that were obtained from multiple simulation runs with differing parameters. In all cases a pseudo random bit sequence, PRBS, generator (2³⁹ - 1) was used to fill the G.709 frames with pseudorandom data and to generate a 1 in 256 error rate (which has the potential to corrupt the frame alignment words). The parameters fed into the simulation are the PRBS seed, initial barrel rotation offset and frame alignment word start position.

1.223 ms, 1.419 ms, 1.860 ms, 3.230 ms, 3.671 ms, 6.756 ms, 1.957 ms, 6.168 ms, 4.944 ms, 4.944 ms, 5.042 ms, 5.482 ms, 4.748 ms, 3.084 ms, 4.700 ms, 8.861 ms, 2.300 ms, 3.769 ms, 1.957 ms, 5.581 ms, 6.315 ms, 6.070 ms, 4.307 ms, 12.680 ms, 2.104 ms, 4.794 ms, 6.706 ms, 2.887 ms, 6.071 ms, 11.799 ms. Reference is now made to FIG. 6 where a histogram displaying these 30 results is presented. The horizontal axis displays the range of training time in milliseconds. The vertical axis displays the frequency of occurrence.

If there was no falsing effect and a zero bit error rate then the maximum training time would be given by the (already derived) formula:

(1 + e)-K-L frames

Since one frame is 48.971 microseconds long and taking e to be 0.05 then this gives a figure of about 0.823 ms. This illustrates the dramatic effect that falsing and the bit error rate have on the training time.

In one embodiment the 4:1 down-converters 102 - 110 are known in the art de- multiplexing functions.

Also in one embodiment the first-order 4:1 down-converter 102 is located outside the processing device and other blocks, 104 - 120, are contained within the ASIC or FPGA. In an alternative embodiment all five down-converters, 102 - 110, four slice aligners, 112 - 118, and the combiner 120 are contained within ASIC or FPGA.

In yet another embodiment the method of the invention may be implemented in a computer program product for execution by a processor and stored on any computer useable storage device.

Claims

1. An apparatus (100) for de-serialisation of a framed data stream, each frame being M-bits long and comprising a fixed frame alignment word, said apparatus comprising one first-order K:l down-converter (102) for splitting received data stream into K data streams, K second-order L:l down-converters (104 - 110), each one for splitting received data stream into L data streams, and each connected to one of the outputs of the first-order down-converter (102) and K slice aligners (112 - 118), each connected to outputs of one of the second-order down-converters (104 - 110); the apparatus further comprises a combiner (120) for combining all data streams from the slice aligners (112 - 118) into one contiguous data stream of width of K-L bits, wherein M is divisible by K-L and said first- order down converter (102) is adapted to form K different alignment slices from the frame alignment word by taking every K^th bit of said frame alignment word, wherein each of the slice aligners (112 - 118) is adapted to search for one of the K alignment slices in the received data stream and to generate a marker indicating a bit sequence in the data stream that matches the sought alignment slice and the combiner (120) is adapted to assemble the contiguous K-L-bit wide data stream if within two adjacent clock cycles all K slice aligners generated said markers for K different alignment slices.

2. The apparatus (100) according to claim 1 comprising a memory for storing data, wherein said data in said memory is arranged in K groups, each group comprising data received by one slice aligner (112 - 118) associated with said group in preceding clock cycles.

3. The apparatus (100) according to claim 2, wherein size of the memory is at least equal to the size of one frame of the framed data stream.

4. The apparatus (100) according to claim 2 or claim 3, wherein the length of the data samples stored in particular group of the memory is of the length of the alignment slice in the slice aligner associated with that group.

5. The apparatus (100) according to any one of claims 1 - 4, wherein all K alignment slices have equal length.

6. The apparatus (100) according to any one of preceding claims, wherein the slice aligner is adapted (112 - 118) to generate the alignment marker if said slice aligner (112 - 118) found a bit pattern of one of the K alignment slices three times consecutively and the spacing between said three consecutive findings is M/K bits.

7. The apparatus (100) according to any one of preceding claims, wherein the combiner (120) is adapted to try a new search arrangement if there is no match within the spacing of M/K bits, wherein in said new search arrangement the slice aligners (112 - 118) are adapted to search for the same alignment slice with changed bit orientation.

8. The apparatus (100) according to any one of preceding claims, wherein if there is no match within the spacing of M/K bits the combiner (120) is adapted to start a new search for the K alignment slices, wherein in said new search each slice aligner is adapted to search for a different alignment slice from the group of K alignment slices in comparison to the search, which yielded no match within the spacing of M/K bits.

9. The apparatus (100) according to any one of preceding claims, wherein the combiner (120) is adapted to store information if the marker was received from the slice aligner (112 - 118) in the preceding clock cycle.

10. The apparatus (100) according to claim 9, wherein the combiner (120) is adapted to compensate delay of the markers received in the preceding clock cycle in relation to other markers if the delay is one clock cycle and to apply the same delay compensation to alignment slices and data in the data stream of the delayed marker.

11. The apparatus (100) according to claim 9 or claim 10, wherein the combiner (120) is adapted to discard the received markers and to initiate a new search for the alignment slices if the markers were received within more than two clock cycles.

12. The apparatus (100) according to any one of preceding claims, wherein the down- converter (102 - 110) comprises of a demultiplexer.

13. The apparatus (100) according to any one of preceding claims, wherein the data stream conforms to ITU-T G.709 standard.

14. The apparatus (100) according any one of preceding claims, wherein each frame further comprises a multi-frame alignment word, said multi-frame alignment word is adapted to change its value periodically in accordance with a predefined algorithm, said first order down-converter (102) is adapted to add to every of said K alignment slices at least one bit taken from the multi-frame alignment word, wherein said first order down- converter (102) is adapted to take every K^th bit from said multi-frame alignment word in order to add said at least one bit to said alignment slice, and said slice aligners (112 - 118) are adapted to check if the bits added to the K alignment slices change their values in accordance with said predefined algorithm.

15. The apparatus (100) according to claim 15, wherein only part of said slice aligners are adapted to check if the bits added to the K alignment slices change their values in accordance with said predefined algorithm, wherein said adapted slice aligners are allocated to data streams with a highest periodicity of change of said added bit.

16. A method of de-serialisation of a framed data stream, each frame being M-bits long and comprising a fixed frame alignment word, said method comprising: - a first-order down-converting (202) of the input data stream to K first-order data streams and said first-order down converting includes forming K different alignment slices from the frame alignment word by taking every K^th bit of said frame alignment word;

- a second-order down-converting (204) in which each one of the K first-order data streams is down-converted to L second-order data streams;

- searching (206) for K alignment slices formed from the frame alignment word, wherein M is divisible by K-L, and the search is carried out by K slice aligners and each of said slice aligners searches for a different one of the K alignment slices;

- generating (210) by a slice aligner a marker indicating a bit sequence in the data stream that matches the sought alignment slice;

- assembling (214) in a combiner a contiguous K-L bit wide data stream if within two adjacent clock cycles (212) all K slice aligners generated said markers for K different alignment slices.

17. The method according to claim 16 comprising storing in a memory data received in previous clock cycles, wherein said memory is arranged in K groups, each group comprising data received by one slice aligner associated with said group.

18. The method according to claim 17, wherein size of the memory is at least equal to the size of one frame of the framed data stream.

19. The method according to claim 17 or claim 18 comprising arranging of the data in samples, wherein the length of the data samples stored in particular group of the memory is of the length of the alignment slice in the slice aligner associated with that group.

20. The method according to any one of claims 16 - 19, wherein the K alignments slices have equal length.

21. The method according to any one of claims 16 - 20, wherein each of said slice aligners generates the alignment marker if said slice aligner found a bit pattern of one of the K alignment slices three times consecutively and the spacing between said three consecutive findings is M/K bits.

22. The method according to any one of claims 16 - 21, wherein the combiner tries a new search arrangement if there is no match within the spacing of M/K bits, wherein in said new search arrangement the slice aligners search for the same alignment slice with changed bit orientation.

23. The method according to any one of claims 16 - 22, wherein if there is no match within the spacing of M/K bits the combiner starts a new search for the K alignment slices, wherein said new search each slice aligner searches for a different alignment slice from the group of K alignment slices in comparison to the search, which yielded no match within the spacing of M/K bits.

24. The method according to any one of claims 16 - 23, wherein the combiner stores information if the marker was received from the slice aligner in the preceding clock cycle.

25. The method according to claim 24, wherein the combiner compensates delay of the markers received in the preceding clock cycle in relation to other markers if the delay is one clock cycle and applies the same delay compensation to alignment slices and data in the data stream of the delayed marker.

26. The method according to claim 24 or claim 25, wherein the combiner discards the received markers and initiates a new search for the alignment slices if the markers were received within more than two clock cycles.

27. The method according any one of preceding claims, wherein each frame further comprises a multi-frame alignment word, said multi-frame alignment word changes its value periodically in accordance with a predefined algorithm, the method further comprising adding to every of said K alignment slices at least one bit taken from the multi- frame alignment word, wherein said first order down-converter takes every K^th bit from said multi-frame alignment word in order to add said at least one bit to said alignment slice, and said slice aligners check if the bits added to the K alignment slices change their values in accordance with said predefined algorithm.

28. The method according to claim 27, wherein only part of said slice aligners check if the bits added to the K alignment slices change their values in accordance with said predefined algorithm, wherein said adapted slice aligners are allocated to data streams with a highest periodicity of change of said added bit.