EP2067235A2

EP2067235A2 - Power supply and electronic ballast with auxiliary protection circuit

Info

Publication number: EP2067235A2
Application number: EP07837873A
Authority: EP
Inventors: Arjun K. Choudhury; Bangalore Sharath
Original assignee: Osram Sylvania Inc
Current assignee: Osram GmbH
Priority date: 2006-09-30
Filing date: 2007-09-07
Publication date: 2009-06-10
Also published as: KR20090096689A; CN101523679B; WO2008039293A2; WO2008039293A3; CN101523679A; EP2067235A4

Abstract

An arrangement (10) comprises a front-end circuit (100), a back-end circuit (200), and an auxiliary protection circuit (300). Front-end circuit (100), which typically includes an EMI filter and rectifier circuitry, has first and second input connections (12,14) for receiving a conventional source of AC voltage (20). Back-end circuit (200), which typically includes power factor correction and inverter circuitry, is coupled to front-end circuit (100) and a load (30) such as one or more gas discharge lamps. Auxiliary protection circuit (300) is coupled between front- end circuit (100) and back-end circuit (200). During operation, auxiliary protection circuit (300) protects back-end circuit (200) from any malfunction or damage that may occur due to a line-sag condition or due to a phase-to-phase miswiring condition. Additionally, auxiliary protection circuit (300) significantly reduces the peak inrush current that is experienced by arrangement (10) following initial application of AC power.

Description

POWER SUPPLY AND ELECTRONIC BALLAST WITH AUXILIARY PROTECTION CIRCUIT

Field of the Invention

[0001] The present invention relates to the general subjects of power supplies and circuits for powering gas discharge lamps. More particularly, the present invention relates to a power supply and electronic ballast that includes an auxiliary protection circuit for the protecting the power supply or ballast against certain AC line fault conditions and for limiting the peak inrush current following initial application of AC power to the power supply or ballast.

Background of the Invention

[0002] Many existing power supplies and electronic ballasts (for powering one or more gas discharge lamps) are typically connected to a source of alternating current (AC) voltage (e.g., 277 volts rms at 60 hertz) that is provided by an electric utility company. In practice, power supplies and electronic ballasts encounter a number of operational difficulties that involve the AC voltage source. Those problems include AC line drop-out conditions (also referred to as "line-sag" conditions), phase-to-phase miswiring conditions, and high inrush current.

[0003] AC line drop-out conditions (wherein the voltage provided by the AC source temporarily decreases to a level that is dramatically less than its nominal value) have been observed to cause problems in power supplies and electronic ballasts. Many power supplies and ballasts include a DC-to-DC converter (e.g., a boost converter) for purposes of providing power factor correction and other features. For those power supplies and ballasts, an AC line drop-out condition (also referred to as a "line sag" condition) sometimes causes the DC-to-DC converter to enter into a "lock-out" mode wherein the converter fails to operate in a normal manner even after the AC line drop-out condition ceases; in such a case, it is necessary to cycle the AC input power to the ballast or power supply in order to allows the DC-to-DC converter to operate in its intended normal manner. Additionally, for at least some DC-to-DC converters, an AC line dropout condition often causes a significant overshoot in the voltage provided at the output of the DC-to-DC converter, thereby endangering the reliability of the DC-to-DC converter.

[0004] During installation of power supplies and electronic ballasts, a common wiring error involves incorrectly connecting the input wires of the power supply or ballast to two different phases of the AC voltage source (instead of correctly connecting the "hot" wire to one phase and the "neutral" wire to the neutral connection of the AC voltage source). Such miswiring, which is sometimes referred to as a "phase-to-phase" wiring fault condition, may produce voltages within the power supply or ballast that are significantly higher than normal, and which may therefore cause failure of certain components within the power supply or ballast.

[0005] Inrush current, which occurs upon initial application of AC power, is widely acknowledged to be a significant problem in power supplies and electronic ballasts, and is inherent (in the absence of protective/compensatory means) in many AC-line powered circuits which include a large bulk capacitance that is operably coupled in series with the AC voltage source. High peak inrush currents have been associated with a host of problems, including nuisance tripping of circuit breakers, degradation of electrical components, etc.

[0006] Thus, a need exists for power supplies and electronic ballasts that include auxiliary protection circuitry for protecting against line drop-out and phase-to-phase wiring fault conditions, and for reducing the peak inrush current. A power supply or electronic ballast with such an auxiliary protection circuit would represent a significant advance over the prior art.

Brief Description of the Drawings

[0007] Fig. 1 is an electrical diagram of an arrangement that includes an auxiliary protection circuit, in accordance with a preferred embodiment of the present invention. Detailed Description of the Preferred Embodiments

[0008] FIG. 1 describes an arrangement 10 comprising a front-end circuit 100, a back-end circuit 200, and an auxiliary protection circuit 300. Front-end circuit 100, which typically includes an electromagnetic interference (EMI) filter and rectifier circuitry, includes first and second input connections 12,14 for receiving a conventional source of alternating current (AC) voltage 20 (e.g., 277 volts rms at 60 hertz). AC voltage source 20 provides a voltage VAC between first and second input connections 12,14. Back-end circuit 200, which typically includes power factor correction (e.g., boost converter) and inverter circuitry, is operably (i.e., not necessarily directly) coupled to front-end circuit 100. During operation of arrangement 10, back-end circuit 200 delivers power to a load 30 by way of first and second output connections 16,18. Auxiliary protection circuit 300 is coupled between front-end circuit 100 and back-end circuit 200. During operation, auxiliary protection circuit provides the following functions:

(1) To electrically isolate back-end circuit 200 from AC source 20, in response to a

phase-to-phase miswiring condition (i.e., wherein first input connection 12 is connected to a first

phase of AC source 20, and second input connection 14 is connected to a second phase of AC

source 20, instead of to the neutral wire of AC source 20);

(2) To electrically isolate back-end circuit 200 from AC source 20, in response to a line-

sag condition (i.e., wherein the magnitude of the AC voltage, V_AC, provided by AC source 20 is substantially less than its normal value); and (3) To limit the peak inrush current (which occurs upon initial application of power to

arrangement 10).

[0009] In a preferred embodiment of the present invention, as illustrated in FIG. 1, auxiliary protection circuit 300 includes first and second input terminals 302,304, first and second output terminals 306,308, first, second, third, fourth, and fifth nodes 310,312,314,316,318, first, second, third, and fourth electronic switches M1,M2,M3,M4, first, second third, fourth, fifth, sixth, seventh, and eighth resistors R1,R2,R3,R4,R5,R6,R7,R8, and first and second capacitors C1,C2.

[0010] First and second input terminals 302,304 are coupled to front-end circuit 100. First and second output terminals 306,308 are coupled to back-end circuit 200. First electronic switch Ml is operably coupled between second input terminal 304 and second output terminal 308; first electronic switch Ml has a control terminal 332 coupled to first node 310. Second electronic switch M2 is operably coupled between first node 310 and circuit ground 320 (circuit ground 320 is coupled to second input terminal 304); second electronic switch M2 has a control terminal 342 coupled to fifth node 318. In response to a line-sag condition, M2 turns on and thereby turns off Ml. Third electronic switch M3 is operably coupled between second node 312 and circuit ground 320; third electronic switch M3 has a control terminal 352 coupled to fourth node 316. In response to a line-sag condition, M3 turns off and thereby allows M2 to turn on (which, in turn, causes Ml to turn off). Fourth electronic switch M4 is operably coupled between first node 310 and circuit ground 320; fourth electronic switch M4 has a control terminal 362 coupled to third node 314. In response to a phase-to-phase miswiring condition, M4 turns on and thereby turns off Ml. [0011] As depicted in FIG. 1, each of electronic switches M1,M2,M3,M4 is preferably realized by a N-channel field-effect transistor (FET). More particularly, first electronic switch Ml has a gate terminal (i.e., control terminal) 332 coupled to first node 310, a drain terminal 334 coupled to second output terminal 308, and a source terminal 336 coupled to second input terminal 304. Second electronic switch M2 has a gate terminal (i.e., control terminal) 342 coupled to fifth node 318, a drain terminal 344 coupled to first node 310, and a source terminal 346 coupled to circuit ground 320. Third electronic switch M3 has a gate terminal (i.e., control terminal) 352 coupled to fourth node 316, a drain terminal 354 coupled to fifth node 318, and a source terminal 356 coupled to circuit ground 320. Finally, fourth electronic switch M4 has a gate terminal (i.e., control terminal) 362 coupled to third node 314, a drain terminal 364 coupled to first node 310, and a source terminal 366 coupled to circuit ground 320.

[0012] As illustrated in FIG. 1, first resistor Rl is coupled between first input terminal 302 and first node 310. Second resistor R2 is coupled between first node 310 and circuit ground 320. First capacitor Cl is coupled between first node 310 and circuit ground 320. Third resistor R3 is coupled between first input terminal 302 and second node 312. Fourth resistor R4 is coupled between second node 312 and third node 314. Second capacitor C2 is coupled between second node 312 and circuit ground 320. Fifth resistor R5 is coupled between third node 314 and circuit ground 320. Sixth resistor R6 is coupled between second node 312 and fourth node 316. Seventh resistor R7 is coupled between fourth node 316 and circuit ground 320. Finally, eigth resistor R8 is coupled between second node 312 and fifth node 318.

[0013] During normal operation of arrangement 10 (i.e., when no line-sag or phase-to-phase miswiring condition is present), electronic switch Ml is on and the output of front-end circuit 100 is provided to back-end circuit 200; that is, auxiliary protection circuit 300 exerts no effect upon the normal operation of arrangement 10. [0014] If a phase-to-phase miswiring condition occurs, the voltage across input terminals 302,304 will be substantially higher than normal. Resistors Rl, R2 and capacitor Cl are sized so that, under this condition, the voltage Vc at node 314 will exceed the turn-on threshold for M4 well before the voltage Va at node 310 reaches the turn-on threshold for Ml. Accordingly, M4 will turn on well before Ml has a chance to turn on. With M4 turned on, the voltage Va at node 310 will be pulled down to about zero (because when M4 is turned on, node 310 is effectively connected to circuit ground 320), thereby ensuring that Ml is not turned on. With Ml off, back-end circuit 200 is protected from any excessive (and potentially destructive) voltage that would otherwise (i.e., in the absence of auxiliary protection circuit 300) appear across output terminals 306,308 following a phase-to-phase miswiring condition. M4 will remain on (and, correspondingly, Ml will remain off) until at least such time as the excessive voltage (present across input terminals 302,304) due to the phase-to-phase miswiring condition is cured.

[0015] If a line-sag condition occurs, the voltage across input terminals 302,304 will be substantially less than normal. Resistors R3,R6,R7 are sized so that, under this condition, the voltage Vd at node 316 will fall below the turn-on threshold necessary for keeping M3 on. Accordingly, M3 will be turned off. With M3 turned off, the voltage Ve at node 318 is allowed to assume a level (which, with M3 turned on, was at about zero volts) that exceeds the turn-on threshold of M2. Accordingly, M2 will turn on. With M2 turned on, the voltage Va at node 310 will be pulled down to about zero (because when M2 is turned on, node 310 is effectivelty connected to circuit ground 320), thereby turning off Ml. With Ml turned off, back-end circuit ' 200 is effectively isolated from the line-sag condition and is therefore prevented from entering any undesirable "lock out" mode as a result of the line-sag condition. M2 will remain on (and, correspondingly, Ml will remain off) until at least such time as the line-sag condition is cured and the voltage across input terminals 302,304 returns to an approximately normal level (at which point the voltage Vd will be higher than the turn-on threshold for M3, causing M3 to turn on, which cause Ve to go to about zero, thereby turning M2 off and allowing Ml to turn on).

[0016] Shortly after initial application of AC power to arrangement 10, FET Ml becomes conductive (i.e., once the voltage Va at node 310 reaches the turn-on threshold for Ml). It has been observed, in a prototype arrangement configured substantially as described in FIG. 1 , that, with the presence of auxiliary protection circuit 300, the peak inrush current (flowing into first input connection 12) was reduced from over 50 amperes (without auxiliary protection circuit 300) to a value on the order of only several amperes (with auxiliary protection circuit). Thus, auxiliary protection circuit 300 provides the added benefit of substantially reducing the peak inrush current.

[0017] Arrangement 10 may be advantageously employed within any of a number of power supply circuits or within electronic ballasts for gas discharge lamps (for the latter application, load 30 will consist of one or more gas discharge lamps).

[0018] Although the present invention has been described with reference to certain preferred embodiments, numerous modifications and variations can be made by those skilled in the art without departing from the novel spirit and scope of this invention.

[0019] What is claimed is:

Claims

1. An arrangement (10), comprising: a front-end circuit (100) having first and second input connections (12,14) adapted to receive a conventional source of alternating current (AC) voltage (20); a back-end circuit (200) operably coupled to the front-end circuit (100) and operable to deliver power to a load via first and second output connections (16,18); an auxiliary protection circuit (300) coupled between the front-end circuit (100) and the back-end circuit (300), wherein the auxiliary protection circuit (300) is operable:

(i) to electrically isolate the back-end circuit (200) from the source of AC voltage (20) in response to a miswiring of the first and second input connections (12,14), wherein the miswiring includes connection of the first input connection to a first phase of the source of AC voltage and connection of the second input connection to a second phase of the source of AC voltage;

(ii) to electrically isolate the back-end circuit (200) from the source of AC voltage (20) in response to a line-sag condition wherein the magnitude of the AC voltage provided by the AC voltage source (20) is substantially less than its nominal value; and

(iii) to limit a peak inrush- current that occurs upon initial application of AC power to the arrangement.

2. The arrangement of claim 1 , wherein the auxiliary protection circuit (300) comprises: first and second input terminals (302,304) coupled to the front-end circuit (100); first and second output terminals (306,308) coupled to the back-end circuit (200); first, second, third, fourth, and fifth nodes (310,312,314,316,318); a first electronic switch (Ml) operably coupled between the second input terminal (304) and the second output terminal (308), the first electronic switch having a control terminal (332) coupled to the first node (310); a second electronic switch (M2) operably coupled between the first node (310) and circuit ground (320), wherein circuit ground (320) is coupled to the second input terminal (304), the second electronic switch having a control terminal (342) that is coupled to the fifth node (318), wherein the second electronic switch is operable, in response to a line-sag condition, to turn on and to thereby turn off the first electronic switch (Ml); a third electronic switch (M3) operably coupled between the second node (312) and circuit ground (320), the third electronic switch having a control terminal (352) that is coupled to the fourth node, wherein the third electronic switch is operable, in response to a line- sage condition, to turn off and to thereby allow the second electronic switch (M2) to turn on; and a fourth electronic switch (M4) operably coupled between the first node (310) and circuit ground (320), the fourth electronic switch having a control terminal (362) that is coupled to a third node (314), wherein the fourth electronic switch is operable, in response to a phase-to- phase miswiring condition, to turn on and to thereby turn off the first electronic switch (Ml).

3. The arrangement of claim 2, wherein the auxiliary protection circuit (300) further comprises: a first resistor (Rl) coupled between the first input terminal (302) and the first node (310); a second resistor (R2) coupled between the first node (310) and circuit ground (320); a first capacitor (Cl) coupled between the first node (310) and circuit ground (320); a third resistor (R3) coupled between the first input terminal (302) and the second node (312); a fourth resistor (R4) coupled between the second node (312) and the third node (314); a second capacitor (C2) coupled between the second node (312) and circuit ground (320); a fifth resistor (R5) coupled between the third node (314) and circuit ground (320); a sixth resistor (R6) coupled between the second node (312) and the fourth node (316); a seventh resistor (R7) coupled between the fourth node (316) and circuit ground (320); and an eighth resistor (R8) coupled between the second node (312) and the fifth node (318).

4. The arrangement of claim 3, wherein the first electronic switch (Ml) comprises a N- channel field-effect transistor having a gate terminal (332), a drain terminal (334), and a source terminal (336), wherein the gate terminal (332) is the control terminal and is coupled to the first node (310), the drain terminal (334) is coupled to the second output terminal (308), and the source terminal (336) is coupled to the second input terminal (304)

5. The arrangement of claim 4, wherein the second electronic switch (M2) comprises a N- channel field-effect transistor having a gate terminal (342), a drain terminal (344), and a source terminal (346), wherein the gate terminal (342) is the control terminal and is coupled to the fifth node (318), the drain terminal (344) is coupled to the first node (310), and the source terminal (346) is coupled to circuit ground (320).

6. The arrangement of claim 5, wherein the third electronic switch (M3) comprises a N- channel field-effect transistor having a gate terminal (352), a drain terminal (354), and a source terminal (356), wherein the gate terminal (352) is the control terminal and is coupled to the fourth node (316), the drain terminal (354) is coupled to the fifth node (318), and the source terminal (356) is coupled to circuit ground (320).

7. The arrangement of claim 6, wherein the fourth electronic switch (M4) comprises a N- channel field-effect transistor having a gate terminal (362), a drain terminal (364), and a source terminal (366), wherein the gate terminal (362) is the control terminal and is coupled to the third node (314), the drain terminal (364) is coupled to the first node (310), and the source terminal (366) is coupled to circuit ground (320).

8. The arrangement of claim 1, wherein the load comprises at least one gas discharge lamp.

9. A circuit (10) for powering a load (30), comprising: a front-end circuit (100) having first and second input connections (12,14) adapted to receive a conventional source of alternating current (AC) voltage (20); a back-end circuit (200) operably coupled to the front-end circuit (100) and operable to deliver power to a load; an auxiliary protection circuit (300), comprising: first and second input terminals (302,304) coupled to the front-end circuit (100); first and second output terminals (306,308) coupled to the back-end circuit (200); first, second, third, fourth, and fifth nodes (310,312,314,316,318); a first electronic switch (Ml) operably coupled between the second input terminal (304) and the second output terminal (308), the first electronic switch having a control terminal (332) coupled to the first node (310); a second electronic switch (M2) operably coupled between the first node (310) and circuit ground (320), wherein circuit ground (320) is coupled to the second input terminal (304), the second electronic switch having a control terminal (342) that is coupled to the fifth node (318), wherein the second electronic switch is operable, in response to a line-sag condition, to turn on and to thereby turn off the first electronic switch (Ml); a third electronic switch (M3) operably coupled between the second node (312) and circuit ground (320), the third electronic switch having a control terminal (352) that is coupled to the fourth node, wherein the third electronic switch is operable, in response to a line- sage condition, to turn off and to thereby allow the second electronic switch (M2) to turn on; and a fourth electronic switch (M4) operably coupled between the first node (310) and circuit ground (320), the fourth electronic switch having a control terminal (362) that is coupled to a third node (314), wherein the fourth electronic switch is operable, in response to a phase-to-phase miswiring fault condition, to turn on and to thereby turn off the first electronic switch (Ml).

10. The circuit of claim 9, wherein the auxiliary protection circuit (300) further comprises: a first resistor (Rl) coupled between the first input terminal (302) and the first node (310); a second resistor (R2) coupled between the first node (310) and circuit ground (320); a first capacitor (Cl) coupled between the first node (310) and circuit ground (320); a third resistor (R3) coupled between the first input terminal (302) and the second node (312); a fourth resistor (R4) coupled between the second node (312) and the third node (314); a second capacitor (C2) coupled between the second node (312) and circuit ground (320); a fifth resistor (R5) coupled between the third node (314) and circuit ground (320); a sixth resistor (R6) coupled between the second node (312) and the fourth node (316); a seventh resistor (R7) coupled between the fourth node (316) and circuit ground (320); and an eighth resistor (R8) coupled between the second node (312) and the fifth node (318).

11. The circuit of claim 9, wherein the first electronic switch (Ml) comprises a N-channel field-effect transistor having a gate terminal (332), a drain terminal (334), and a source terminal (336), wherein the gate terminal (332) is the control terminal and is coupled to the first node (310), the drain terminal (334) is coupled to the second output terminal (308), and the source terminal (336) is coupled to the second input terminal (304)

12. The circuit of claim 9, wherein the second electronic switch (M2) comprises a N-channel field-effect transistor having a gate terminal (342), a drain terminal (344), and a source terminal (346), wherein the gate terminal (342) is the control terminal and is coupled to the fifth node (318), the drain terminal (344) is coupled to the first node (310), and the source terminal (346) is coupled to circuit ground (320).

13. The circuit of claim 9, wherein the third electronic switch (M3) comprises a N-channel field-effect transistor having a gate terminal (352), a drain terminal (354), and a source terminal (356), wherein the gate terminal (352) is the control terminal and is coupled to the fourth node (316), the drain terminal (354) is coupled to the fifth node (318), and the source terminal (356) is coupled to circuit ground (320).

14. The circuit of claim 9, wherein the fourth electronic switch (M4) comprises a N-channel field-effect transistor having a gate terminal (362), a drain terminal (364), and a source terminal (366), wherein the gate terminal (362) is the control terminal and is coupled to the third node (314), the drain terminal (364) is coupled to the first node (310), and the source terminal (366) is coupled to circuit ground (320).

15. The circuit of claim 9, wherein the load comprises at least one gas discharge lamp.

16. An electronic ballast for powering at least one gas discharge lamp, comprising: a front-end circuit (100) having first and second input connections (12,14) adapted to receive a conventional source of alternating current (AC) voltage (20); a back-end circuit (200) operably coupled to the front-end circuit (100) and operable to deliver power to a load; an auxiliary protection circuit (300), comprising: first and second input terminals (302,304) coupled to the front-end circuit (100); first and second output terminals (306,308) coupled to the back-end circuit (200); first, second, third, fourth, and fifth nodes (310,312,314,316,318); a first electronic switch (Ml) operably coupled between the second input terminal (304) and the second output terminal (308), the first electronic switch having a control terminal (332) coupled to the first node (310); a second electronic switch (M2) operably coupled between the first node (310) and circuit ground (320), wherein circuit ground (320) is coupled to the second input terminal (304), the second electronic switch having a control terminal (342) that is coupled to the fifth node (318), wherein the second electronic switch is operable, in response to a line-sag condition, to turn on and to thereby turn off the first electronic switch (Ml); a third electronic switch (M3) operably coupled between the second node (312) and circuit ground (320), the third electronic switch having a control terminal (352) that is coupled to the fourth node, wherein the third electronic switch is operable, in response to a line- sage condition, to turn off and to thereby allow the second electronic switch (M2) to turn on; and a fourth electronic switch (M4) operably coupled between the first node (310) and circuit ground (320), the fourth electronic switch having a control terminal (362) that is coupled to a third node (314), wherein the fourth electronic switch is operable, in response to a phase-to-phase miswiring fault condition, to turn on and to thereby turn off the first electronic switch (Ml).

17. The electronic ballast of claim 16, wherein the auxiliary protection circuit (300) further comprises: a first resistor (Rl) coupled between the first input terminal (302) and the first node (310); a second resistor (R2) coupled between the first node (310) and circuit ground (320); a first capacitor (Cl) coupled between the first node (310) and circuit ground (320); a third resistor (R3) coupled between the first input terminal (302) and the second node (312); a fourth resistor (R4) coupled between the second node (312) and the third node (314); a second capacitor (C2) coupled between the second node (312) and circuit ground (320); a fifth resistor (R5) coupled between the third node (314) and circuit ground (320); a sixth resistor (R6) coupled between the second node (312) and the fourth node (316); a seventh resistor (R7) coupled between the fourth node (316) and circuit ground (320); and an eighth resistor (R8) coupled between the second node (312) and the fifth node (318).

18. The electronic ballast of claim 17, wherein: the first electronic switch (Ml) comprises a N-channel field-effect transistor having a gate terminal (332), a drain terminal (334), and a source terminal (336), wherein the gate terminal (332) is the control terminal and is coupled to the first node (310), the drain terminal (334) is coupled to the second output terminal (308), and the source terminal (336) is coupled to the second input terminal (304); the second electronic switch (M2) comprises a N-channel field-effect transistor having a gate terminal (342), a drain terminal (344), and a source terminal (346), wherein the gate terminal (342) is the control terminal and is coupled to the fifth node (318), the drain terminal (344) is coupled to the first node (310), and the source terminal (346) is coupled to circuit ground (320); the third electronic switch (M3) comprises a N-channel field-effect transistor having a gate terminal (352), a drain terminal (354), and a source terminal (356), wherein the gate terminal (352) is the control terminal and is coupled to the fourth node (316), the drain terminal (354) is coupled to the fifth node (318), and the source terminal (356) is coupled to circuit ground (320); and the fourth electronic switch (M4) comprises a N-channel field-effect transistor having a gate terminal (362), a drain terminal (364), and a source terminal (366), wherein the gate terminal (362) is the control terminal and is coupled to the third node (314), the drain terminal (364) is coupled to the first node (310), and the source terminal (366) is coupled to circuit ground (320).