EP2049967A2 - Controlled frequency core processor and method for starting-up said core processor in a programmed manner - Google Patents

Controlled frequency core processor and method for starting-up said core processor in a programmed manner

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Publication number
EP2049967A2
EP2049967A2 EP07787400A EP07787400A EP2049967A2 EP 2049967 A2 EP2049967 A2 EP 2049967A2 EP 07787400 A EP07787400 A EP 07787400A EP 07787400 A EP07787400 A EP 07787400A EP 2049967 A2 EP2049967 A2 EP 2049967A2
Authority
EP
European Patent Office
Prior art keywords
interface component
mode
processor core
processor
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP07787400A
Other languages
German (de)
French (fr)
Inventor
Jean Michel Titone
Michel Coignard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thales SA
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Filing date
Publication date
Application filed by Thales SA filed Critical Thales SA
Publication of EP2049967A2 publication Critical patent/EP2049967A2/en
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • C—CHEMISTRY; METALLURGY
    • C07—ORGANIC CHEMISTRY
    • C07D—HETEROCYCLIC COMPOUNDS
    • C07D401/00—Heterocyclic compounds containing two or more hetero rings, having nitrogen atoms as the only ring hetero atoms, at least one ring being a six-membered ring with only one nitrogen atom
    • C07D401/02—Heterocyclic compounds containing two or more hetero rings, having nitrogen atoms as the only ring hetero atoms, at least one ring being a six-membered ring with only one nitrogen atom containing two hetero rings
    • C07D401/12—Heterocyclic compounds containing two or more hetero rings, having nitrogen atoms as the only ring hetero atoms, at least one ring being a six-membered ring with only one nitrogen atom containing two hetero rings linked by a chain containing hetero atoms as chain links
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means

Definitions

  • the invention relates to a frequency-controlled processor core and a method of starting said processor core in a programmed mode.
  • the invention applies to processor cores embedded in aircraft.
  • a processor core also known as the CPU card, is an onboard electronic card comprising a processor performing calculations and treatments.
  • a processor core may in particular be embedded in an aircraft type system where it performs a set of specific numerical calculations.
  • a processor core particularly in the aeronautical field, performs tasks of great criticality, such as the management of flight parameters, and must therefore have significant reliability.
  • a processor core is defined by a detailed definition file and validated, and must be the subject of a validation / certification phase both conceptually and materially. It follows in particular that each modification of a characteristic of said processor core must be subject to an evolution of the definition file followed by a study of risk and / or impact on its reliability and those of related equipment.
  • one of the characteristics of a processor core that can be modified not only during the design phase but also during the life cycle of said core is the frequency of the components included in the processor core.
  • the modification of the frequency of the components included in the processor core is generally referred to as the "clamping / unclamping" of a processor core.
  • it is desirable that the "clamping / unclamping" of the processor core can be performed without hardware modification ("without hardware retrofit").
  • BIOS basic input / output systems
  • this solution does not have sufficient security and reliability characteristics for an embedded processor core. Indeed, if an erroneous value is written via the BIOS before restarting the computer, it will be unable to start again and will be in an unstable and unpredictable state.
  • the subject of the invention is a processor core comprising at least one processor, a non-volatile memory comprising a startup program, a bridge interconnecting buses connecting the different components of said processor core.
  • the processor core comprises an interface component, a non-volatile memory comprising at least two frequency configurations each corresponding to a mode of operation of the buses and / or components of said processor core.
  • the nonvolatile memory includes information to determine which mode of operation should be used. Said information is read by the interface component to determine the chosen mode.
  • the interface component generates one or more clock signals. The frequency of said generated clock signals substantially corresponds to that described by the configuration of the chosen mode.
  • the clock signals drive the buses and / or the components of said processor core.
  • the interface component when the reading by the interface component of the information on the selected mode proves impossible or erroneous, the interface component is adapted to choose a default mode.
  • the processor core comprises a clock delivering a reference clock signal. The frequency of said reference clock signal is then multiplied by the interface component to generate the signals whose frequency corresponding substantially to that described by the configuration of the chosen mode.
  • the processor core may receive a protection signal, said signal authorizing or not depending on its value the writing of information to determine which mode of operation should be used.
  • the information to determine which operating mode should be used is for example modifiable by programming the non-volatile memory and / or the processor.
  • the invention also relates to a method for starting a processor core comprising at least one non-volatile memory comprising a startup program, a bridge interconnecting buses connecting the various components of said processor core, an interface component, the memory non-volatile having at least two frequency configurations each corresponding to a mode of operation of the buses and / or components of said processor core.
  • the non-volatile memory includes information to determine which mode of operation is to be used, said information being read by the interface component to determine the mode chosen.
  • the method comprises the following steps: a power-up step of the processor core, the components of the processor core being held by the interface component in an inhibited state; a step where the interface component prohibits the resetting of the non-volatile memory; a read access step by the interface component to the information relating to the selected operating mode and the associated configuration contained in the non-volatile memory; a step of generation by the interface component of one or more signals whose frequency corresponds to the configuration of the selected mode, said signals driving the buses and / or the components of said processor core; o a step of disinhibition by the interface component of the different components.
  • the method includes a delay step until the reference clock signal satisfies certain defined stability criteria.
  • the interface component chooses at the step in place of inaccessible or erroneous information a default mode.
  • the method includes a delay step until the buses reach stably their target frequency.
  • the latter determines multiplicative factors to be applied to the frequency of a reference clock signal to obtain one or more signals of which the frequency corresponds to that described in the configuration corresponding to the selected mode.
  • the advantages of the invention include that it makes it possible to secure and make reliable the management of bus frequency changes. It can be totally managed at the hardware level of the processor core.
  • the invention allows a hardware check of the restart configuration with a still valid default configuration, even if the storage area of the configuration is erased.
  • FIG. 1 a block diagram of the processor core according to the invention
  • FIG. 2 a diagram of a process for starting the processor core in a programmed mode according to the invention
  • FIG. 1 shows a block diagram of a processor core according to the invention.
  • the frequency-controlled processor core according to the invention comprises in particular at least one processor 1.
  • the processor 1 is particularly suitable for performing numerical calculations.
  • the processor 1 communicates via at least one processor bus 10 to the other components of the processor core.
  • the processor core may also comprise RAM 3, for example DDR-SDRAM type memory.
  • the RAM 3 is accessible via a memory bus 1 1.
  • the processor core may also include external buses 13, such as one or more PCI buses.
  • the processor core comprises a nonvolatile memory 4 comprising the startup program.
  • the non-volatile memory 4 may for example be a FLASH memory bank.
  • the processor core comprises an interface component 6 between a clock 5 (for example, a quartz), a multiplexed peripheral bus 1 1 to which is connected in particular the nonvolatile memory 4 comprising the startup program, and possibly a signal of protection 7 of the startup program.
  • the interface component 6 may be a programmable component.
  • the processor core comprises a bridge 2 responsible for managing and interconnecting the buses of said core.
  • the startup program included in the nonvolatile memory 4 includes the instructions necessary to start the processor core.
  • the non-volatile memory 4 comprises at least two frequency configurations, each corresponding to a mode of operation of the buses and / or components of the processor core: a bridled mode, an unbridled mode.
  • the operating frequency of the buses in unbridled mode is greater or equal to the flanged mode.
  • the nonvolatile memory 4 comprises information, contained for example in memory locations, for determining which mode of operation should be used for the next start of the processor core.
  • the configuration relating to a given operating mode describes in particular the frequency at which the buses must operate and possibly, if relevant, the components of the processor core.
  • the protection signal 7 authorizes or not according to its value the writing of the information to determine which mode of operation should be used. For example, when the protection signal 7 is received, it is possible to read but not to write the information to determine which mode of operation should be used. Conversely, when the protection signal 7 is not received, it is possible to write said information.
  • the information to determine which operating mode is to be used can be modified by programming the nonvolatile memory 4 and / or the processor 1.
  • the interface component 6 receives a reference clock signal 5 from the clock.
  • the interface component 6 reads the information on the chosen mode included in the non-volatile memory 4. If the reading of the information on the chosen mode proves impossible or erroneous (the detection can for example be ensured by a mechanism cyclic redundancy check or Cyclic Redundancy Check or by checking the membership of the read values to a predefined value range), the interface component 6 selects a mode by default, corresponding, for example, to the lowest frequency of the different buses and / or components of the processor core. The default mode can in particular be programmed within the interface component 6. This mechanism provides an additional level of security, in particular avoiding the use of a value entered by mistake or inaccurate in the non-volatile memory.
  • the interface component 6 generates one or more clock signals from the reference clock signal 5. These clock signals generated have a frequency corresponding to that described in the configuration of the selected mode. These generated clock signals are used to drive the buses and / or components of the processor core. These clock signals will then be used for each bus and / or component and will then determine their operating frequency. Thus, if the configuration describing the flanged mode corresponds to an operating frequency of 100 MHz for the processor bus 10, the memory bus 1 1, the interface component will generate a signal of frequency substantially equal to 100 MHz, thus forcing the processor 1, the processor bus 10, the RAM 3 and the memory bus 1 1 to operate at 100 MHz.
  • the interface component will generate a frequency signal substantially equal to 133 MHz, thus forcing the processor 1 , the processor bus 10, the RAM 3 and the memory bus 11 to operate at 133 MHz. It is of course possible to define, if the processor core can support it moreover, different bus frequencies for the same mode given according to the components, and to operate the memory bus 1 1 at a different speed of the processor bus 1.
  • FIG. 2 schematically illustrates a method for starting the processor core in a programmed mode according to the invention.
  • the starting method according to the invention describes the starting sequence of a processor core according to the invention (for example, that illustrated in FIG. 1) in a given operating mode.
  • the processor core is powered on.
  • the core processor components (such as the processor 1, the bridge 2, ...) are maintained in an inhibited state (or according to the English expression "reset").
  • a step 21 delays until the clock signal from clock 5 meets certain defined stability criteria.
  • the interface component 6 prohibits in a step 22 the resetting of the nonvolatile memory 4 comprising the startup program.
  • the interface component 6 reads the information contained in the non-volatile memory 4, in particular the selected operating mode and the associated configuration. If the reading by the interface component 6 of the information on the chosen mode proves to be impossible or erroneous, the interface component 6 chooses in step 23 instead of the inaccessible or erroneous information a default mode, corresponding for example to the lowest frequency of the various buses and / or components of the processor core. From this information, in a step 24, the interface component 6 generates one or more signals whose frequency corresponds to the configuration of the selected mode, said signals driving the buses and / or the components of said processor core.
  • the interface component determines the multiplicative factor to be applied to the frequency of the clock signal 5 to obtain a signal whose frequency corresponds to the configuration corresponding to the selected mode.
  • this multiplicative factor depends on the configuration of the selected mode and is therefore different depending on whether the active mode selected is the bridled mode or the unbridled mode.
  • the interface component 6 From this multiplicative factor, the interface component 6 generates a signal whose frequency corresponds to the configuration of the selected mode. This signal is then used by the different buses of the processor core. In a delay step, a time delay makes it possible to wait for the buses to stably reach their target frequency.
  • the interface component 6 disinhibits the various components (processor 1, bridge 2, ...), in a step 26.
  • the processor 1, the bridge 2, the buses, and the other components can then start in a step 27 in the selected mode, flanged or not.
  • the processor core can then be used by the operating system in the selected operating mode.
  • the operating mode can be changed to another mode. To make this change, it is possible for example to remove the protection of the non-volatile memory containing the startup program by modifying the input protection signal 7 to allow writing.
  • the chosen mode can then be re-registered either by programming (for example by using a JTAG type cable) or by the processor 1.
  • the new configuration will only be taken into account after a power failure.

Abstract

The invention concerns a controlled frequency core processor. It comprises at least one processor, a non-volatile memory comprising a start-up program, a bridge interconnecting the busses which link the different components of said core processor, an interface component. The non-volatile memory comprises at least two corresponding configurations with respect to the frequency, each of which has a mode of operation of the busses and/ or of the components of said core processor. The non-volatile memory comprises an information which allows for determining which mode of operation has to be used, wherein said information is read by the interface component in order to determine the selected mode. The interface component generates one or several clock signals. The frequency of said clock signals generated substantially corresponds to the one described by the configuration of the selected mode. The clock signals control the busses and/ or the components of said core processor. The invention also concerns a method for starting-up said core processor in a programmed manner. In particular, the invention is applied to core processors installed in an aircraft.

Description

Cœur processeur à fréquence pi lotée et procédé de démarrage dudit cœur processeu r dans u n mode programmé. Heart processor frequency pi lotée and method of starting said processor heart in a n mode programmed.
L'invention concerne un cœur processeur à fréquence pilotée ainsi qu'un procédé de démarrage dudit cœur processeur dans un mode programmé. En particulier, l'invention s'applique aux cœurs processeurs embarqués dans des aéronefs.The invention relates to a frequency-controlled processor core and a method of starting said processor core in a programmed mode. In particular, the invention applies to processor cores embedded in aircraft.
Un cœur processeur, connu aussi sous le nom de carte CPU, est une carte électronique embarquée comportant un processeur réalisant des calculs et des traitements. A titre d'exemple, un cœur processeur peut notamment être embarqué dans un système de type aéronef où il effectue un ensemble de calculs numériques spécifiques. Un cœur processeur, particulièrement dans le domaine aéronautique, réalise des tâches d'une grande criticité, comme par exemple la gestion des paramètres de vol, et doit en conséquence présenter une fiabilité importante. Pour répondre à ces contraintes, un cœur processeur est défini par un dossier de définition détaillé et validé, et doit faire l'objet d'une phase de validation/certification tant sur le plan conceptuel que matériel. Il en résulte notamment que chaque modification d'une caractéristique dudit cœur processeur doit faire l'objet d'une évolution du dossier de définition suivie d'une étude de risque et/ou d'impact sur sa fiabilité et celles des équipements connexes. Il est bien sûr à noter que de telles études ont un impact significatif sur le coût du cœur processeur. Dans ce contexte, une des caractéristiques d'un cœur processeur susceptible de modification non seulement en phase de conception mais aussi au cours du cycle de vie dudit cœur est la fréquence des composants compris dans le cœur processeur. La modification de la fréquence des composants compris dans le cœur processeur est généralement désigner par le terme de « Bridage / Débridage » d'un cœur processeur. En outre, en relation avec les contraintes préalablement énoncées, il est souhaitable que le « Bridage / Débridage » du cœur processeur puisse s'effectuer sans modification matérielle (« sans retrofit Hardware »).A processor core, also known as the CPU card, is an onboard electronic card comprising a processor performing calculations and treatments. For example, a processor core may in particular be embedded in an aircraft type system where it performs a set of specific numerical calculations. A processor core, particularly in the aeronautical field, performs tasks of great criticality, such as the management of flight parameters, and must therefore have significant reliability. To meet these constraints, a processor core is defined by a detailed definition file and validated, and must be the subject of a validation / certification phase both conceptually and materially. It follows in particular that each modification of a characteristic of said processor core must be subject to an evolution of the definition file followed by a study of risk and / or impact on its reliability and those of related equipment. It is of course worth noting that such studies have a significant impact on the cost of the core processor. In this context, one of the characteristics of a processor core that can be modified not only during the design phase but also during the life cycle of said core is the frequency of the components included in the processor core. The modification of the frequency of the components included in the processor core is generally referred to as the "clamping / unclamping" of a processor core. In addition, in relation to the previously stated constraints, it is desirable that the "clamping / unclamping" of the processor core can be performed without hardware modification ("without hardware retrofit").
Il est connu, pour réaliser un « Bridage / Débridage » d'un cœur processeur, d'inclure dans celui-ci des composants multiplicateurs de fréquence (PLL), et/ou des pilotes d'horloges comprenant des cavaliers (« Clock drivers par pull-up/pull-down »). Malheureusement, une mise à jour (« retrofit ») matérielle est inévitable pour réaliser le changement de fréquence du cœur processeur. Ce qui se traduit notamment par une impossibilité de changement dynamique (c'est-à-dire en cours de fonctionnement) de configuration, ainsi que les inconvénients préalablement exposés.It is known, to perform a "clamping / unclamping" of a processor core, to include in it frequency multiplying components (PLL), and / or clock drivers including jumpers ("Clock drivers by pull-up / pull-down"). Unfortunately, a hardware "retrofit" is inevitable to achieve the frequency change of the processor core. This is reflected in particular by an impossibility of dynamic change (that is to say during operation) of configuration, as well as the disadvantages previously exposed.
Dans le domaine informatique en particulier celui des ordinateurs personnels, les systèmes de base d'entrée/sortie (BIOS) peuvent être pourvus dans certains cas d'un dispositif intégré à la carte mère permettant de changer la fréquence processeur et la fréquence bus. Cependant cette solution ne présente pas des caractéristiques de sécurité et fiabilité suffisante pour un cœur processeur embarqué. En effet, si une valeur erronée est écrite via le BIOS avant le redémarrage de l'ordinateur, celui-ci sera incapable de démarrer à nouveau et sera dans un état instable et imprévisible.In the computer field in particular that of personal computers, basic input / output systems (BIOS) can be provided in some cases with a device integrated in the motherboard for changing the processor frequency and the bus frequency. However, this solution does not have sufficient security and reliability characteristics for an embedded processor core. Indeed, if an erroneous value is written via the BIOS before restarting the computer, it will be unable to start again and will be in an unstable and unpredictable state.
L'invention a notamment pour but de pallier les inconvénients précités. A cet effet, l'invention a pour objet un cœur processeur comportant au moins un processeur, une mémoire non volatile comprenant un programme de démarrage, un pont interconnectant des bus reliant les différents composants dudit cœur processeur. Le cœur processeur comporte un composant d'interface, une mémoire non volatile comportant au moins deux configurations en fréquence correspondant chacune à un mode de fonctionnement des bus et/ou des composants dudit cœur processeur. La mémoire non volatile comporte une information permettant de déterminer quel mode de fonctionnement doit être utilisé. Ladite information est lue par le composant d'interface pour déterminer le mode choisi. Le composant d'interface génère un ou plusieurs signaux d'horloge. La fréquence desdits signaux d'horloge générés correspond sensiblement à celle décrite par la configuration du mode choisi. Les signaux d'horloge pilotent les bus et/ou les composants dudit cœur processeur.The purpose of the invention is in particular to overcome the aforementioned drawbacks. For this purpose, the subject of the invention is a processor core comprising at least one processor, a non-volatile memory comprising a startup program, a bridge interconnecting buses connecting the different components of said processor core. The processor core comprises an interface component, a non-volatile memory comprising at least two frequency configurations each corresponding to a mode of operation of the buses and / or components of said processor core. The nonvolatile memory includes information to determine which mode of operation should be used. Said information is read by the interface component to determine the chosen mode. The interface component generates one or more clock signals. The frequency of said generated clock signals substantially corresponds to that described by the configuration of the chosen mode. The clock signals drive the buses and / or the components of said processor core.
Avantageusement, lorsque la lecture par le composant d'interface de l'information sur le mode choisie s'avère impossible ou erronée, le composant d'interface est adapté à choisir un mode par défaut. Dans un mode de réalisation, le cœur processeur comporte une horloge délivrant un signal d'horloge de référence. La fréquence dudit signal d'horloge de référence est alors multiplié par le composant d'interface pour générer les signaux dont la fréquence correspondant sensiblement à celle décrite par la configuration du mode choisi.Advantageously, when the reading by the interface component of the information on the selected mode proves impossible or erroneous, the interface component is adapted to choose a default mode. In one embodiment, the processor core comprises a clock delivering a reference clock signal. The frequency of said reference clock signal is then multiplied by the interface component to generate the signals whose frequency corresponding substantially to that described by the configuration of the chosen mode.
Le cœur processeur peut recevoir un signal de protection, ledit signal autorisant ou non en fonction de sa valeur l'écriture de l'information permettant de déterminer quel mode de fonctionnement doit être utilisé. L'information permettant de déterminer quel mode de fonctionnement doit être utilisé est par exemple modifiable par programmation de la mémoire non volatile et/ou par le processeur.The processor core may receive a protection signal, said signal authorizing or not depending on its value the writing of information to determine which mode of operation should be used. The information to determine which operating mode should be used is for example modifiable by programming the non-volatile memory and / or the processor.
L'invention a aussi pour objet un procédé de démarrage d'un cœur processeur comportant au moins une mémoire non volatile comprenant un programme de démarrage, un pont interconnectant des bus reliant les différents composants dudit cœur processeur, un composant d'interface, la mémoire non volatile comportant au moins deux configurations en fréquence correspondant chacune à un mode de fonctionnement des bus et/ou des composants dudit cœur processeur. La mémoire non volatile comporte une information permettant de déterminer quel mode de fonctionnement doit être utilisé, ladite information étant lue par le composant d'interface pour déterminer le mode choisi. Le procédé comporte les étapes suivantes : o une étape de mise sous tension du cœur processeur, les composants du cœur processeur étant maintenus par le composant d'interface dans un état inhibé ; o une étape où le composant d'interface interdit la remise à zéro de la mémoire non volatile ; o une étape d'accès en lecture par le composant d'interface aux informations relatives au mode de fonctionnement sélectionné et la configuration associée contenus dans la mémoire non volatile ; o une étape de génération par le composant d'interface d'un ou plusieurs signaux dont la fréquence correspond à la configuration du mode sélectionné, lesdits signaux pilotant les bus et/ou les composants dudit cœur processeur ; o une étape de désinhibition par le composant d'interface des différents composants.The invention also relates to a method for starting a processor core comprising at least one non-volatile memory comprising a startup program, a bridge interconnecting buses connecting the various components of said processor core, an interface component, the memory non-volatile having at least two frequency configurations each corresponding to a mode of operation of the buses and / or components of said processor core. The non-volatile memory includes information to determine which mode of operation is to be used, said information being read by the interface component to determine the mode chosen. The method comprises the following steps: a power-up step of the processor core, the components of the processor core being held by the interface component in an inhibited state; a step where the interface component prohibits the resetting of the non-volatile memory; a read access step by the interface component to the information relating to the selected operating mode and the associated configuration contained in the non-volatile memory; a step of generation by the interface component of one or more signals whose frequency corresponds to the configuration of the selected mode, said signals driving the buses and / or the components of said processor core; o a step of disinhibition by the interface component of the different components.
Avantageusement, après l'étape de mise sous tension du cœur processeur, le procédé comporte une étape de temporisation jusqu'à ce que le signal d'horloge de référence réponde à certains critères définis de stabilité.Advantageously, after the processor core power-up step, the method includes a delay step until the reference clock signal satisfies certain defined stability criteria.
Avantageusement, si la lecture par le composant d'interface de l'information sur le mode choisie à l'étape d'accès en lecture s'avère impossible ou erronée, le composant d'interface choisit à l'étape en lieu et place de l'information non accessible ou erronée un mode par défaut.Advantageously, if the reading by the interface component of the information on the mode chosen at the read access step proves impossible or erroneous, the interface component chooses at the step in place of inaccessible or erroneous information a default mode.
Dans un mode de réalisation, après l'étape de génération par le composant d'interface d'un ou plusieurs signaux dont la fréquence correspond à la configuration du mode sélectionné, le procédé comporte une étape de temporisation jusqu'à ce que les bus atteignent de manière stable leur fréquence cible.In one embodiment, after the step of generating by the interface component one or more signals whose frequency corresponds to the configuration of the selected mode, the method includes a delay step until the buses reach stably their target frequency.
Dans un autre mode de réalisation, à l'étape de génération de signaux par le composant d'interface, celui-ci détermine des facteurs multiplicatifs à appliquer à la fréquence d'un signal d'horloge de référence pour obtenir un ou plusieurs signaux dont la fréquence correspond celle décrite dans la configuration correspondant au mode sélectionné.In another embodiment, at the signal generation step by the interface component, the latter determines multiplicative factors to be applied to the frequency of a reference clock signal to obtain one or more signals of which the frequency corresponds to that described in the configuration corresponding to the selected mode.
L'invention a notamment pour avantages qu'elle permet de sécuriser et de fiabiliser la gestion des changements de fréquences bus. Elle peut être totalement gérée au niveau matériel du cœur processeur. L'invention autorise un contrôle matériel de la configuration de redémarrage avec une configuration par défaut toujours valide, y compris en cas d'effacement de la zone de mémorisation de la configuration. D'autres caractéristiques et avantages de l'invention apparaîtront à l'aide de la description qui suit faite en regard des dessins annexés qui représentent :The advantages of the invention include that it makes it possible to secure and make reliable the management of bus frequency changes. It can be totally managed at the hardware level of the processor core. The invention allows a hardware check of the restart configuration with a still valid default configuration, even if the storage area of the configuration is erased. Other characteristics and advantages of the invention will become apparent with the aid of the following description made with reference to the appended drawings which represent:
• la figure 1 , un synoptique du cœur processeur selon l'invention ;FIG. 1, a block diagram of the processor core according to the invention;
• la figure 2, un schéma d'un procédé de démarrage du cœur processeur dans un mode programmé selon l'invention;FIG. 2, a diagram of a process for starting the processor core in a programmed mode according to the invention;
La figure 1 montre par un synoptique un cœur processeur selon l'invention. Le cœur processeur à fréquence pilotée selon l'invention comporte notamment au moins un processeur 1 . Le processeur 1 est adapté notamment à effectuer des calculs numériques. Le processeur 1 communique via au moins un bus processeur 10 vers les autres composants du cœur processeur. Le cœur processeur peut encore comporter de la mémoire vive 3, par exemple de la mémoire de type DDR-SDRAM. La mémoire vive 3 est accessible par l'intermédiaire d'un bus mémoire 1 1 . Le cœur processeur peut aussi comporter des bus extérieurs 13, comme par exemple un ou plusieurs bus PCI. Le cœur processeur comporte une mémoire non volatile 4 comportant le programme de démarrage. La mémoire non volatile 4 peut par exemple être un banc de mémoires FLASH. Le cœur processeur comporte un composant d'interface 6 entre une horloge 5 (par exemple, un quartz), un bus de périphérique multiplexe 1 1 sur lequel est connecté notamment la mémoire non volatile 4 comportant le programme de démarrage, et éventuellement un signal de protection 7 du programme de démarrage. Le composant d'interface 6 peut être un composant programmable. Le cœur processeur comporte un pont 2 chargé de gérer et d'interconnecter les bus dudit cœur.FIG. 1 shows a block diagram of a processor core according to the invention. The frequency-controlled processor core according to the invention comprises in particular at least one processor 1. The processor 1 is particularly suitable for performing numerical calculations. The processor 1 communicates via at least one processor bus 10 to the other components of the processor core. The processor core may also comprise RAM 3, for example DDR-SDRAM type memory. The RAM 3 is accessible via a memory bus 1 1. The processor core may also include external buses 13, such as one or more PCI buses. The processor core comprises a nonvolatile memory 4 comprising the startup program. The non-volatile memory 4 may for example be a FLASH memory bank. The processor core comprises an interface component 6 between a clock 5 (for example, a quartz), a multiplexed peripheral bus 1 1 to which is connected in particular the nonvolatile memory 4 comprising the startup program, and possibly a signal of protection 7 of the startup program. The interface component 6 may be a programmable component. The processor core comprises a bridge 2 responsible for managing and interconnecting the buses of said core.
Le programme de démarrage compris dans la mémoire non volatile 4 comprend les instructions nécessaires au démarrage du cœur processeur. La mémoire non volatile 4 comporte au moins deux configurations en fréquence, correspondant chacune à un mode de fonctionnement des bus et/ou des composants du cœur processeur : un mode bridé, un mode débridé. La fréquence de fonctionnement des bus en mode débridé est supérieure, voire égale, au mode bridé. La mémoire non volatile 4 comprend une information, contenue par exemple dans des emplacements mémoires, permettant de déterminer quel mode de fonctionnement doit être utilisé pour le prochain démarrage du cœur processeur. La configuration relative à un mode de fonctionnement donné décrit notamment la fréquence à laquelle doivent fonctionner les bus et éventuellement, si cela s'avère pertinent, les composants du cœur processeur. Le signal de protection 7 autorise ou non en fonction de sa valeur l'écriture de l'information permettant de déterminer quel mode de fonctionnement doit être utilisé. Par exemple, lorsque le signal de protection 7 est reçu, il est possible lire mais pas d'écrire l'information permettant de déterminer quel mode de fonctionnement doit être utilisé. Réciproquement, lorsque le signal de protection 7 n'est pas reçu, il est possible d'écrire ladite information. L'information permettant de déterminer quel mode de fonctionnement doit être utilisé est modifiable par programmation de la mémoire non volatile 4 et/ou par le processeur 1.The startup program included in the nonvolatile memory 4 includes the instructions necessary to start the processor core. The non-volatile memory 4 comprises at least two frequency configurations, each corresponding to a mode of operation of the buses and / or components of the processor core: a bridled mode, an unbridled mode. The operating frequency of the buses in unbridled mode is greater or equal to the flanged mode. The nonvolatile memory 4 comprises information, contained for example in memory locations, for determining which mode of operation should be used for the next start of the processor core. The configuration relating to a given operating mode describes in particular the frequency at which the buses must operate and possibly, if relevant, the components of the processor core. The protection signal 7 authorizes or not according to its value the writing of the information to determine which mode of operation should be used. For example, when the protection signal 7 is received, it is possible to read but not to write the information to determine which mode of operation should be used. Conversely, when the protection signal 7 is not received, it is possible to write said information. The information to determine which operating mode is to be used can be modified by programming the nonvolatile memory 4 and / or the processor 1.
Le composant d'interface 6 reçoit un signal d'horloge de référence 5 provenant de l'horloge. Le composant d'interface 6 lit l'information sur le mode choisi comprise dans la mémoire non volatile 4. Si la lecture de l'information sur le mode choisie s'avère impossible ou erronée (la détection pouvant par exemple être assurer par un mécanisme de contrôle d'erreur de type contrôle de redondance cyclique ou selon l'expression anglo-saxonne Cyclic Redundancy Check ou encore par vérification de l'appartenance des valeurs lues à une plage de valeur prédéfinie), le composant d'interface 6 choisit un mode par défaut, correspondant par exemple à la fréquence la plus basse des différents bus et/ou composants du cœur processeur. Le mode par défaut peut notamment être programmé au sein même du composant d'interface 6. Ce mécanisme assure un niveau de sécurité supplémentaire, évitant notamment l'utilisation d'une valeur inscrite par erreur ou inexacte dans la mémoire non volatile 4. En fonction du mode sélectionné et de la configuration associée compris dans la mémoire non volatile 4, le composant d'interface 6 génère un ou plusieurs signaux d'horloge à partir du signal d'horloge de référence 5. Ces signaux d'horloges générés ont une fréquence correspondant sensiblement à celle décrite dans la configuration du mode sélectionné. Ces signaux d'horloge générés servent à piloter les bus et/ou les composants du cœur processeur. Ces signaux d'horloge seront alors utilisés pour chaque bus et/ou composant et détermineront alors leur fréquence de fonctionnement. Ainsi, si la configuration décrivant le mode bridé correspond à une fréquence de fonctionnement de 100 MHz pour le bus processeur 10, le bus mémoire 1 1 , le composant d'interface générera un signal de fréquence sensiblement égal à 100 MHz, forçant ainsi le processeur 1 , le bus processeur 10, la mémoire vive 3 et le bus mémoire 1 1 à fonctionner à 100 MHz. Ainsi, si la configuration décrivant le mode débridé correspond à une fréquence de fonctionnement de 133 MHz pour le bus processeur 10, le bus mémoire 11 , le composant d'interface générera un signal de fréquence sensiblement égal à 133 MHz, forçant ainsi le processeur 1 , le bus processeur 10, la mémoire vive 3 et le bus mémoire 11 à fonctionner à 133 MHz. Il est bien entendu possible de définir, si le cœur processeur peut le supporter par ailleurs, des fréquences de bus différentes pour un même mode donné selon les composants, et faire fonctionner le bus mémoire 1 1 à une vitesse différente du bus processeur 1.The interface component 6 receives a reference clock signal 5 from the clock. The interface component 6 reads the information on the chosen mode included in the non-volatile memory 4. If the reading of the information on the chosen mode proves impossible or erroneous (the detection can for example be ensured by a mechanism cyclic redundancy check or Cyclic Redundancy Check or by checking the membership of the read values to a predefined value range), the interface component 6 selects a mode by default, corresponding, for example, to the lowest frequency of the different buses and / or components of the processor core. The default mode can in particular be programmed within the interface component 6. This mechanism provides an additional level of security, in particular avoiding the use of a value entered by mistake or inaccurate in the non-volatile memory. of the selected mode and the associated configuration included in the non-volatile memory 4, the interface component 6 generates one or more clock signals from the reference clock signal 5. These clock signals generated have a frequency corresponding to that described in the configuration of the selected mode. These generated clock signals are used to drive the buses and / or components of the processor core. These clock signals will then be used for each bus and / or component and will then determine their operating frequency. Thus, if the configuration describing the flanged mode corresponds to an operating frequency of 100 MHz for the processor bus 10, the memory bus 1 1, the interface component will generate a signal of frequency substantially equal to 100 MHz, thus forcing the processor 1, the processor bus 10, the RAM 3 and the memory bus 1 1 to operate at 100 MHz. Thus, if the configuration describing the unbridled mode corresponds to an operating frequency of 133 MHz for the processor bus 10, the memory bus 11, the interface component will generate a frequency signal substantially equal to 133 MHz, thus forcing the processor 1 , the processor bus 10, the RAM 3 and the memory bus 11 to operate at 133 MHz. It is of course possible to define, if the processor core can support it moreover, different bus frequencies for the same mode given according to the components, and to operate the memory bus 1 1 at a different speed of the processor bus 1.
La figure 2 illustre par un schéma un procédé de démarrage du cœur processeur dans un mode programmé selon l'invention. Les éléments identiques aux éléments déjà présentés sur les autres figures portent les mêmes références. Le procédé de démarrage selon l'invention décrit la séquence de démarrage d'un cœur processeur selon l'invention (par exemple, celui illustré à la figure 1 ) dans un mode de fonctionnement donné. Dans une étape 20, le cœur processeur est mis sous tension. Les composants du cœur processeur (comme le processeur 1 , le pont 2,...) sont maintenus dans un état inhibé (ou selon l'expression anglo-saxonne « reset »). Une étape 21 temporise jusqu'à ce que le signal d'horloge émis par l'horloge 5 répondent à certains critères définis de stabilité. Le composant d'interface 6 interdit dans une étape 22 la remise à zéro de la mémoire non volatile 4 comprenant le programme de démarrage. Puis dans une étape 23, le composant d'interface 6 accède en lecture aux informations contenues dans la mémoire non volatile 4, en particulier le mode de fonctionnement sélectionné et la configuration associée. Si la lecture par le composant d'interface 6 de l'information sur le mode choisie s'avère impossible ou erronée, le composant d'interface 6 choisit à l'étape 23 en lieu et place de l'information non accessible ou erronée un mode par défaut, correspondant par exemple à la fréquence la plus basse des différents bus et/ou composants du cœur processeur. A partir de ces informations, dans une étape 24, le composant d'interface 6 génère un ou plusieurs signaux dont la fréquence correspond à la configuration du mode sélectionné, lesdits signaux pilotant les bus et/ou les composants dudit cœur processeur. Pour cela, le composant d'interface détermine le facteur multiplicatif à appliquer à la fréquence du signal d'horloge 5 pour obtenir un signal dont la fréquence correspond à la configuration correspondant au mode sélectionné. Ainsi, ce facteur multiplicatif dépend de la configuration du mode sélectionné et est donc différent selon que le mode actif sélectionné est le mode bridé ou le mode débridé. A partir, de ce facteur multiplicatif, le composant d'interface 6 génère un signal dont la fréquence correspond à la configuration du mode sélectionné. Ce signal est ensuite utilisé par les différents bus du cœur processeur. Dans une étape 25 de temporisation, une temporisation permet d'attendre que les bus atteigne de manière stable leur fréquence cible. Puis, le composant d'interface 6 désinhibe les différents composants (processeur 1 , pont 2, ...), dans une étape 26. Le processeur 1 , le pont 2, les bus, et les autres composants peuvent alors démarrer dans une étape 27 dans le mode sélectionné, bridé ou non. Le cœur processeur est alors utilisable par le système d'exploitation dans le mode de fonctionnement choisi.FIG. 2 schematically illustrates a method for starting the processor core in a programmed mode according to the invention. Elements identical to the elements already presented in the other figures bear the same references. The starting method according to the invention describes the starting sequence of a processor core according to the invention (for example, that illustrated in FIG. 1) in a given operating mode. In a step 20, the processor core is powered on. The core processor components (such as the processor 1, the bridge 2, ...) are maintained in an inhibited state (or according to the English expression "reset"). A step 21 delays until the clock signal from clock 5 meets certain defined stability criteria. The interface component 6 prohibits in a step 22 the resetting of the nonvolatile memory 4 comprising the startup program. Then in a step 23, the interface component 6 reads the information contained in the non-volatile memory 4, in particular the selected operating mode and the associated configuration. If the reading by the interface component 6 of the information on the chosen mode proves to be impossible or erroneous, the interface component 6 chooses in step 23 instead of the inaccessible or erroneous information a default mode, corresponding for example to the lowest frequency of the various buses and / or components of the processor core. From this information, in a step 24, the interface component 6 generates one or more signals whose frequency corresponds to the configuration of the selected mode, said signals driving the buses and / or the components of said processor core. For this, the interface component determines the multiplicative factor to be applied to the frequency of the clock signal 5 to obtain a signal whose frequency corresponds to the configuration corresponding to the selected mode. Thus, this multiplicative factor depends on the configuration of the selected mode and is therefore different depending on whether the active mode selected is the bridled mode or the unbridled mode. From this multiplicative factor, the interface component 6 generates a signal whose frequency corresponds to the configuration of the selected mode. This signal is then used by the different buses of the processor core. In a delay step, a time delay makes it possible to wait for the buses to stably reach their target frequency. Then, the interface component 6 disinhibits the various components (processor 1, bridge 2, ...), in a step 26. The processor 1, the bridge 2, the buses, and the other components can then start in a step 27 in the selected mode, flanged or not. The processor core can then be used by the operating system in the selected operating mode.
Le mode de fonctionnement peut être changer vers un autre mode. Pour effectuer ce changement, il est possible par exemple de retirer la protection de la mémoire non volatile comportant le programme de démarrage en modifiant en entrée le signal de protection 7 pour permettre l'écriture. Le mode choisi peut alors être réinscrit soit par programmation (par exemple en utilisant un câble de type JTAG) soit via le processeur 1. La nouvelle configuration ne sera prise en compte qu'après une coupure/mise sous tension. The operating mode can be changed to another mode. To make this change, it is possible for example to remove the protection of the non-volatile memory containing the startup program by modifying the input protection signal 7 to allow writing. The chosen mode can then be re-registered either by programming (for example by using a JTAG type cable) or by the processor 1. The new configuration will only be taken into account after a power failure.

Claims

REVENDICATIONS
1. Cœur processeur comportant au moins un processeur (1 ), une mémoire non volatile (4) comprenant un programme de démarrage, un pont (2) interconnectant des bus (10, 1 1 , 12, 13) reliant les différents composants (1 , 3, 4, 6) dudit cœur processeur, caractérisé en ce qu'il comporte un composant d'interface (6), une mémoire non volatile (4) comportant au moins deux configurations en fréquence correspondant chacune à un mode de fonctionnement des bus (10, 1 1 , 12, 13) et/ou des composants (1 , 3, 4, 6) dudit cœur processeur, la mémoire non volatile (4) comportant une information permettant de déterminer quel mode de fonctionnement doit être utilisé, ladite information étant lue par le composant d'interface (6) pour déterminer le mode choisi, le composant d'interface (6) générant un ou plusieurs signaux d'horloge, la fréquence desdits signaux d'horloge générés correspondant sensiblement à celle décrite par la configuration du mode choisi, lesdits signaux d'horloge pilotant les bus (10, 11 , 12, 13) et/ou les composants (1 , 3, 4, 6) dudit cœur processeur.A processor core comprising at least one processor (1), a non-volatile memory (4) comprising a startup program, a bridge (2) interconnecting buses (10, 1 1, 12, 13) connecting the different components (1). , 3, 4, 6) of said processor core, characterized in that it comprises an interface component (6), a non-volatile memory (4) comprising at least two frequency configurations each corresponding to a mode of operation of the buses (10, 11, 12, 13) and / or components (1, 3, 4, 6) of said processor core, the nonvolatile memory (4) having information to determine which mode of operation is to be used, said information being read by the interface component (6) to determine the selected mode, the interface component (6) generating one or more clock signals, the frequency of said generated clock signals substantially corresponding to that described by the configuration of the selected mode, said clock signals oge driving the buses (10, 11, 12, 13) and / or the components (1, 3, 4, 6) of said processor core.
2. Cœur processeur selon la revendication 1 caractérisé en ce que, lorsque la lecture par le composant d'interface (6) de l'information sur le mode choisie s'avère impossible ou erronée, le composant d'interface (6) est adapté à choisir un mode par défaut.2. Heart processor according to claim 1 characterized in that, when the reading by the interface component (6) of the information on the selected mode is impossible or erroneous, the interface component (6) is adapted to choose a default mode.
3. Cœur processeur selon l'une des quelconques revendications 1 à 2 caractérisé en ce qu'il comporte une horloge délivrant un signal d'horloge de référence (5), la fréquence dudit signal d'horloge de référence (5) étant multipliée par le composant d'interface (6) pour générer les signaux dont la fréquence correspond sensiblement à celle décrite par la configuration du mode choisi.3. Heart processor according to any one of claims 1 to 2 characterized in that it comprises a clock delivering a reference clock signal (5), the frequency of said reference clock signal (5) being multiplied by the interface component (6) for generating the signals whose frequency corresponds substantially to that described by the configuration of the chosen mode.
4. Cœur processeur selon l'une des quelconques revendications 1 à 3, caractérisé en ce qu'il reçoit un signal de protection (7), ledit signal autorisant ou non en fonction de sa valeur l'écriture de l'information permettant de déterminer quel mode de fonctionnement doit être utilisé 4. Heart processor according to any one of claims 1 to 3, characterized in that it receives a protection signal (7), said signal allowing or not depending on its value the writing of the information to determine which mode of operation should be used
5. Cœur processeur selon la revendication 4 caractérisé en ce que l'information permettant de déterminer quel mode de fonctionnement doit être utilisé est modifiable par programmation de la mémoire non volatile (4) et/ou par le processeur (1 ).5. Heart processor according to claim 4 characterized in that the information for determining which operating mode is to be used is modifiable by programming the nonvolatile memory (4) and / or by the processor (1).
6. Procédé de démarrage d'un cœur processeur comportant au moins une mémoire non volatile (4) comprenant un programme de démarrage, un pont (2) interconnectant des bus (10, 1 1 , 12, 13) reliant les différents composants (1 , 3, 4, 6) dudit cœur processeur, caractérisé en ce que, le cœur processeur comportant aussi un composant d'interface (6), la mémoire non volatile (4) comportant au moins deux configurations en fréquence correspondant chacune à un mode de fonctionnement des bus (10, 1 1 , 12, 13) et/ou des composants (1 , 3, 4, 6) dudit cœur processeur, la mémoire non volatile (4) comportant une information permettant de déterminer quel mode de fonctionnement doit être utilisé, ladite information étant lue par le composant d'interface (6) pour déterminer le mode choisi, il comporte les étapes suivantes : o une étape (20) de mise sous tension du cœur processeur, les composants du cœur processeur (1 , 3) étant maintenus par le composant d'interface dans un état inhibé ; o une étape (22) où le composant d'interface (6) interdit la remise à zéro de la mémoire non volatile (4) ; o une étape (23) d'accès en lecture par le composant d'interface (6) aux informations relatives au mode de fonctionnement sélectionné et la configuration associée contenus dans la mémoire non volatileProcess for starting a processor core comprising at least one non-volatile memory (4) comprising a startup program, a bridge (2) interconnecting buses (10, 1 1, 12, 13) connecting the different components (1) , 3, 4, 6) of said processor core, characterized in that, the processor core also having an interface component (6), the non-volatile memory (4) having at least two frequency configurations each corresponding to a mode of operation of buses (10, 1 1, 12, 13) and / or components (1, 3, 4, 6) of said processor core, the nonvolatile memory (4) having information to determine which mode of operation is to be used, said information being read by the interface component (6) to determine the chosen mode, it comprises the following steps: a step (20) of powering the processor core, the components of the processor core (1, 3 ) being maintained by the interface component in a inhibited state; a step (22) where the interface component (6) prohibits the resetting of the non-volatile memory (4); a step (23) of read access by the interface component (6) to the information relating to the selected operating mode and the associated configuration contained in the non-volatile memory
(4) ; o une étape (24) de génération par le composant d'interface (6) d'un ou plusieurs signaux dont la fréquence correspond à la configuration du mode sélectionné, lesdits signaux pilotant les bus (10, 1 1 , 12, 13) et/ou les composants (1 , 3, 4, 6) dudit cœur processeur ; o une étape (26) de désinhibition par le composant d'interface (6) des différents composants (1 , 2). (4); a step (24) of generation by the interface component (6) of one or more signals whose frequency corresponds to the configuration of the selected mode, said signals driving the buses (10, 1 1, 12, 13) and / or the components (1, 3, 4, 6) of said processor core; a step (26) of disinhibition by the interface component (6) of the various components (1, 2).
7. Procédé selon la revendication 6 caractérisé en ce qu'après l'étape (20) de mise sous tension du cœur processeur, le procédé comporte une étape (21 ) de temporisation jusqu'à ce que le signal d'horloge de référence (5) répondent à certains critères définis de stabilité.7. Method according to claim 6, characterized in that after step (20) of powering the processor core, the method comprises a step (21) of delay until the reference clock signal ( 5) meet certain defined criteria of stability.
8. Procédé selon l'une des quelconques revendications 6 à 7 caractérisé en ce que si la lecture par le composant d'interface (6) de l'information sur le mode choisie à l'étape (23) d'accès en lecture s'avère impossible ou erronée, le composant d'interface (6) choisit à l'étape (23) en lieu et place de l'information non accessible ou erronée un mode par défaut.8. Method according to any one of claims 6 to 7 characterized in that if the reading by the interface component (6) of the information on the mode chosen in step (23) read access s is impossible or erroneous, the interface component (6) chooses in step (23) instead of the inaccessible or erroneous information a default mode.
9. Procédé selon l'une des quelconques revendications 6 à 8 caractérisé en ce qu'après l'étape (24) de génération par le composant d'interface (6) d'un ou plusieurs signaux dont la fréquence correspond à la configuration du mode sélectionné, le procédé comporte une étape (25) de temporisation jusqu'à ce que les bus atteignent de manière stable leur fréquence cible.9. Method according to any one of claims 6 to 8 characterized in that after the step (24) of generating by the interface component (6) of one or more signals whose frequency corresponds to the configuration of the In the selected mode, the method includes a delay step (25) until the buses stably reach their target frequency.
10. Procédé selon l'une des quelconques revendications 6 à 10 caractérisé en ce qu'à l'étape (24) de génération de signaux par le composant d'interface (6), celui-ci (6) détermine des facteurs multiplicatifs à appliquer à la fréquence d'un signal d'horloge de référence (5) pour obtenir un ou plusieurs signaux dont la fréquence correspond celle décrite dans la configuration correspondant au mode sélectionné. 10. Method according to any one of claims 6 to 10 characterized in that in step (24) of generating signals by the interface component (6), the latter (6) determines multiplicative factors to applying at the frequency of a reference clock signal (5) to obtain one or more signals whose frequency corresponds to that described in the configuration corresponding to the selected mode.
EP07787400A 2006-07-21 2007-07-11 Controlled frequency core processor and method for starting-up said core processor in a programmed manner Withdrawn EP2049967A2 (en)

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