EP2017879A2 - Method of treating wall portions of an opening made in a silicon substrate - Google Patents

Method of treating wall portions of an opening made in a silicon substrate Download PDF

Info

Publication number
EP2017879A2
EP2017879A2 EP08160591A EP08160591A EP2017879A2 EP 2017879 A2 EP2017879 A2 EP 2017879A2 EP 08160591 A EP08160591 A EP 08160591A EP 08160591 A EP08160591 A EP 08160591A EP 2017879 A2 EP2017879 A2 EP 2017879A2
Authority
EP
European Patent Office
Prior art keywords
opening
wall
dopants
substrate
openings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP08160591A
Other languages
German (de)
French (fr)
Inventor
Edgard Jeanne
Sylvain Nizou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Publication of EP2017879A2 publication Critical patent/EP2017879A2/en
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H01L29/8083—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M8/00—Fuel cells; Manufacture thereof
    • H01M8/10—Fuel cells with solid electrolytes
    • H01M8/12—Fuel cells with solid electrolytes operating at high temperature, e.g. with stabilised ZrO2 electrolyte
    • H01M8/1213—Fuel cells with solid electrolytes operating at high temperature, e.g. with stabilised ZrO2 electrolyte characterised by the electrode/electrolyte combination or the supporting material
    • H01M8/1226—Fuel cells with solid electrolytes operating at high temperature, e.g. with stabilised ZrO2 electrolyte characterised by the electrode/electrolyte combination or the supporting material characterised by the supporting layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M8/00—Fuel cells; Manufacture thereof
    • H01M8/10—Fuel cells with solid electrolytes
    • H01M8/12—Fuel cells with solid electrolytes operating at high temperature, e.g. with stabilised ZrO2 electrolyte
    • H01M8/1286—Fuel cells applied on a support, e.g. miniature fuel cells deposited on silica supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H01L21/31155—Doping the insulating layers by ion implantation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/30—Hydrogen technology
    • Y02E60/50—Fuel cells

Definitions

  • the present invention relates to semiconductor structures and, more particularly, to the treatment of localized areas of one or more walls of an opening or trench formed in a semiconductor substrate.
  • openings can then be treated in various ways.
  • the walls of the openings can be heavily doped.
  • the openings may also be filled with insulating or conductive materials, or alternating insulating and conductive layers.
  • step (c) consists of implantation of dopants in the upper part of the wall and in an intermediate part of the wall located under the upper part of the wall, the dopants being chosen in the group comprising boron, phosphorus and arsenic.
  • step (c) consists in deoxidizing at least one intermediate portion of the wall located under the upper part of the wall and then implanting dopants in the intermediate portion of the wall, the dopants being chosen from the group comprising boron, phosphorus and arsenic.
  • step (c) consists of deoxidizing at least an intermediate portion of the wall located under the upper part of the wall and then etching, in the opening, the unprotected silicon substrate by oxide.
  • step (c) is followed by a step of total deoxidation of the opening.
  • implantations of dopants and fluorine atoms are oblique implantations with respect to the direction of the opening.
  • the opening does not pass through the substrate.
  • An embodiment of the present invention provides a junction vertical field effect transistor formed in a lightly doped N-type silicon substrate comprising, in the upper portion of the substrate, a source electrode in contact with the substrate by the intermediate of a heavily doped N-type region, and, in the lower portion of the substrate, a drain region in contact with the substrate via a heavily doped N-type region, the source region being flanked by apertures filled with a conductor connected to the gate of the transistor, the walls of these openings being coated with oxide, with the exception of deep zones from which P-type doped areas extend.
  • One embodiment of the present invention provides a silicon fuel cell cell holder having non-through vertical openings and through-going vertical openings, the upper ends of the non-through openings opening into portions. active fuel cell and the upper ends of the through openings opening on non-active parts of the fuel cell, horizontal openings being formed in depth on the walls of the vertical openings, these horizontal openings to form passages between the vertical openings.
  • FIGS. 1A to 1D are sectional views illustrating successive steps of a method of forming a heavily doped buried well extending from the walls of an opening formed in a silicon substrate.
  • the Figure 1A represents the upper part of a silicon substrate 1.
  • an opening 3 This opening extends either over the entire thickness of the substrate or only to a limited depth thereof.
  • the opening has the shape of a straight trench but it can of course have any desired shape. It may for example have a circular section and / or consist of portions of trenches joining at different angles.
  • fluorine atoms 5 On the upper part of two opposite faces 4 of the opening 3, fluorine atoms 5 have been implanted.
  • the implanted zones 5 may result from two oblique implantations which are symmetrical with respect to the vertical. If it is desired to implant the entire periphery of the upper region of the opening 3, an oblique implantation can be maintained while the substrate is rotated on a support.
  • the Figure 1B represents the structure obtained after carrying out a thermal oxidation step.
  • This thermal oxidation causes the flanks of the opening to be oxidized on a first thickness, at locations 7 where the opening has not received implantation of fluorine atoms, and on a second thickness, at locations 9 where the The opening has been implanted with fluorine atoms.
  • the second thickness, in the implanted regions of fluorine atoms is greater than the first thickness.
  • oxidation of the upper surface of the substrate 1 was not represented. that the thermal oxidation was carried out while this surface was protected, for example by a layer of silicon nitride. This protection may also have been used to avoid the implantation of fluorine atoms in the upper surface of the substrate. Nevertheless, this is only a variant of the invention and it can be provided that the upper surface of the substrate has also been implanted fluorine atoms and is also oxidized to a depth substantially equal to that of the regions 9.
  • a new oblique implantation was made, but this time of atoms of a dopant.
  • the implantation energy is chosen so that the implanted dopants do not pass through the thick silicon oxide regions 9.
  • the angle and the implantation energy are chosen to implant a region 13 through the thinner oxide layer 7 to a limited depth.
  • the implanted zone 13 extends over a depth between the depth h1 of the region having undergone implantation of fluorine atoms and the depth h2 resulting from the implantation angle chosen for implantation.
  • the doping atoms may be P-type dopants such as boron or N-type dopants such as phosphorus or arsenic.
  • a partial deoxidation step of the structure may then be provided, for example, to completely eliminate the oxide layer 7 leaving in place a portion of the thickness of the oxide layer 9. It will be understood that this step is optional and depends on the use that we want to make the device. Alternatively, the duration of the deoxidation step can be calculated such that a silicon oxide region 10 remains in place in aperture 3 below implanted regions 13. In fact, commonly an undoped oxide is slower than a doped oxide.
  • FIGS 2C and 2D illustrate an alternative embodiment of the method described above.
  • partial deoxidation is first carried out to leave in place only the thinned upper oxide regions 9 and to eliminate completely, or almost completely, the deeper oxide parts and more 7. This may facilitate implantation of doping atoms in regions 13.
  • FIGS 3A and 3B are two sectional views illustrating another variant of a method according to an embodiment of the present invention.
  • an etching step is performed, for example an isotropic etching. This etching can be plasma etching or wet etching.
  • the walls of the opening 3 are thus hollowed out below the region protected by oxide 9.
  • figure 3B represents an optional step that can follow the step of the figure 3A .
  • the structure is shown after removal of the oxide regions 9.
  • FIGS. 4 to 6 illustrate various variants of another embodiment of the method described herein, in which it is desired to perform a treatment on a well-defined depth of an opening, at a certain depth with respect to the upper surface of the substrate in which is formed the 'opening.
  • the Figure 4A is again a sectional view of the upper part of a silicon substrate 1 in which has been formed an opening or trench 3.
  • thermal oxidation was carried out. This thermal oxidation causes the formation of a silicon oxide layer 21 on the walls of the opening 3, and possibly, if it is not protected, an oxidation (not shown) of the upper face of the substrate of silicon 1.
  • oblique implantation of the upper part 23 of the oxide layer 21 by doping atoms such as boron, phosphorus or arsenic atoms has been carried out.
  • This implantation is performed in the upper part of the oxide layer, to a depth h3.
  • the implantation energy is chosen so that the doping atoms penetrate into the oxide layer but do not pass through it.
  • Silicon oxide was etched. This etching is limited in time so as to completely etch part 23 of the oxide layer which has received doping atoms and to only partially etch part 21 of the oxide layer which has not been implanted. .
  • an opening is obtained in which the entire lower part is coated with an oxide layer 21 and at least one wall of the upper part of which has been stripped so that the silicon of the substrate 1 is apparent.
  • FIG 4C it has been shown that the two opposite faces of the opening are stripped. The entire contour of the upper part of the opening could of course also be stripped, or on the contrary a single wall of this opening could be stripped.
  • partial deoxidation of the structure is carried out so that the thinnest oxide layer 27 is removed in the region designated by reference 32 while at least a portion of the thicker oxide layers 29 and 31 stays in place.
  • a doped region 33 was formed at zone 32 between the depths h1 and h3.
  • the doping may be carried out by any means desired in the case shown where it was carried out prior to a complete deoxidation of the relevant region located between the depths h1 and h3.
  • This doping may, for example, result from diffusion from doped polycrystalline silicon formed in the opening or from diffusion carried out from a gaseous predeposit.
  • This doping may also be performed by oblique implantation, but then the angle of implantation need not be carefully chosen since the area to be doped, 32, has been delimited by the oxide regions 29 and 31. It will be noted that, in the case of oblique implantation, the implantation could be carried out through a thin layer of oxide remaining in place in zone 32.
  • the opening or trench 3 can extend over a great depth from the upper surface of the substrate, and possibly on the whole thickness of this substrate.
  • the opening or trench 3 may also have a limited depth, and this applies to all variants of the method described above.
  • the figure 6 represents the case of an opening of limited depth in correspondence with the structure illustrated in figure 5 .
  • oxide 31 lines the walls of the opening under the depth h3, as in figure 5 but the bottom of the opening is also oxidized.
  • FIGS. 7A and 7B represent an example of application of the method described above in which portions of buried doped layers are produced from at least one wall of an opening.
  • the Figure 7A is a side view in section and the Figure 7B is a sectional top view of cells of a vertical junction field effect transistor (JFET).
  • JFET vertical junction field effect transistor
  • Multiple cells are formed in an N-type silicon 100 substrate.
  • Each cell comprises, on its upper surface side, a source electrode 102 in contact through a more heavily doped N-type region 104. with the substrate 100.
  • On the side of the underside of the substrate 100 extends a strongly doped region of N (N + ) type 106 having, possibly, as shown, a relatively large thickness, in which case the substrate 100 is in fact an epitaxial layer formed on this region N + 106.
  • the region 106 is covered with a drain metallization 108.
  • the source region is surrounded by openings 110 filled with a conductor, for example doped polycrystalline silicon.
  • a conductor for example doped polycrystalline silicon.
  • the upper part of the opening, to a depth h1 is coated with oxide, and the lower part of this opening, beyond a depth h3, is coated with oxide 112.
  • doped areas 113 are formed. These doped zones result for example from a diffusion of doping atoms from the highly doped polycrystalline silicon filling the openings 110.
  • Grid metallizations 114 are in contact with the conductor filling the openings 110. In a first state, where the gate is not polarized, there is no conduction through the region N 100 between the source regions. 104 and drain 106.
  • the Figure 7B is a top view in section along the sectional plane BB of the Figure 7A . We see a set of cells identical to that of the Figure 7A .
  • the figure 8 illustrates an integrated fuel cell.
  • a silicon support 200 is formed an insulating layer 202 surmounted by a conductive layer 204 forming the anode collector of the fuel cell.
  • Through-openings 206 are formed in the silicon holder 200, the insulating layer 202 and the anode collector conductive layer 204.
  • a thick insulating layer 208 is formed on the conductive layer 204 in each of several openings formed in the layer 208.
  • the insulating layer 208 Above the second catalyst layer 216 is formed a conductive cathode collector layer 218 which has through apertures over its entire surface.
  • an opening 220 allowing contact with the anode collector conductive layer 204.
  • H + protons which are directed towards the electrolyte layer 214 and, on the other hand, electrons which are directed towards the anode collector 204.
  • the H + protons pass through the electrolyte layer 214 to join the catalyst layer 216.
  • the layer 216 is in contact with oxygen, for example ambient air, and H + protons recombine with oxygen. This results in the appearance of a potential difference between anode and cathode.
  • FIGS. 9A and 9B illustrate steps of forming a fuel cell cell support 200 according to an embodiment of the present invention.
  • Dashed lines 208 indicate the limits of the stack of the catalyst support 210, the first catalyst layer 212, the electrolyte layer 214 and the second catalyst layer 216.
  • non-through apertures 222 are formed in the support 200.
  • Through-openings 224 are formed on either side of the non-through apertures 222 in the support 200 to allow the supply of hydrogen to the fuel cell.
  • the dotted lines 208 illustrate that the active stack of the stack is formed at the non-through apertures 222 but does not extend at the through apertures 224. In other words, the through apertures 224 open at the aperture 224. look at the thick insulating layer 208 of the figure 8 .
  • the structure of the Figure 9B has the advantage of avoiding that the hydrogen is directly sent on the catalyst layer 212. Indeed, as shown by arrows in Figure 9B , the hydrogen arriving in the openings 224 passes through the horizontal openings 226 then into the vertical openings 222 to reach the catalyst layer 212. This makes it possible to regulate the pressure peaks of the hydrogen arriving on the catalyst layer 212, by example when you open a bottle of hydrogen. This eliminates a risk of separation of the active stack of the fuel cell.

Abstract

The method involves implanting fluorine atoms in an upper part of a wall of an opening (3) formed on a silicon substrate (1), where the opening is in the form of a rectilinear trench. The upper part of the wall is oxidized. A portion of a non implanted part of the opening is etched or dopants are implanted in an oxide layer formed on the upper part of the wall, where the dopants are chosen from boron, phosphorous and arsenic. Independent claims are also included for the following: (1) a vertical junction FET formed in a lightly doped N-type silicon substrate (2) a silicon fuel cell support comprising vertical traversing openings.

Description

Domaine de l'inventionField of the invention

La présente invention concerne des structures semiconductrices et, plus particuliÚrement, le traitement de zones localisées d'une ou plusieurs parois d'une ouverture ou tranchée formée dans un substrat semiconducteur.The present invention relates to semiconductor structures and, more particularly, to the treatment of localized areas of one or more walls of an opening or trench formed in a semiconductor substrate.

Exposé de l'art antérieurPresentation of the prior art

Pour former des composants Ă©lectroniques sur un substrat semiconducteur, il peut ĂȘtre nĂ©cessaire de crĂ©er, dans le substrat, une ou plusieurs ouvertures ou tranchĂ©es verticales qui peuvent ĂȘtre traversantes ou non traversantes. Ces ouvertures peuvent ĂȘtre ensuite traitĂ©es de diverses maniĂšres. Par exemple, les parois des ouvertures peuvent ĂȘtre fortement dopĂ©es. Les ouvertures peuvent Ă©galement ĂȘtre remplies de matĂ©riaux isolants ou conducteurs, ou d'une alternance de couches isolantes et conductrices.To form electronic components on a semiconductor substrate, it may be necessary to create, in the substrate, one or more vertical openings or trenches that may be through or not through. These openings can then be treated in various ways. For example, the walls of the openings can be heavily doped. The openings may also be filled with insulating or conductive materials, or alternating insulating and conductive layers.

Résumé de l'inventionSummary of the invention

On peut également souhaiter traiter, uniquement sur une certaine profondeur, une ou plusieurs parois d'une ouverture ou tranchée verticale, par exemple pour former des caissons enterrés fortement dopés ou pour réaliser une gravure à partir d'une partie d'une ou de plusieurs parois de l'ouverture.It may also be desired to treat, only at a certain depth, one or more walls of a vertical opening or trench, for example to form caissons buried heavily doped or to perform an etching from a portion of one or more walls of the opening.

On propose ici divers procédés permettant de réaliser un masque sur une ou plusieurs parois d'une ouverture formée dans un substrat semiconducteur, ce masque permettant de réaliser des implantations de dopants ou des gravures à une certaine profondeur sur la ou les parois de l'ouverture.Various methods for producing a mask on one or more walls of an opening formed in a semiconductor substrate are proposed here, this mask making it possible to implement dopant implantations or etchings at a certain depth on the wall or walls of the opening. .

Ainsi, un mode de réalisation de la présente invention prévoit un procédé de traitement d'au moins une paroi d'une ouverture formée dans un substrat de silicium, comprenant successivement les étapes suivantes :

  1. (a) réaliser une implantation d'atomes de fluor dans une partie supérieure de la paroi de l'ouverture ;
  2. (b) procéder à une étape d'oxydation ; et
  3. (c) appliquer un traitement spécifique sur au moins une portion de la partie non implantée de l'ouverture.
Thus, an embodiment of the present invention provides a method of treating at least one wall of an opening formed in a silicon substrate, comprising successively the following steps:
  1. (a) performing implantation of fluorine atoms in an upper part of the wall of the opening;
  2. (b) performing an oxidation step; and
  3. (c) applying a specific treatment to at least a portion of the non-implanted portion of the opening.

Selon un mode de réalisation de la présente invention, l'étape (a) est précédée des étapes suivantes :

  • former une couche d'oxyde sur la paroi de l'ouverture ;
  • rĂ©aliser une implantation de dopants dans la couche d'oxyde au niveau de la partie supĂ©rieure de la paroi et au niveau d'une partie intermĂ©diaire de la paroi situĂ©e sous la partie supĂ©rieure de la paroi, les dopants Ă©tant choisis dans le groupe comprenant le bore, le phosphore et l'arsenic ; et
  • enlever l'oxyde qui a Ă©tĂ© dopĂ© au niveau des parties supĂ©rieure et intermĂ©diaire de la paroi.
According to an embodiment of the present invention, step (a) is preceded by the following steps:
  • forming an oxide layer on the wall of the opening;
  • performing implantation of dopants in the oxide layer at the upper part of the wall and at an intermediate portion of the wall located under the upper part of the wall, the dopants being chosen from the group comprising boron phosphorus and arsenic; and
  • remove the oxide that has been doped at the upper and middle parts of the wall.

Selon un mode de réalisation de la présente invention, l'étape (c) consiste en une implantation de dopants dans la partie supérieure de la paroi et dans une partie intermédiaire de la paroi située sous la partie supérieure de la paroi, les dopants étant choisis dans le groupe comprenant le bore, le phosphore et l'arsenic.According to one embodiment of the present invention, step (c) consists of implantation of dopants in the upper part of the wall and in an intermediate part of the wall located under the upper part of the wall, the dopants being chosen in the group comprising boron, phosphorus and arsenic.

Selon un mode de réalisation de la présente invention, l'étape (c) consiste à désoxyder au moins une partie intermédiaire de la paroi située sous la partie supérieure de la paroi puis à implanter des dopants dans la partie intermédiaire de la paroi, les dopants étant choisis dans le groupe comprenant le bore, le phosphore et l'arsenic.According to one embodiment of the present invention, step (c) consists in deoxidizing at least one intermediate portion of the wall located under the upper part of the wall and then implanting dopants in the intermediate portion of the wall, the dopants being chosen from the group comprising boron, phosphorus and arsenic.

Selon un mode de réalisation de la présente invention, l'étape (c) consiste à désoxyder au moins une partie intermédiaire de la paroi située sous la partie supérieure de la paroi puis à graver, dans l'ouverture, le substrat de silicium non protégé par de l'oxyde.According to one embodiment of the present invention, step (c) consists of deoxidizing at least an intermediate portion of the wall located under the upper part of the wall and then etching, in the opening, the unprotected silicon substrate by oxide.

Selon un mode de réalisation de la présente invention, l'étape (c) est suivie d'une étape de désoxydation totale de l'ouverture.According to one embodiment of the present invention, step (c) is followed by a step of total deoxidation of the opening.

Selon un mode de réalisation de la présente invention, les implantations de dopants et d'atomes de fluor sont des implantations obliques par rapport à la direction de l'ouverture.According to one embodiment of the present invention, implantations of dopants and fluorine atoms are oblique implantations with respect to the direction of the opening.

Selon un mode de réalisation de la présente invention, l'ouverture ne traverse pas le substrat.According to one embodiment of the present invention, the opening does not pass through the substrate.

Un mode de rĂ©alisation de la prĂ©sente invention prĂ©voit un transistor Ă  effet de champ vertical Ă  jonction formĂ© dans un substrat de silicium faiblement dopĂ© de type N comprenant, dans la partie supĂ©rieure du substrat, une Ă©lectrode de source en contact avec le substrat par l'intermĂ©diaire d'une rĂ©gion de type N fortement dopĂ©e, et, dans la partie infĂ©rieure du substrat, une rĂ©gion de drain en contact avec le substrat par l'intermĂ©diaire d'une rĂ©gion de type N fortement dopĂ©e, la rĂ©gion de source Ă©tant encadrĂ©e par des ouvertures remplies d'un conducteur connectĂ© Ă  la grille du transistor, les parois de ces ouvertures Ă©tant revĂȘtues d'oxyde, Ă  l'exception de zones profondes Ă  partir desquelles s'Ă©tendent des zones dopĂ©es de type P.An embodiment of the present invention provides a junction vertical field effect transistor formed in a lightly doped N-type silicon substrate comprising, in the upper portion of the substrate, a source electrode in contact with the substrate by the intermediate of a heavily doped N-type region, and, in the lower portion of the substrate, a drain region in contact with the substrate via a heavily doped N-type region, the source region being flanked by apertures filled with a conductor connected to the gate of the transistor, the walls of these openings being coated with oxide, with the exception of deep zones from which P-type doped areas extend.

Un mode de réalisation de la présente invention prévoit un support de cellule de pile à combustible en silicium comprenant des ouvertures verticales non traversantes et des ouvertures verticales traversantes, les extrémités supérieures des ouvertures non traversantes débouchant sur des parties actives de la pile à combustible et les extrémités supérieures des ouvertures traversantes débouchant sur des parties non-actives de la pile à combustible, des ouvertures horizontales étant formées en profondeur sur les parois des ouvertures verticales, ces ouvertures horizontales permettant de former des passages entre les ouvertures verticales.One embodiment of the present invention provides a silicon fuel cell cell holder having non-through vertical openings and through-going vertical openings, the upper ends of the non-through openings opening into portions. active fuel cell and the upper ends of the through openings opening on non-active parts of the fuel cell, horizontal openings being formed in depth on the walls of the vertical openings, these horizontal openings to form passages between the vertical openings.

BrĂšve description des dessinsBrief description of the drawings

Ces objets, caractéristiques et avantages, ainsi que d'autres seront exposés en détail dans la description suivante de modes de réalisation particuliers faite à titre non-limitatif en relation avec les figures jointes parmi lesquelles :

  • les figures 1A Ă  1D sont des vues en coupe illustrant des Ă©tapes successives d'un premier procĂ©dĂ© de formation d'un caisson enterrĂ© fortement dopĂ© s'Ă©tendant Ă  partir des parois d'une ouverture formĂ©e dans un substrat de silicium ;
  • les figures 2C et 2D sont des vues en coupe illustrant une variante du procĂ©dĂ© des figures 1A Ă  1D ;
  • les figures 3A et 3B sont des vues en coupe illustrant des Ă©tapes successives d'un procĂ©dĂ© de gravure d'une partie des parois d'une ouverture formĂ©e dans un substrat de silicium ;
  • les figures 4A Ă  4G sont des vues en coupe illustrant des Ă©tapes successives d'un second procĂ©dĂ© de formation d'un caisson enterrĂ© fortement dopĂ© s'Ă©tendant Ă  partir des parois d'une ouverture formĂ©e dans un substrat de silicium ;
  • les figures 5 et 6 illustrent des variantes du procĂ©dĂ© des figures 4A Ă  4G ;
  • les figures 7A et 7B reprĂ©sentent un exemple d'application d'un procĂ©dĂ© selon un mode de rĂ©alisation de la prĂ©sente invention ;
  • la figure 8 illustre une cellule de pile Ă  combustible connue ; et
  • les figures 9A et 9B reprĂ©sentent un autre exemple d'application d'un procĂ©dĂ© selon un mode de rĂ©alisation de la prĂ©sente invention.
These and other objects, features, and advantages will be set forth in detail in the following description of particular embodiments in a non-limitative manner with reference to the accompanying figures in which:
  • the Figures 1A to 1D are sectional views illustrating successive steps of a first method of forming a heavily doped buried well extending from the walls of an opening formed in a silicon substrate;
  • the Figures 2C and 2D are sectional views illustrating a variant of the method of Figures 1A to 1D ;
  • the Figures 3A and 3B are sectional views illustrating successive steps of a method of etching a portion of the walls of an opening formed in a silicon substrate;
  • the Figures 4A to 4G are sectional views illustrating successive steps of a second method of forming a heavily doped buried well extending from the walls of an opening formed in a silicon substrate;
  • the Figures 5 and 6 illustrate variants of the process of Figures 4A to 4G ;
  • the Figures 7A and 7B show an example of application of a method according to an embodiment of the present invention;
  • the figure 8 illustrates a known fuel cell cell; and
  • the Figures 9A and 9B represent another example of application of a method according to an embodiment of the present invention.

Par souci de clartĂ©, de mĂȘmes Ă©lĂ©ments ont Ă©tĂ© dĂ©signĂ©s par de mĂȘmes rĂ©fĂ©rences aux diffĂ©rentes figures et, de plus, comme cela est habituel dans la reprĂ©sentation des structures semiconductrices, les diverses figures ne sont pas tracĂ©es Ă  l'Ă©chelle.For the sake of clarity, the same elements have been designated with the same references in the various figures and, moreover, as is customary in the representation of the semiconductor structures, the various figures are not drawn to scale.

Description détailléedetailed description

Les figures 1A à 1D sont des vues en coupe illustrant des étapes successives d'un procédé de formation d'un caisson enterré fortement dopé s'étendant à partir des parois d'une ouverture formée dans un substrat de silicium.The Figures 1A to 1D are sectional views illustrating successive steps of a method of forming a heavily doped buried well extending from the walls of an opening formed in a silicon substrate.

La figure 1A reprĂ©sente la partie supĂ©rieure d'un substrat de silicium 1. Dans ce substrat est formĂ©e une ouverture 3. Cette ouverture s'Ă©tend ou bien sur toute l'Ă©paisseur du substrat ou bien seulement sur une profondeur limitĂ©e de celui-ci. Dans ce qui suit, on considĂ©rera que l'ouverture a la forme d'une tranchĂ©e rectiligne mais elle pourra bien entendu avoir toute forme souhaitĂ©e. Elle pourra par exemple avoir une section circulaire et/ou ĂȘtre constituĂ©e de portions de tranchĂ©es se rejoignant Ă  des angles divers. Sur la partie supĂ©rieure de deux faces opposĂ©es 4 de l'ouverture 3, on a implantĂ© des atomes de fluor 5. Les zones implantĂ©es 5 peuvent rĂ©sulter de deux implantations obliques symĂ©triques par rapport Ă  la verticale. Si l'on souhaite implanter toute la pĂ©riphĂ©rie de la rĂ©gion supĂ©rieure de l'ouverture 3, on pourra maintenir une implantation oblique tandis que l'on fait tourner le substrat sur un support.The Figure 1A represents the upper part of a silicon substrate 1. In this substrate is formed an opening 3. This opening extends either over the entire thickness of the substrate or only to a limited depth thereof. In what follows, we will consider that the opening has the shape of a straight trench but it can of course have any desired shape. It may for example have a circular section and / or consist of portions of trenches joining at different angles. On the upper part of two opposite faces 4 of the opening 3, fluorine atoms 5 have been implanted. The implanted zones 5 may result from two oblique implantations which are symmetrical with respect to the vertical. If it is desired to implant the entire periphery of the upper region of the opening 3, an oblique implantation can be maintained while the substrate is rotated on a support.

La figure 1B reprĂ©sente la structure obtenue aprĂšs avoir procĂ©dĂ© Ă  une Ă©tape d'oxydation thermique. Cette oxydation thermique entraĂźne que les flancs de l'ouverture sont oxydĂ©s sur une premiĂšre Ă©paisseur, aux emplacements 7 oĂč l'ouverture n'a pas reçu d'implantation d'atomes de fluor, et sur une seconde Ă©paisseur, aux emplacements 9 oĂč l'ouverture a reçu une implantation d'atomes de fluor. La seconde Ă©paisseur, dans les rĂ©gions ayant reçu une implantation d'atomes de fluor, est supĂ©rieure Ă  la premiĂšre Ă©paisseur. En figure 1B, on n'a pas reprĂ©sentĂ© d'oxydation de la surface supĂ©rieure du substrat 1. Ceci suppose que l'oxydation thermique a Ă©tĂ© effectuĂ©e alors que cette surface Ă©tait protĂ©gĂ©e, par exemple par une couche de nitrure de silicium. Cette protection peut Ă©galement avoir servi Ă  Ă©viter l'implantation d'atomes de fluor dans la surface supĂ©rieure du substrat. NĂ©anmoins, ceci ne constitue qu'une variante de l'invention et on pourra prĂ©voir que la surface supĂ©rieure du substrat ait Ă©galement reçu une implantation d'atomes de fluor et soit Ă©galement oxydĂ©e sur une profondeur sensiblement Ă©gale Ă  celle des rĂ©gions 9.The Figure 1B represents the structure obtained after carrying out a thermal oxidation step. This thermal oxidation causes the flanks of the opening to be oxidized on a first thickness, at locations 7 where the opening has not received implantation of fluorine atoms, and on a second thickness, at locations 9 where the The opening has been implanted with fluorine atoms. The second thickness, in the implanted regions of fluorine atoms, is greater than the first thickness. In Figure 1B , oxidation of the upper surface of the substrate 1 was not represented. that the thermal oxidation was carried out while this surface was protected, for example by a layer of silicon nitride. This protection may also have been used to avoid the implantation of fluorine atoms in the upper surface of the substrate. Nevertheless, this is only a variant of the invention and it can be provided that the upper surface of the substrate has also been implanted fluorine atoms and is also oxidized to a depth substantially equal to that of the regions 9.

A l'Ă©tape illustrĂ©e en figure 1C, on a rĂ©alisĂ© une nouvelle implantation oblique mais cette fois-ci d'atomes d'un dopant. L'Ă©nergie d'implantation est choisie de sorte que les dopants implantĂ©s ne traversent pas les rĂ©gions 9 d'oxyde de silicium Ă©pais. L'angle et l'Ă©nergie d'implantation sont choisis pour qu'on implante une rĂ©gion 13 Ă  travers la couche d'oxyde plus mince 7 sur une profondeur limitĂ©e. Ainsi, aprĂšs recuit, la zone implantĂ©e 13 s'Ă©tend sur une profondeur comprise entre la profondeur h1 de la rĂ©gion ayant subi l'implantation d'atomes de fluor et la profondeur h2 rĂ©sultant de l'angle d'implantation choisi pour l'implantation oblique d'atomes dopants. A titre d'exemple, les atomes dopants pourront ĂȘtre des dopants de type P tels que du bore ou des dopants de type N tels que du phosphore ou de l'arsenic.At the step illustrated in figure 1C a new oblique implantation was made, but this time of atoms of a dopant. The implantation energy is chosen so that the implanted dopants do not pass through the thick silicon oxide regions 9. The angle and the implantation energy are chosen to implant a region 13 through the thinner oxide layer 7 to a limited depth. Thus, after annealing, the implanted zone 13 extends over a depth between the depth h1 of the region having undergone implantation of fluorine atoms and the depth h2 resulting from the implantation angle chosen for implantation. oblique of doping atoms. By way of example, the doping atoms may be P-type dopants such as boron or N-type dopants such as phosphorus or arsenic.

Comme l'illustre la figure 1D, on peut Ă©ventuellement prĂ©voir ensuite une Ă©tape de dĂ©soxydation partielle de la structure pour, par exemple, Ă©liminer complĂštement la couche d'oxyde 7 en laissant en place une partie de l'Ă©paisseur de la couche d'oxyde 9. On comprendra que cette Ă©tape est optionnelle et dĂ©pend de l'utilisation que l'on veut faire du dispositif. A titre de variante, la durĂ©e de l'Ă©tape de dĂ©soxydation peut ĂȘtre calculĂ©e de sorte qu'il reste en place une rĂ©gion d'oxyde de silicium 10 dans l'ouverture 3 en dessous des rĂ©gions implantĂ©es 13. En effet, de façon courante, un oxyde non dopĂ© se grave moins vite qu'un oxyde dopĂ©.As illustrated by figure 1D a partial deoxidation step of the structure may then be provided, for example, to completely eliminate the oxide layer 7 leaving in place a portion of the thickness of the oxide layer 9. It will be understood that this step is optional and depends on the use that we want to make the device. Alternatively, the duration of the deoxidation step can be calculated such that a silicon oxide region 10 remains in place in aperture 3 below implanted regions 13. In fact, commonly an undoped oxide is slower than a doped oxide.

Les figures 2C et 2D illustrent une variante de réalisation du procédé décrit ci-dessus. On part de l'état de la structure telle que représentée en figure 1B mais, comme l'illustre la figure 2C, avant de réaliser l'implantation des régions dopées 13, on commence par effectuer une désoxydation partielle pour laisser en place seulement des régions d'oxyde supérieures 9 amincies et pour éliminer complÚtement, ou presque complÚtement, les parties d'oxyde plus profondes et plus minces 7. Ceci peut faciliter l'implantation des atomes dopants dans les régions 13.The Figures 2C and 2D illustrate an alternative embodiment of the method described above. We start from the state of the structure as represented in Figure 1B but, as illustrated by Figure 2C before performing the implantation of the doped regions 13, partial deoxidation is first carried out to leave in place only the thinned upper oxide regions 9 and to eliminate completely, or almost completely, the deeper oxide parts and more 7. This may facilitate implantation of doping atoms in regions 13.

Les figures 3A et 3B sont deux vues en coupe illustrant une autre variante d'un procĂ©dĂ© selon un mode de rĂ©alisation de la prĂ©sente invention. On part par exemple de la structure illustrĂ©e en figure 2C et, au lieu de rĂ©aliser une implantation d'atomes dopants 13 sur une profondeur limitĂ©e de l'ouverture, on procĂšde Ă  une Ă©tape de gravure, par exemple une gravure isotrope. Cette gravure peut ĂȘtre une gravure plasma ou une gravure humide. On creuse ainsi, en dessous de la rĂ©gion protĂ©gĂ©e par l'oxyde 9, les parois de l'ouverture 3. La figure 3B reprĂ©sente une Ă©tape optionnelle qui peut suivre l'Ă©tape de la figure 3A. En figure 3B, on a reprĂ©sentĂ© la structure aprĂšs Ă©limination des rĂ©gions d'oxyde 9.The Figures 3A and 3B are two sectional views illustrating another variant of a method according to an embodiment of the present invention. For example from the structure illustrated in Figure 2C and, instead of performing implantation of doping atoms 13 over a limited depth of the opening, an etching step is performed, for example an isotropic etching. This etching can be plasma etching or wet etching. The walls of the opening 3 are thus hollowed out below the region protected by oxide 9. figure 3B represents an optional step that can follow the step of the figure 3A . In figure 3B the structure is shown after removal of the oxide regions 9.

On notera que l'utilisation du procédé décrit en figures 3A et 3B entraßne que l'on grave les parois de l'ouverture ou tranchée sur toute la profondeur de celle-ci à partir de la profondeur h1 correspondant au fond de la région dans laquelle on a implanté les atomes de fluor.It should be noted that the use of the method described in Figures 3A and 3B causes the walls of the opening or trench to be etched over the entire depth thereof from the depth h1 corresponding to the bottom of the region in which the fluorine atoms have been implanted.

Les figures 4 à 6 illustrent diverses variantes d'un autre mode de réalisation du procédé décrit ici, dans lequel on cherche à effectuer un traitement sur une profondeur bien délimitée d'une ouverture, à une certaine profondeur par rapport à la surface supérieure du substrat dans lequel est formée l'ouverture.The Figures 4 to 6 illustrate various variants of another embodiment of the method described herein, in which it is desired to perform a treatment on a well-defined depth of an opening, at a certain depth with respect to the upper surface of the substrate in which is formed the 'opening.

La figure 4A est à nouveau une vue en coupe de la partie supérieure d'un substrat de silicium 1 dans lequel a été formée une ouverture ou tranchée 3. A l'étape illustrée en figure 4A, on a d'abord procédé à une oxydation thermique. Cette oxydation thermique entraßne la formation d'une couche d'oxyde de silicium 21 sur les parois de l'ouverture 3, et éventuellement, si celle-ci n'est pas protégée, une oxydation (non représentée) de la face supérieure du substrat de silicium 1.The Figure 4A is again a sectional view of the upper part of a silicon substrate 1 in which has been formed an opening or trench 3. At the step illustrated in Figure 4A first, thermal oxidation was carried out. This thermal oxidation causes the formation of a silicon oxide layer 21 on the walls of the opening 3, and possibly, if it is not protected, an oxidation (not shown) of the upper face of the substrate of silicon 1.

A l'étape illustrée en figure 4B, on a procédé à une implantation oblique de la partie supérieure 23 de la couche d'oxyde 21 par des atomes dopants tels que les atomes de bore, de phosphore ou d'arsenic. Cette implantation est effectuée dans la partie supérieure de la couche d'oxyde, sur une profondeur h3. L'énergie d'implantation est choisie pour que les atomes dopants pénÚtrent dans la couche d'oxyde mais ne la traversent pas.At the step illustrated in Figure 4B oblique implantation of the upper part 23 of the oxide layer 21 by doping atoms such as boron, phosphorus or arsenic atoms has been carried out. This implantation is performed in the upper part of the oxide layer, to a depth h3. The implantation energy is chosen so that the doping atoms penetrate into the oxide layer but do not pass through it.

A l'Ă©tape illustrĂ©e en figure 4C, on a procĂ©dĂ© Ă  une gravure de l'oxyde de silicium. Cette gravure est limitĂ©e dans le temps, de façon Ă  graver complĂštement la partie 23 de la couche d'oxyde qui a reçu des atomes dopants et Ă  ne graver que partiellement la partie 21 de la couche d'oxyde qui n'a pas Ă©tĂ© implantĂ©e. Il rĂ©sulte de cette Ă©tape que l'on obtient une ouverture dont toute la partie infĂ©rieure est revĂȘtue d'une couche d'oxyde 21 et dont au moins une paroi de la partie supĂ©rieure a Ă©tĂ© dĂ©nudĂ©e de sorte que le silicium du substrat 1 est apparent. En figure 4C, on a reprĂ©sentĂ© que les deux faces opposĂ©es de l'ouverture sont dĂ©nudĂ©es. Tout le contour de la partie supĂ©rieure de l'ouverture pourrait bien entendu ĂȘtre dĂ©nudĂ© Ă©galement, ou au contraire une seule paroi de cette ouverture pourrait ĂȘtre dĂ©nudĂ©e.At the step illustrated in figure 4C Silicon oxide was etched. This etching is limited in time so as to completely etch part 23 of the oxide layer which has received doping atoms and to only partially etch part 21 of the oxide layer which has not been implanted. . As a result of this step, an opening is obtained in which the entire lower part is coated with an oxide layer 21 and at least one wall of the upper part of which has been stripped so that the silicon of the substrate 1 is apparent. . In figure 4C it has been shown that the two opposite faces of the opening are stripped. The entire contour of the upper part of the opening could of course also be stripped, or on the contrary a single wall of this opening could be stripped.

AprĂšs cela, Ă  l'Ă©tape illustrĂ©e en figure 4D, on reprend le processus dĂ©crit en relation avec la figure 1. Ainsi, en figure 4D, on peut voir que l'on a implantĂ© des atomes de fluor 5 dans la partie supĂ©rieure de l'ouverture sur une profondeur h1 infĂ©rieure Ă  la profondeur h3. Cette implantation est reprĂ©sentĂ©e comme Ă©tant effectuĂ©e sur deux faces opposĂ©es de l'ouverture. De la mĂȘme façon que cela a Ă©tĂ© dĂ©crit prĂ©cĂ©demment, elle pourra ĂȘtre rĂ©alisĂ©e sur tout le tour de l'ouverture ou sur une seule face de celle-ci.After that, at the step illustrated in figure 4D , we repeat the process described in relation to the figure 1 . So, in figure 4D it can be seen that fluorine atoms 5 have been implanted in the upper part of the opening to a depth h1 smaller than the depth h3. This implantation is represented as being performed on two opposite faces of the opening. In the same way as described above, it can be performed all round the opening or on one side of it.

En figure 4E, comme en figure 1B, on procÚde à une étape d'oxydation thermique. Il en résulte que la couche d'oxyde 21 dans la partie inférieure de l'ouverture s'épaissit pour fournir une couche d'oxyde 31, qu'une couche d'oxyde moins épaisse 27 se forme entre les profondeurs h1 et h3, et qu'une couche d'oxyde plus épaisse 29 se forme sur la profondeur h1.In figure 4E , as in Figure 1B a thermal oxidation step is carried out. As a result, the oxide layer 21 in the lower portion of the aperture thickens to provide an oxide layer 31, whereby a thinner oxide layer 27 is formed between the depths h1 and h3, and a thicker oxide layer 29 is formed on the depth h1.

A l'étape illustrée en figure 4F, on a procédé à une désoxydation partielle de la structure, de sorte que la couche d'oxyde la plus mince 27 est éliminée dans la zone désignée par la référence 32 tandis qu'une partie au moins des couches d'oxyde plus épaisses 29 et 31 reste en place.At the step illustrated in figure 4F partial deoxidation of the structure is carried out so that the thinnest oxide layer 27 is removed in the region designated by reference 32 while at least a portion of the thicker oxide layers 29 and 31 stays in place.

A l'Ă©tape illustrĂ©e en figure 4G, on a formĂ© une rĂ©gion dopĂ©e 33 au niveau de la zone 32, entre les profondeurs h1 et h3. Le dopage peut ĂȘtre effectuĂ© par tout moyen dĂ©sirĂ© dans le cas reprĂ©sentĂ© oĂč on a procĂ©dĂ© prĂ©alablement Ă  une dĂ©soxydation complĂšte de la rĂ©gion concernĂ©e situĂ©e entre les profondeurs h1 et h3. Ce dopage pourra par exemple rĂ©sulter d'une diffusion Ă  partir de silicium polycristallin dopĂ© formĂ© dans l'ouverture ou d'une diffusion rĂ©alisĂ©e Ă  partir d'un prĂ©dĂ©pĂŽt gazeux. Ce dopage pourra aussi ĂȘtre rĂ©alisĂ© par implantation oblique, mais alors l'angle d'implantation n'a pas besoin d'ĂȘtre choisi avec soin puisque la zone Ă  doper, 32, a Ă©tĂ© dĂ©limitĂ©e par les rĂ©gions d'oxyde 29 et 31. On notera que, dans le cas d'une implantation oblique, l'implantation pourrait ĂȘtre rĂ©alisĂ©e Ă  travers une mince couche d'oxyde restant en place dans la zone 32.At the step illustrated in figure 4G a doped region 33 was formed at zone 32 between the depths h1 and h3. The doping may be carried out by any means desired in the case shown where it was carried out prior to a complete deoxidation of the relevant region located between the depths h1 and h3. This doping may, for example, result from diffusion from doped polycrystalline silicon formed in the opening or from diffusion carried out from a gaseous predeposit. This doping may also be performed by oblique implantation, but then the angle of implantation need not be carefully chosen since the area to be doped, 32, has been delimited by the oxide regions 29 and 31. It will be noted that, in the case of oblique implantation, the implantation could be carried out through a thin layer of oxide remaining in place in zone 32.

En figure 5, on a représenté qu'au lieu de doper la zone 32 de l'ouverture située entre les profondeurs h1 et h3, on peut procéder à une gravure pour former des évidements 35 s'étendant à partir de la zone 32.In figure 5 it has been shown that instead of doping the area 32 of the opening between the depths h1 and h3, etching may be performed to form recesses 35 extending from the zone 32.

Dans ce qui précÚde, on a énoncé que l'ouverture ou tranchée 3 pouvait s'étendre sur une grande profondeur à partir de la surface supérieure du substrat, et éventuellement sur toute l'épaisseur de ce substrat. L'ouverture ou tranchée 3 pourra également avoir une profondeur limitée, et ceci s'applique à toutes les variantes du procédé décrit précédemment.In the foregoing, it has been stated that the opening or trench 3 can extend over a great depth from the upper surface of the substrate, and possibly on the whole thickness of this substrate. The opening or trench 3 may also have a limited depth, and this applies to all variants of the method described above.

La figure 6 représente le cas d'une ouverture de profondeur limitée en correspondance avec la structure illustrée en figure 5. Dans ce cas, de l'oxyde 31 tapisse les parois de l'ouverture sous la profondeur h3, comme en figure 5, mais le fond de l'ouverture est également oxydé.The figure 6 represents the case of an opening of limited depth in correspondence with the structure illustrated in figure 5 . In this case, oxide 31 lines the walls of the opening under the depth h3, as in figure 5 but the bottom of the opening is also oxidized.

Les figures 7A et 7B représentent un exemple d'application du procédé décrit précédemment dans lequel on réalise des portions de couches dopées enterrées à partir d'au moins une paroi d'une ouverture.The Figures 7A and 7B represent an example of application of the method described above in which portions of buried doped layers are produced from at least one wall of an opening.

Plus particuliĂšrement, la figure 7A est une vue de cĂŽtĂ© en coupe et la figure 7B est une vue de dessus en coupe de cellules d'un transistor Ă  effet de champ vertical Ă  jonction (JFET). De multiples cellules sont formĂ©es dans un substrat de silicium 100 de type N. Chaque cellule comprend, du cĂŽtĂ© de sa surface supĂ©rieure, une Ă©lectrode de source 102 en contact, par l'intermĂ©diaire d'une rĂ©gion de type N plus fortement dopĂ©e 104, avec le substrat 100. Du cĂŽtĂ© de la face infĂ©rieure du substrat 100, s'Ă©tend une rĂ©gion fortement dopĂ©e de type N (N+) 106 ayant Ă©ventuellement, contrairement Ă  ce qui est reprĂ©sentĂ©, une Ă©paisseur relativement importante, auquel cas le substrat 100 est en fait une couche Ă©pitaxiĂ©e formĂ©e sur cette rĂ©gion N+ 106. La rĂ©gion 106 est recouverte d'une mĂ©tallisation de drain 108. La rĂ©gion de source est encadrĂ©e par des ouvertures 110 remplies d'un conducteur, par exemple du silicium polycristallin dopĂ©. ConformĂ©ment au procĂ©dĂ© dĂ©crit prĂ©cĂ©demment, la partie supĂ©rieure de l'ouverture, sur une profondeur h1, est revĂȘtue d'oxyde, et la partie infĂ©rieure de cette ouverture, au-delĂ  d'une profondeur h3, est revĂȘtue d'oxyde 112. Entre les profondeurs h1 et h3, des zones dopĂ©es 113 sont formĂ©es. Ces zones dopĂ©es rĂ©sultent par exemple d'une diffusion d'atomes dopants Ă  partir du silicium polycristallin fortement dopĂ© remplissant les ouvertures 110. Des mĂ©tallisations de grille 114 sont en contact avec le conducteur remplissant les ouvertures 110. Dans un premier Ă©tat, oĂč la grille n'est pas polarisĂ©e, il n'existe pas de conduction Ă  travers la rĂ©gion N 100 entre les rĂ©gions de source 104 et de drain 106. Par contre, lorsque la grille est convenablement polarisĂ©e, l'amincissement des zones dĂ©plĂ©tĂ©es 113 autorise la circulation des charges. C'est lĂ  le fonctionnement classique d'un transistor JFET dit "Normally OFF" ou Ă  "fonctionnement normal non passant". On notera que la structure est rĂ©alisĂ©e de façon particuliĂšrement simple grĂące au procĂ©dĂ© dĂ©crit prĂ©cĂ©demment.In particular, the Figure 7A is a side view in section and the Figure 7B is a sectional top view of cells of a vertical junction field effect transistor (JFET). Multiple cells are formed in an N-type silicon 100 substrate. Each cell comprises, on its upper surface side, a source electrode 102 in contact through a more heavily doped N-type region 104. with the substrate 100. On the side of the underside of the substrate 100, extends a strongly doped region of N (N + ) type 106 having, possibly, as shown, a relatively large thickness, in which case the substrate 100 is in fact an epitaxial layer formed on this region N + 106. The region 106 is covered with a drain metallization 108. The source region is surrounded by openings 110 filled with a conductor, for example doped polycrystalline silicon. According to the method described above, the upper part of the opening, to a depth h1, is coated with oxide, and the lower part of this opening, beyond a depth h3, is coated with oxide 112. Between depths h1 and h3, doped areas 113 are formed. These doped zones result for example from a diffusion of doping atoms from the highly doped polycrystalline silicon filling the openings 110. Grid metallizations 114 are in contact with the conductor filling the openings 110. In a first state, where the gate is not polarized, there is no conduction through the region N 100 between the source regions. 104 and drain 106. On the other hand, when the grid is suitably polarized, the thinning of the depleted zones 113 allows the circulation of the charges. This is the conventional operation of a transistor JFET said "Normally OFF" or "normal operation not passing". It will be noted that the structure is produced in a particularly simple manner by means of the method described above.

La figure 7B est une vue de dessus en coupe selon le plan de coupe B-B de la figure 7A. On y voit un ensemble de cellules identiques Ă  celle de la figure 7A.The Figure 7B is a top view in section along the sectional plane BB of the Figure 7A . We see a set of cells identical to that of the Figure 7A .

La figure 8 illustre une cellule de pile à combustible intégrée. Sur un support de silicium 200 est formée une couche isolante 202 surmontée d'une couche conductrice 204 formant le collecteur d'anode de la pile à combustible. Des ouvertures traversantes 206 sont formées dans le support de silicium 200, la couche isolante 202 et la couche conductrice de collecteur d'anode 204. Sur la couche conductrice 204 est formée une couche isolante épaisse 208. Dans chacune de plusieurs ouvertures formées dans la couche 208 est formé un empilement d'un support de catalyseur 210, d'une premiÚre couche de catalyseur 212, d'une couche d'électrolyte 214 et d'une seconde couche de catalyseur 216, la couche de catalyseur 216 affleurant la face supérieure de la couche isolante 208. Au-dessus de la seconde couche de catalyseur 216 est formée une couche conductrice de collecteur de cathode 218 qui comporte des ouvertures traversantes sur toute sa surface. Dans la couche isolante 208 est formée une ouverture 220 permettant le contact avec la couche conductrice de collecteur d'anode 204.The figure 8 illustrates an integrated fuel cell. On a silicon support 200 is formed an insulating layer 202 surmounted by a conductive layer 204 forming the anode collector of the fuel cell. Through-openings 206 are formed in the silicon holder 200, the insulating layer 202 and the anode collector conductive layer 204. On the conductive layer 204 is formed a thick insulating layer 208. In each of several openings formed in the layer 208 is formed a stack of a catalyst support 210, a first catalyst layer 212, an electrolyte layer 214 and a second catalyst layer 216, the catalyst layer 216 flush with the upper face of the catalyst. the insulating layer 208. Above the second catalyst layer 216 is formed a conductive cathode collector layer 218 which has through apertures over its entire surface. In the insulating layer 208 is formed an opening 220 allowing contact with the anode collector conductive layer 204.

Pour faire fonctionner la cellule de pile à combustible, on injecte de l'hydrogÚne dans les ouvertures 206 du support 200. L'hydrogÚne est "décomposé" au niveau de la couche de catalyseur 212 pour former, d'une part, des protons H+ qui se dirigent vers la couche d'électrolyte 214 et, d'autre part, des électrons qui se dirigent vers le collecteur d'anode 204. Les protons H+ traversent la couche d'électrolyte 214 jusqu'à rejoindre la couche de catalyseur 216. La couche 216 est en contact avec de l'oxygÚne, par exemple l'air ambiant, et les protons H+ se recombinent avec l'oxygÚne. Il en résulte l'apparition d'une différence de potentiel entre anode et cathode.To operate the fuel cell cell, hydrogen is injected into the openings 206 of the support 200. The hydrogen is "decomposed" at the level of the layer catalyst 212 to form, on the one hand, protons H + which are directed towards the electrolyte layer 214 and, on the other hand, electrons which are directed towards the anode collector 204. The H + protons pass through the electrolyte layer 214 to join the catalyst layer 216. The layer 216 is in contact with oxygen, for example ambient air, and H + protons recombine with oxygen. This results in the appearance of a potential difference between anode and cathode.

Les figures 9A et 9B illustrent des étapes de formation d'un support 200 de cellule de pile à combustible selon un mode de réalisation de la présente invention. Des lignes en pointillés 208 indiquent les limites de l'empilement du support de catalyseur 210, de la premiÚre couche de catalyseur 212, de la couche d'électrolyte 214 et de la seconde couche de catalyseur 216.The Figures 9A and 9B illustrate steps of forming a fuel cell cell support 200 according to an embodiment of the present invention. Dashed lines 208 indicate the limits of the stack of the catalyst support 210, the first catalyst layer 212, the electrolyte layer 214 and the second catalyst layer 216.

A l'étape illustrée en figure 9A, des ouvertures 222 non traversantes sont formées dans le support 200. Des ouvertures traversantes 224 sont formées de part et d'autre des ouvertures non traversantes 222 dans le support 200 pour permettre l'alimentation en hydrogÚne de la cellule de pile à combustible. Les lignes en pointillés 208 illustrent le fait que l'empilement actif de la pile est formé au niveau des ouvertures non traversantes 222 mais ne s'étend pas au niveau des ouvertures traversantes 224. En d'autres termes, les ouvertures traversantes 224 débouchent en regard de la couche isolante épaisse 208 de la figure 8.At the step illustrated in Figure 9A non-through apertures 222 are formed in the support 200. Through-openings 224 are formed on either side of the non-through apertures 222 in the support 200 to allow the supply of hydrogen to the fuel cell. The dotted lines 208 illustrate that the active stack of the stack is formed at the non-through apertures 222 but does not extend at the through apertures 224. In other words, the through apertures 224 open at the aperture 224. look at the thick insulating layer 208 of the figure 8 .

A l'Ă©tape illustrĂ©e en figure 9B, on a appliquĂ© le procĂ©dĂ© dĂ©crit prĂ©cĂ©demment en relation avec les figures 4A Ă  4F et 5 aux ouvertures 222 et 224. On forme ainsi, sur une profondeur dĂ©sirĂ©e du support 200, des ouvertures horizontales 226 de chaque cĂŽtĂ© des ouvertures 222 et 224, les ouvertures horizontales 226 se rejoignant entre les ouvertures verticales 222 et 224. En figure 9B, une couche d'oxyde 228 est prĂ©sente sur les parois des ouvertures verticales 222 et 224. Cette couche 228 peut ĂȘtre enlevĂ©e, si dĂ©sirĂ©, une fois les ouvertures horizontales 226 formĂ©es.At the step illustrated in Figure 9B the method described above was applied in relation to the Figures 4A to 4F and 5 222 and 224 are thus formed. Thus, on a desired depth of the support 200, horizontal openings 226 are formed on each side of the openings 222 and 224, the horizontal openings 226 joining between the vertical openings 222 and 224. Figure 9B an oxide layer 228 is present on the walls of the vertical openings 222 and 224. This layer 228 can be removed, if desired, once the horizontal openings 226 formed.

La structure de la figure 9B a l'avantage d'Ă©viter que l'hydrogĂšne ne soit directement envoyĂ© sur la couche de catalyseur 212. En effet, comme cela est reprĂ©sentĂ© par des flĂšches en figure 9B, l'hydrogĂšne arrivant dans les ouvertures 224 passe dans les ouvertures horizontales 226 puis dans les ouvertures verticales 222 pour atteindre la couche de catalyseur 212. Ceci permet de rĂ©guler les pics de pression de l'hydrogĂšne arrivant sur la couche de catalyseur 212, par exemple aux moments oĂč on ouvre une bouteille d'hydrogĂšne. On Ă©limine ainsi un risque de dĂ©collement de l'empilement actif de la cellule de pile Ă  combustible.The structure of the Figure 9B has the advantage of avoiding that the hydrogen is directly sent on the catalyst layer 212. Indeed, as shown by arrows in Figure 9B , the hydrogen arriving in the openings 224 passes through the horizontal openings 226 then into the vertical openings 222 to reach the catalyst layer 212. This makes it possible to regulate the pressure peaks of the hydrogen arriving on the catalyst layer 212, by example when you open a bottle of hydrogen. This eliminates a risk of separation of the active stack of the fuel cell.

Des modes de rĂ©alisation particuliers de la prĂ©sente invention ont Ă©tĂ© dĂ©crits. Diverses variantes et modifications apparaĂźtront Ă  l'homme de l'art. En particulier, il est possible de former plusieurs zones spĂ©cifiques sur les parois d'ouvertures formĂ©es dans un substrat de silicium. En effet, une fois une premiĂšre zone traitĂ©e sur les parois de l'ouverture, il est possible de rĂ©pĂ©ter le procĂ©dĂ© dĂ©crit en relation avec les figures 4A Ă  4F pour obtenir un second masque permettant de traiter une autre zone des parois. A l'Ă©tape de la figure 4B, l'implantation de dopants sera rĂ©alisĂ©e sur une profondeur adaptĂ©e. De plus, il est possible de rĂ©aliser, sur une mĂȘme paroi, des traitements diffĂ©rents. Par exemple, il est possible de rĂ©aliser une gravure sur une portion de la ou des parois et de former un caisson fortement dopĂ© sur une autre portion de la ou des parois.Particular embodiments of the present invention have been described. Various variations and modifications will be apparent to those skilled in the art. In particular, it is possible to form a plurality of specific areas on the aperture walls formed in a silicon substrate. Indeed, once a first treated area on the walls of the opening, it is possible to repeat the process described in relation to the Figures 4A to 4F to obtain a second mask for treating another area of the walls. At the stage of Figure 4B the implantation of dopants will be performed on a suitable depth. In addition, it is possible to perform on the same wall, different treatments. For example, it is possible to etch a portion of the wall or walls and form a heavily doped box on another portion of the wall or walls.

Claims (10)

ProcĂ©dĂ© de traitement d'au moins une paroi d'une ouverture (3) formĂ©e dans un substrat de silicium (1), comprenant successivement les Ă©tapes suivantes : (a) rĂ©aliser une implantation d'atomes de fluor (5) dans une partie supĂ©rieure de la paroi de l'ouverture (3) ; (b) procĂ©der Ă  une Ă©tape d'oxydation ; et (c) graver au moins une portion de la partie non implantĂ©e de l'ouverture (3) ou y implanter des dopants. A method of treating at least one wall of an opening (3) formed in a silicon substrate (1), comprising successively the following steps: (a) performing implantation of fluorine atoms (5) in an upper part of the wall of the opening (3); (b) performing an oxidation step; and (c) etching at least a portion of the non-implanted portion of the opening (3) or implanting dopants therein. ProcĂ©dĂ© selon la revendication 1, dans lequel l'Ă©tape (a) est prĂ©cĂ©dĂ©e des Ă©tapes suivantes : former une couche d'oxyde (21) sur la paroi de l'ouverture (3) ; rĂ©aliser une implantation de dopants (23) dans la couche d'oxyde (21) au niveau de ladite partie supĂ©rieure de la paroi et au niveau d'une partie intermĂ©diaire de la paroi situĂ©e sous la partie supĂ©rieure de la paroi, les dopants Ă©tant choisis dans le groupe comprenant le bore, le phosphore et l'arsenic ; et enlever l'oxyde qui a Ă©tĂ© dopĂ© (23) au niveau des parties supĂ©rieure et intermĂ©diaire de la paroi. The method of claim 1 wherein step (a) is preceded by the steps of: forming an oxide layer (21) on the wall of the opening (3); performing implantation of dopants (23) in the oxide layer (21) at said upper part of the wall and at an intermediate portion of the wall located under the upper part of the wall, the dopants being chosen in the group comprising boron, phosphorus and arsenic; and remove the oxide that has been doped (23) at the upper and middle parts of the wall. ProcĂ©dĂ© selon la revendication 1 ou 2, dans lequel l'Ă©tape (c) consiste en une implantation de dopants dans ladite partie supĂ©rieure de la paroi et dans une partie intermĂ©diaire de la paroi situĂ©e sous la partie supĂ©rieure de la paroi, les dopants Ă©tant choisis dans le groupe comprenant le bore, le phosphore et l'arsenic.Method according to claim 1 or 2, wherein step (c) consists of implanting dopants in said upper part of the wall and in an intermediate part of the wall located under the upper part of the wall, the dopants being chosen in the group comprising boron, phosphorus and arsenic. ProcĂ©dĂ© selon la revendication 1 ou 2, dans lequel l'Ă©tape (c) consiste Ă  dĂ©soxyder au moins une partie intermĂ©diaire de la paroi situĂ©e sous ladite partie supĂ©rieure de la paroi puis Ă  implanter des dopants dans la partie intermĂ©diaire de la paroi, les dopants Ă©tant choisis dans le groupe comprenant le bore, le phosphore et l'arsenic.Process according to claim 1 or 2, wherein step (c) consists of deoxidizing at least one intermediate portion of the wall located under said upper part of the wall and then implanting dopants in the intermediate part of the wall, the dopants being selected from the group consisting of boron, phosphorus and arsenic. ProcĂ©dĂ© selon la revendication 1 ou 2, dans lequel l'Ă©tape (c) consiste Ă  dĂ©soxyder au moins une partie intermĂ©diaire de la paroi situĂ©e sous ladite partie supĂ©rieure de la paroi puis Ă  graver, dans l'ouverture (3), le substrat de silicium non protĂ©gĂ© par de l'oxyde.The process of claim 1 or 2, wherein step (c) comprises deoxidizing at least one intermediate portion of the wall located under said upper part of the wall and then to burn, in the opening (3), the silicon substrate not protected by oxide. ProcĂ©dĂ© selon la revendication 1, dans lequel l'Ă©tape (c) est suivie d'une Ă©tape de dĂ©soxydation totale de l'ouverture (3).The process of claim 1, wherein step (c) is followed by a step of completely deoxidizing the opening (3). ProcĂ©dĂ© selon la revendication 1, dans lequel les implantations de dopants et d'atomes de fluor sont des implantations obliques par rapport Ă  la direction de l'ouverture (3).The method of claim 1, wherein the implantations of dopants and fluorine atoms are oblique implantations with respect to the direction of the opening (3). ProcĂ©dĂ© selon la revendication 1, dans lequel l'ouverture (3) ne traverse pas le substrat (1).The method of claim 1, wherein the opening (3) does not pass through the substrate (1). Transistor Ă  effet de champ vertical Ă  jonction formĂ© dans un substrat de silicium (100) faiblement dopĂ© de type N comprenant, dans la partie supĂ©rieure du substrat, une Ă©lectrode de source (102) en contact avec le substrat par l'intermĂ©diaire d'une rĂ©gion de type N fortement dopĂ©e (104), et, dans la partie infĂ©rieure du substrat, une rĂ©gion de drain (108) en contact avec le substrat par l'intermĂ©diaire d'une rĂ©gion de type N fortement dopĂ©e (106), la rĂ©gion de source Ă©tant encadrĂ©e par des ouvertures (110) remplies d'un conducteur connectĂ© Ă  la grille du transistor, les parois de ces ouvertures Ă©tant revĂȘtues d'oxyde (111, 112), Ă  l'exception de zones profondes Ă  partir desquelles s'Ă©tendent des zones dopĂ©es de type P (113), lesdites zones dopĂ©es de type P Ă©tant formĂ©es conformĂ©ment au procĂ©dĂ© de la revendication 1.A vertical junction field effect transistor formed in a lightly doped N-type silicon substrate (100) comprising, in the upper portion of the substrate, a source electrode (102) in contact with the substrate via a strongly doped N-type region (104), and in the lower portion of the substrate, a drain region (108) in contact with the substrate via a heavily doped N-type region (106), the region source being framed by openings (110) filled with a conductor connected to the gate of the transistor, the walls of these openings being coated with oxide (111, 112), with the exception of deep zones from which extend P-type doped areas (113), said P-type doped areas being formed in accordance with the method of claim 1. Support de cellule de pile Ă  combustible (200) en silicium comprenant des ouvertures verticales non traversantes (222) et des ouvertures verticales traversantes (224), les extrĂ©mitĂ©s supĂ©rieures des ouvertures non traversantes (222) dĂ©bouchant sur des parties actives de la pile Ă  combustible et les extrĂ©mitĂ©s supĂ©rieures des ouvertures traversantes (224) dĂ©bouchant sur des parties non-actives de la pile Ă  combustible, des ouvertures horizontales (226) Ă©tant formĂ©es, conformĂ©ment au procĂ©dĂ© selon les revendications 1, 2 et 5, en profondeur sur les parois des ouvertures verticales (222, 224), ces ouvertures horizontales (226) permettant de former des passages entre les ouvertures verticales (222, 224).Silicon fuel cell cell carrier (200) having non-through vertical apertures (222) and through apertures (224), the top ends of non-through apertures (222) opening onto active portions of the fuel cell and the upper ends of the through apertures (224) opening out non-active parts of the fuel cell, horizontal apertures (226) being formed in accordance with the method of claims 1, 2 and 5, in depth on the walls of the fuel cells. vertical openings (222, 224), these openings horizontal (226) forming passages between the vertical openings (222, 224).
EP08160591A 2007-07-18 2008-07-17 Method of treating wall portions of an opening made in a silicon substrate Withdrawn EP2017879A2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0756571 2007-07-18

Publications (1)

Publication Number Publication Date
EP2017879A2 true EP2017879A2 (en) 2009-01-21

Family

ID=39113977

Family Applications (1)

Application Number Title Priority Date Filing Date
EP08160591A Withdrawn EP2017879A2 (en) 2007-07-18 2008-07-17 Method of treating wall portions of an opening made in a silicon substrate

Country Status (2)

Country Link
US (1) US8470190B2 (en)
EP (1) EP2017879A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102347363A (en) * 2010-07-21 2012-02-08 ć›œé™…ć•†äžšæœș晹慬揾 Method and structure for balancing power and performance using fluorine and nitrogen doped substrates

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8697979B1 (en) * 2009-05-15 2014-04-15 The United States Of America As Represented By The Secretary Of The Navy Solar-powered system for generation and storage of hydrogen gas in substrate microstructures
US8771153B2 (en) 2010-11-08 2014-07-08 Icon Ip, Inc. Exercise weight bar with rotating handle and cam selection device
WO2012131768A1 (en) * 2011-03-30 2012-10-04 æ ȘćŒäŒšç€Ÿæ—„ç«‹èŁœäœœæ‰€ Silicon carbide semiconductor device and method for producing same
JP2013243272A (en) * 2012-05-22 2013-12-05 Sumitomo Electric Ind Ltd Silicon carbide semiconductor device and manufacturing method of the same
EP2969058B1 (en) 2013-03-14 2020-05-13 Icon Health & Fitness, Inc. Strength training apparatus with flywheel and related methods
EP3623020A1 (en) 2013-12-26 2020-03-18 Icon Health & Fitness, Inc. Magnetic resistance mechanism in a cable machine
US10426989B2 (en) 2014-06-09 2019-10-01 Icon Health & Fitness, Inc. Cable system incorporated into a treadmill
EP3024020A1 (en) * 2014-11-19 2016-05-25 Nxp B.V. Semiconductor device and method
TWI644702B (en) 2015-08-26 2018-12-21 çŸŽć•†æ„›ćș·é‹ć‹•èˆ‡ć„ćș·ć…Źćž Strength exercise mechanisms
US10940360B2 (en) 2015-08-26 2021-03-09 Icon Health & Fitness, Inc. Strength exercise mechanisms
US10293211B2 (en) 2016-03-18 2019-05-21 Icon Health & Fitness, Inc. Coordinated weight selection
US10441840B2 (en) 2016-03-18 2019-10-15 Icon Health & Fitness, Inc. Collapsible strength exercise machine
US10252109B2 (en) 2016-05-13 2019-04-09 Icon Health & Fitness, Inc. Weight platform treadmill
US10661114B2 (en) 2016-11-01 2020-05-26 Icon Health & Fitness, Inc. Body weight lift mechanism on treadmill

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5460693A (en) 1994-05-31 1995-10-24 Texas Instruments Incorporated Dry microlithography process
DE19845003C1 (en) 1998-09-30 2000-02-10 Siemens Ag Vertical MOS transistor in semiconductor substrate
US6362040B1 (en) * 2000-02-09 2002-03-26 Infineon Technologies Ag Reduction of orientation dependent oxidation for vertical sidewalls of semiconductor substrates
TWI223408B (en) * 2003-05-09 2004-11-01 Nanya Technology Corp Trench type capacitor formation method
TW591756B (en) * 2003-06-05 2004-06-11 Nanya Technology Corp Method of fabricating a memory cell with a single sided buried strap
US6846744B1 (en) * 2003-10-17 2005-01-25 Nanya Technology Corp. Method of fabricating a bottle shaped deep trench for trench capacitor DRAM devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102347363A (en) * 2010-07-21 2012-02-08 ć›œé™…ć•†äžšæœș晹慬揾 Method and structure for balancing power and performance using fluorine and nitrogen doped substrates

Also Published As

Publication number Publication date
US8470190B2 (en) 2013-06-25
US20100003573A1 (en) 2010-01-07

Similar Documents

Publication Publication Date Title
EP2017879A2 (en) Method of treating wall portions of an opening made in a silicon substrate
EP0071494B1 (en) Method of making integrated bipolar transistors of very small dimensions
EP2009682B1 (en) FinFET field-effect transistor isolated from the substrate
EP0057126B1 (en) Process for the manufacture of a transistor
EP1406307A1 (en) Integrated circuit with a highly conductive buried layer
FR2974238A1 (en) METHOD FOR PRODUCING AN IMAGE SENSOR WITH BACKLIGHT LIGHTNESS
EP2765613A1 (en) Process for fabricating a transistor
EP1039546A1 (en) Semiconductor device with reduced leakage current and method of manufacturing it
FR2756664A1 (en) PROCESS FOR MANUFACTURING A P-CHANNEL MOS DOOR DEVICE WITH BASIC LAYOUT THROUGH THE CONTACT WINDOW, AND A DEVICE THUS MANUFACTURED
EP1507286B1 (en) Method of forming an interconnection network of an integrated circuit and methof of forming a surrounding gate transistor
FR2610141A1 (en) CMOS INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING ELECTRICAL ISOLATION AREAS IN THIS CIRCUIT
FR2850791A1 (en) Vertical unipolar component e.g. Schottky diode, has cathode with isolated trenches filled with vertical stacking from two grain conducting portions separated by insulating layer, where stacking depth is equal to cathode thickness
EP1111684A1 (en) Process for making vertical power components
EP2191531B1 (en) Cell holder for fuel cell
FR2864345A1 (en) Formation of insulated conducting trench peripheries on a semiconductor substrate for the production of a Schottky diode with MOS trenches
FR2860919A1 (en) Semiconductor on Insulator regions destined to receive components with an over thickness, notably for the fabrication of MOS transistor
EP4117045B1 (en) Method for producing a tandem photovoltaic cell
EP0038239B1 (en) Blockable diode and method of manufacturing the same
EP2328182A1 (en) Photovoltaic module comprising built-in photovoltaic cells
EP4179579A1 (en) Solar cell manufacture
EP4297548A1 (en) Method of manufacturing electronic devices
EP1494273A1 (en) Method of oxydation of silicon
FR2894075A1 (en) Integrated fuel cell support plate e.g. multilayer printed circuit board, has silicon wafer with front side carrying active fuel cell stack, and recess, formed on rear side of plate, on which channels or perforations emerge out
FR3131658A1 (en) Method of forming a cavity
EP1146554A1 (en) Method for forming buried layers

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MT NL NO PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL BA MK RS

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20130201