EP2016494A2

EP2016494A2 - Writing to and configuring flash memory

Info

Publication number: EP2016494A2
Application number: EP07756993A
Authority: EP
Inventors: Frode Milch Pedersen; Marc Laurent
Original assignee: Atmel Corp
Current assignee: Atmel Corp
Priority date: 2006-02-14
Filing date: 2007-02-14
Publication date: 2009-01-21
Also published as: WO2007095579A2; WO2007095579A3; EP2016494A4

Abstract

System for and method of writing to a flash memory (101) may include receiving two operand write commands (128) that are substantially independent of an internal architecture of the flash memory. The two operand write commands are translated into architecture-dependent flash commands (113). The Architecture-dependent flash commands are executed to fill a page buffer (110) associated with the flash memory; and subsequently contents of the page buffer are transferred to a page of flash memory. In addition, system (416) for configuring or testing a flash memory may cycle a memory array while substantially concurrently performing other functional testing using a serial interface (415).

Description

Writing to and Configuring Flash Memory

BACKGROUND

Nonvolatile memory devices generally include an array of MOS transistors, or "cells," having specialized gate structures that are designed to retain digital values, even in the absence of power to the device, by trapping or storing charge. Electronically erasable programmable read-only (EEPROM) memory devices and flash EEPROM devices ("flash") are two examples of nonvolatile memory devices. As used herein, "EEPROM" refers to devices that are generally programmable and erasable at a byte level, while "flash" refers to devices that are generally programmable and erasable in sections larger than one byte.

The memory cells in a flash device are generally arranged in blocks referred to as "pages." Each page may store many bytes of data. For example, a 256 kilobyte (K) flash device may be arranged as 1024 pages where each page stores 256 bytes of data. As another example, a 256K flash device may be arranged as 512 pages, where each page stores 512 bytes of data. Bytes within a page may be individually addressable, or they may be organized as larger words (e.g., 2-byte words, 4-byte words, etc.) The memory cells in a flash device are generally programmed or erased at the page level. That is, data in an entire page may be erased simultaneously, rather than in a byte-by-byte manner. Similarly, an entire page of flash may be programmed simultaneously through the use of a volatile page buffer.

In some conventional flash structures, the volatile page buffer generally has the same capacity as an individual page of nonvolatile flash memory. For example, a flash device that is arranged in 256-byte pages will generally have a 256-byte page buffer. To write data to a flash device, the data may be first written to the page buffer. When the page buffer is filled and a page of flash memory specified, the entire page buffer may be written to the specified page of flash memory. The page buffer may then be erased, refilled and written to another page of flash memory. Because flash memory is generally written one page at a time, data should be written in a manner that is compatible with the internal page structure (number of pages, bytes per page, and word size) of the flash memory.

Flash memory may be included in a stand-alone memory chip, or it may be embedded in a chip that provides functions beyond just storing data. For example, flash memory may be included in a microcontroller having a processing unit, registers, embedded memory, peripherals and various interface ports. Either a stand-alone flash memory chip or a device having embedded flash memory may be part of a larger circuit that includes, for example, a printed circuit board (PCB) and various other electrical components. A flash memory die may also be included in a package with other dies that make up a "system on a chip" (SOC).

During fabrication of flash memory, charge may accumulate within individual memory cells. To initially configure a flash memory device for use, the flash memory device may be subjected to a configuration process to dissipate the accumulated charge and "reset" each cell of the flash memory device to an initial, predictable state, where both '0' and '1' logic values may be written and read back with sufficient internal voltage margins between the values. One method of initially configuring a flash memory device is to alternately erase and write a pattern to each page in the flash memory device. This sequence may be repeated a number of times.

At either a PCB level or at a die level, various components, including flash memory, may be tested or configured following the fabrication process. Testing or configuring a PCB or a die may include direct electrical stimulation of various pins on a device or connections ("nets") on a die to verify connectivity or functionality. Testing or configuration of a PCB or die may also include the use of specialized circuitry. For example, components of portions of a die may be tested or configured using a boundary scan testing protocol such as a protocol developed by the Joint Test Action Group (JTAG) and described in IEEE Standards 1149.1 and 1149.1A. To facilitate boundary scan testing and configuration using boundary scan resources, portions of a die or various components on a PCB may be accessible from and serially connected to a Test Access Port (TAP), which may relay certain serial signals used by a boundary scan protocol. The signals may include for example, a clock signal, a mode signal, a serial input and a serial output (e.g., "TCLK," "TMS," "TDI" and "TDO"). By serially shifting in test command or configuration data via the mode signal, and serially shifting in test patterns or programming data via the serial input, an appropriate boundary scanning protocol may facilitate tests of connectivity between components, integrity of nets on a die, or certain functionality; or the boundary scan protocol may configure memory or some other configurable device.

SUMMARY

In some implementations, a flash memory device includes a flash controller that can facilitate efficient writing of data to the flash memory device or efficient configuration of the flash memory device (e.g., initial configuration following fabrication). For example, in some implementations, the flash controller receives write commands that are substantially independent of internal architecture of the flash memory and translates the architecture-independent commands to architecture-dependent commands. In some implementations, a flash controller can initially configure flash memory following fabrication by cycling memory arrays within the flash memory while substantially concurrently performing other functional testing.

Writing to a page of flash memory may include receiving write commands that are substantially independent of an internal architecture of the flash memory. In certain implementations, multi-operand (e.g., two-operand) flash commands are received at a flash controller from a remote controller. In various implementations, the writing process may further include translating each multi-operand write command into architecture-dependent flash commands; executing the architecture-dependent flash commands to fill a page buffer associated with the flash memory; and subsequently transferring contents of the page buffer to the page of flash memory.

In one implementation, a method of writing to a page of flash memory that is arranged to contain a first number of logical data units may include (a) receiving at a local controller from a remote controller via an interconnection means (e.g., a bus), a write command that includes one logical data unit and an address; (b) translating, by the local controller, the write command to a plurality of flash memory commands; and (c) executing the flash memory commands to transfer the logical data unit to a page buffer within the flash memory. Actions (a)-(c) may be repeated a number of times equal to the first number, in order to fill the page buffer; and the contents of the page buffer are transferred to the page of flash memory.

In some implementations, the bus is a serial bus. The serial bus may be a test interface that is compliant with IEEE (Institute of Electrical and Electronics Engineers) standard 1149.1 or 1149.1a. In some implementations, the bus is a programming interface, and the remote controller is a dedicated device programmer.

In some implementations, the flash memory and the local controller are embedded in a microcontroller device. The remote controller may be external to the microcontroller device. The logical data unit may include one byte of data or one word of data; one word of data may include a plurality of bytes of data.

Translating the write command may include generating a page buffer address that corresponds to the address of the write command. The method may further include calculating a page address corresponding to the page of flash memory. Calculating the page address may include calculating the page address based on at least one address received in action (a).

In another implementation, a method of writing to a page of embedded flash memory may include (a) receiving at an embedded flash programming unit, via a bus and from a controller remote from the embedded flash programming unit, a multi-operand (e.g., two operand) write command. The multi-operand write command may have a first operand that specifies an address and a second operand that specifies a data unit. The method may further include (b) translating the multi-operand write command into a plurality of flash commands; (c) repeating (a)-(b) for a number of multi-operand write commands corresponding to a number of data units in a page buffer; (d) executing the flash commands to fill the page buffer; and (e) upon filling the page buffer, writing contents of the page buffer to the page of embedded flash memory.

The method may further include suspending the execution of the plurality of commands to fill the page buffer while writing contents of the page buffer to the page of flash memory. Suspending the execution of the plurality of commands may include suspending the translation of the multi-operand write command into the plurality of commands. Suspending the execution of the plurality of commands may include suspending the receipt of the multi-operand write command. The method may further include generating a halt signal to prevent the controller from transmitting, via the bus, the multi-operand write command to the embedded flash programming unit.

In another implementation, a system for storing data may include a flash memory arranged in a plurality of pages and having a page buffer, each page of the plurality of pages storing a first number of logical data units, the page buffer also storing the first number of logical data units. The system may also include a flash programming unit. The flash programming unit may include an interface that connects, via a bus, to a controller remote from the flash programming unit and that receives multi-operand (e.g. two-operand) write commands from the controller. Each multi-operand write command can have a first operand specifying an address and a second operand specifying at least a portion of a logical data unit. The flash programming unit further includes a translation unit that translates each multi-operand write command to a plurality of flash commands. The plurality of flash commands may cause at least the portion to be written to the page buffer. The flash programming unit may further include a controller that causes contents of the page buffer to be written to a page of the plurality of pages when the page buffer has been written with the first number of logical data units. The system may further include a microcontroller, and the microcontroller may include the flash memory and the flash programming unit. The controller may be external to the microcontroller. The interface may suspend receipt of the multi-operand write commands while the page buffer is written to the page of the plurality of pages. A system for configuring or testing memory may cycle a memory array while substantially concurrently performing other functional testing. In particular implementations, the system may configure or cycle a flash memory using a serial interface and test other functional units using the same serial interface substantially concurrently with cycling the flash memory. In some implementations, the serial interface may be replaced with a parallel interface. In some implementations, cycling the flash memory includes erasing and writing to the flash memory in specific patterns in order to dissipate charge that may have accumulated during a fabrication process. In one implementation, a method is provided for testing an integrated circuit that has a serial interface, embedded memory, an embedded memory controller and at least one functional unit. The method includes receiving, from the serial interface, a first command to cycle the embedded memory. In response to receiving the first command, the embedded memory is cycled with the embedded memory controller. During the cycling of the embedded memory, a second command is received from the serial interface to test the at least one functional unit. The second command is executed to test the at least one functional unit substantially concurrently with the cycling of the embedded memory.

In another implementation, a method is provided for testing and configuring a device having at least a first integrated circuit and a second integrated circuit, where the first integrated circuit has embedded flash memory and an embedded flash memory controller and the first and second integrated circuits are coupled by a serial interface that connects to a device tester that is external to the device. The method includes receiving from the device tester and via the serial interface a command to configure the flash memory. The method further includes configuring the flash memory with the embedded flash memory controller; receiving test commands and test patterns from the device tester and via the serial interface; and executing the test commands and propagating the test patterns substantially concurrently with configuring the flash memory.

In some implementations, cycling or configuring the embedded memory includes executing one or more sequences of initiating erasure of the embedded memory and initiating the writing of data having a specific pattern to the embedded memory. The specific pattern may be an all Os pattern, a checkerboard pattern, or an inverse-checkerboard pattern. Executing one or more sequences may include (a) initiating erasure of the embedded memory; (b) initiating the writing of data having a first pattern to the embedded memory; (c) initiating erasure of the embedded memory; (d) initiating the writing of data having a second pattern to the embedded memory, where the first pattern and the second pattern are different; and (e) repeating (a)-(d) a variable number of times. In various implementations, a voltage level associated with initiating the writing of data may be measured. The variable number of times may be determined based on the measured voltage level. In some implementations, a determination may be made as to whether charge accumulated in the embedded memory during a fabrication process is substantially dissipated. The variable number of times may be based on the determination of whether the charge is substantially dissipated. In some implementations, the serial interface is a boundary scan interface that complies with IEEE (Institute of Electrical and Electronic Engineers) Standard 1149.1 or 1149.1a. The embedded memory may be flash memory.

Advantages of the systems and techniques described herein may include any or all of the following. A flash programming device may program flash memory with fewer commands. A flash programming device may program flash memory with simpler commands. A flash programming operation may be faster. Flash memory may be programmed by commands that are independent of an internal architecture of the flash memory. Embedded memory may be cycled concurrently with other testing, thereby reducing an overall initial test and configuration period for a device that includes the embedded memory. Cycling of the embedded memory may be initiated by a protocol that is not specific to the internal architecture of the embedded memory. Initial cycling and configuration of an embedded memory may be substantially automated.

The general and specific aspects may be implemented using a system, a method, or a computer program, or any combination of systems, methods, and computer programs. The details of one or more implementations are set forth in the accompanying drawings and the description below.

DESCRIPTION OF DRAWINGS

These and other aspects will now be described in detail with reference to the following drawings.

Fig. 1 is a block diagram of a system in which multi-operand (e.g., two- operand) write commands may be translated to flash commands.

Fig. 2 is a block diagram showing additional details of the flash memory and flash controller that are shown in Fig. 1. Fig. 3 is a flow diagram illustrating a method for translating multi- operand write commands to flash commands, and executing the flash commands to write to flash memory. Fig. 4 is a block diagram illustrating a system in which embedded memory may be cycled concurrently with testing of one or more functional units.

Fig. 5 is a block diagram of an exemplary microcontroller having embedded memory. Fig. 6 is a block diagram of an example flash controller and flash memory.

Fig. 7 is a flow diagram of a method for concurrently configuring flash memory and performing other testing.

Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION OF EXEMPLARY IMPLEMENTATIONS

In some implementations, a flash memory device includes a flash controller that can facilitate efficient writing of data to the flash memory device or efficient configuration of the flash memory device (e.g., initial configuration following fabrication). For example, in some implementations, the flash controller receives write commands that are substantially independent of internal architecture of the flash memory and translates the architecture-independent commands to architecture-dependent commands. In some implementations, a flash controller can initially configure flash memory following fabrication by cycling memory arrays within the flash memory while substantially concurrently performing other functional testing. Details are provided of example implementations in which the flash controller can facilitate efficient writing of data to the flash memory device. Additional details are provided of example implementations in which the flash controller can facilitate initial configuration of flash memory.

Efficient writing of data to a flash memory device In some implementations, efficient writing of data to a flash memory device can be facilitated (e.g., by a flash controller). Writing to a page of flash memory may include receiving, at a flash controller, from a remote controller, multi-operand (e.g., two-operand) write commands that are substantially independent of an internal architecture of the flash memory; translating each multi-operand write command into architecture-dependent flash commands; executing the architecture-dependent flash commands to fill a page buffer associated with the flash memory; and subsequently transferring contents of the page buffer to the page of flash memory. Reference will be made to a system that processes two-operand write commands, though those of ordinary skill in the art will recognize that other multi-operand configurations are possible. Fig. 1 is a block diagram illustrating a system 100 in which a page of flash memory may be written by translating a series of two-operand write commands to flash commands. The system 100 includes flash memory 101, which is arranged in a number of pages 104. Each page stores a number of bytes of data. The bytes may be individually addressable, or they may be grouped in other logical data units. For example, each page may be arranged as a number of individually addressable words, and each word 107 may include a number of bytes (e.g., 2 bytes, 4 bytes, 8 bytes, etc.). As shown, each of the pages 104 includes four words. The flash memory 101 also includes a page buffer 110, which in one implementation is the same size as one of the pages 104 of the flash memory 101; that is, the page buffer 110 stores the same number of bytes as one of the pages 104 stores.

As is described in further detail with reference to Fig. 2, writing data to a page of flash memory generally involves first writing the data to the page buffer 110. When the page buffer 110 is full, its contents may be transferred to a specific page 104a of flash memory 101. To write data to all of the pages 104 of the flash memory 101, the page buffer 110 is generally filled once for each page 104 of memory, its contents are transferred to a specific page of flash memory, the page buffer 110 is erased or cleared, the page buffer 110 is again filled, its contents are transferred to another page of flash memory in sequence, and so on.

Filling the page buffer 110, transferring its contents to a specific page 104a of flash memory 101, erasing the page buffer 110, and performing other operations in the flash memory generally require specialized flash commands 113 (hereinafter "flash commands 113"). These specialized flash commands 113 are generally based on an internal architecture of the flash memory 101. For example, in order for a device, such as a remote controller 116, to write data to the flash memory 101, the remote controller 116 may initially clear the page buffer 110 with a specialized flash command, then write data to each word in the page buffer 110 with other specialized flash commands. To properly fill the page buffer 110, the remote controller 116 may account for the size, in bytes, of the page buffer 110; and the width of a bus 119 coupling the remote controller 116 to the flash memory 101. For example, to fill a 32-byte page buffer over a 16-bit bus, the remote controller 116 may transfer 16 two-byte words to the flash memory. After the 16 two-byte words have been transferred to the 32-byte page buffer, the remote controller may cause the page buffer contents to be written to a specific page of flash memory. To properly transfer contents of the page buffer 110 to a page 104a of flash memory 101, the remote controller 116 may also account for the number of pages 104 in the flash memory 101 and the overall capacity of the flash memory 101. For example, to properly fill a number of pages 104 of flash memory 101 in sequence, the remote controller 116 may account for how the pages 104 are addressed, which may, in turn, depend on the overall capacity of the flash memory 101 and of the size of the pages 104. In some implementations, the remote controller 116 may be a dedicated flash programmer, and flash memory 101 may be a stand-alone memory device. In some implementations, the flash memory 101 may be flash memory that is embedded in another device 122, such as a microcontroller. In some implementations, the remote controller 116 may be a microprocessor or memory controller that accesses the flash memory 101. The bus 119 may be a parallel bus that can couple the flash memory 101 to the remote controller 116. For example, the bus 119 may be a parallel system bus that couples the flash memory 101 to other devices within a datapath. The bus 119 may also be a serial bus. For example, the bus 119 may be a dedicated serial communication or programming interface, such as an Inter Integrated Circuit (I²C) bus, or a

Serial Peripheral Interface (SPI) bus. As another example, the bus 119 may be part of a test interface, such as a boundary scan interface that complies with IEEE (Institute of Electrical and Electronics Engineers) Standard 1149.1 or 1149.1a (sometimes referred to as a "JTAG" interface, which was developed by the Joint Test Action Group). In some implementations, the bus 119 (e.g., a JTAG interface) may be used to program devices connected to it, such as the flash memory device 101.

As shown in Fig. 1, the system 100 also includes a flash controller 125 that is interposed between the flash memory 101 and the remote controller 116. In some implementations, the flash controller 125 may be used to translate simple, flash- architecture independent write or store commands (hereinafter "commands 128") into architecture-dependent flash commands 113. Including such a flash controller 125 in the system 100 may enable the remote controller 116 to interact with the flash memory 101 in a flash- architecture independent manner, and the commands 128 necessary to write data to the flash memory may be fewer and simpler. For example, instead of providing "Flash Command IA," "Flash Command IB," and "Flash Command 1C" to the flash memory 101 in order to write, e.g., a single word to the page buffer 110, the remote controller 116 may instead provide a single "Write Command 1." The flash controller 125 may translate the "Write Command 1" into, for example, "Flash Command IA," "Flash Command IB" and "Flash Command 1C," and provide the translated commands to the flash memory 101.

The commands 128 may be completely independent of internal architecture details of the flash memory 101. For example, the commands 128 may be a series of two-operand write commands specifying data units to be sequentially written to the flash memory 101. Each command 128 may specify data to be written and a sequential address to which the data should be written. The address may be independent of page addresses, page buffer addresses, or the page buffer 110 itself. That is, the flash controller 125 may translate, for example, an "absolute" address to an appropriate page buffer address; moreover, after an appropriate number of data units have been received by the flash controller 125 and written to the page buffer 110, the flash controller 125 may issue commands for transferring the contents of the page buffer 110 to an appropriate page 104a. Furthermore, the flash controller 125 may interject flash command(s) 113 to erase the page buffer 110 before continuing to receive additional data units from the remote controller 116 to be written to the flash memory 101.

In some implementations, the flash controller 125 may automatically prevent the remote controller 116 from sending more data units while the contents of the page buffer 110 are being transferred to a page 104a of flash memory 101. For example, the flash controller 125 may generate a busy or halt signal (not shown) that temporarily prevents the remote controller 116 from sending more data units to be written. In some implementations, the flash controller 125 may continuously receive commands from the remote controller 116, and the flash controller 125 may temporarily buffer them (buffer not shown), or temporarily hold off translating them into flash commands 113, while the contents of the page buffer 110 are being written to a page 104a in the flash memory 101. The process of translating two-operand commands 125 to flash commands 113 is now described with reference to Fig. 2.

Fig. 2 is a block diagram illustrating additional details of the flash memory 101 and the flash controller 125 that are shown in Fig. 1. As described above, flash memory 101 is generally arranged in "pages." As shown in Fig. 2, the flash memory 101 has four pages 104, and each page has four words. Fig. 2 is simplified for the purposes of illustration. An actual flash device would generally have more pages, and each page would have more words. For example, a typical flash memory may be arranged as 512 pages, where each page stores 512 bytes of data. In addition, the flash memory 101 has a page buffer 110 that is used to write data to the flash pages 104. The page buffer 110 can have the same capacity as an individual page of the flash memory 101, such that the page buffer 110 may fill one page of flash memory. Data can be first written to the page buffer, and the contents of the page buffer are then transferred to a particular page.

The page buffer 110 may be indirectly accessed through registers. For example, the flash memory 101 may include an address register 201, a data register 204 and a command register 207. Writing a word to the page buffer 110 may involve writing a value to the address register 201 that specifies the word address within the page buffer 110, writing a data value to the data register 204, and writing a command that causes a state machine (not shown) within the flash memory 101 to transfer the contents of the data register 204 to the word in the page buffer 110 corresponding to the contents of the address register 201. This process may be repeated for each word in the page buffer 110, and when the page buffer 110 is full, it may be transferred to a page of memory. To transfer the page buffer 110 to a page of memory, an address of the page may be written to the address register 201, and a command may be written to the command register 207. The command may specify that the page buffer 110 is to be transferred to a page having an address that corresponds to the contents of the address register 201.

The flash memory 101 may perform other operations in response to various other commands. For example, writing certain values to the address register 201 and command register 207 may cause the page buffer 110 to be erased. In response to other commands, individual pages may be erased, the entire device may be erased, values may be read, or other operations may be performed.

In some implementations, a word may be a single byte, and in some implementations, a word may be two or more bytes. The size of the registers 201, 204 and 207 may vary accordingly, and may further vary based on the width of a data bus 210 through which the embedded flash memory is accessed. For example, in implementations with two-byte words and a one -byte bus, the data register may each actually be two registers — a "high" register and a "low" register — and writing data to a page of memory may include additional cycles not described above.

Various features of an example flash controller 125 are now described. The flash controller 125 may be used to translate architecture-independent commands (e.g., two-operand write commands) to architecture-dependent flash commands. To translate architecture-independent commands, the flash controller may include an interface 213 that receives such commands. The interface 213 may include a register that is coupled to the bus 119. Via the bus 119, the interface 213 may receive the commands from a remote controller 116 (shown in Fig. 1), such as, for example, a dedicated flash programmer. The commands received by the interface 213 via the bus 119 (e.g., commands 216) are generally independent of internal architecture of the flash memory 101. In particular, example commands 216 do not specify addresses within the page buffer 110 or flash pages; rather, the commands 216 may specify data corresponding to an "absolute" address that is within a range of addresses mapped to the flash memory. (As used herein, "absolute" is relative to the base address of the flash memory, rather than being relative to pages in the flash memory or relative to the page buffer.)

The flash controller 125, may translate the commands 216 into architecture-dependent flash commands (e.g., the commands 219). As an example, the flash controller 125 may translate the command 216a ("write ADDRl DATAl") into appropriate flash commands for writing the value DATAl to an appropriate word in the page buffer 110. The word in the page buffer 110 may be determined by applying some function to the ADDRl value (depicted as "Fn(ADDRl)" in FIG. 2). For example, in some implementations, the lower bits of an address value may be used to identify a word within the page buffer 110, and higher bits of the address value may be discarded or subsequently used to identify a page within the flash memory. In particular, the DATAl value may be written to the data register 204; the address value — possibly modified by an appropriate function — may be stored in the address register 201; and a command may be stored in a command register 207. The command may cause the data in the data register 204 to be stored in a page buffer word that is addressed by the contents of the address register 201. Thus, in some implementations, the three register writes 222 may be architecture- dependent flash commands corresponding to architecture-independent command 216a.

The flash controller 125 may receive a sufficient number of architecture- independent commands 216 to fill the page buffer 110. For example, the flash controller may receive commands 216b, 216c and 216d and translate each of these commands into architecture-dependent flash commands in the manner described above. Once the page buffer 110 has been filled, the flash controller 125 may issue additional flash commands 225 that specify a page address and cause the contents of the page buffer 110 to be transferred to the specified page. More particularly, the flash controller may write a page address to the address register 201 and a command to the command register 207 that causes the contents of the page buffer 110 to be transferred to a page whose address is specified by the contents of the address register 201.

The process of writing the contents of the page buffer 110 to one of the pages 104 may take some amount of time, during which certain flash operations may be suspended. That is, the flash memory 101 or the flash controller 125 may enforce "wait states," as depicted by the wait command 228, through use of a buffer or a "halt," "suspend," "busy," or similar-functioning signal. In some implementations, wait states may be enforced by transmitting a suspend signal to the bus 119 to temporarily prevent the remote controller 116 from sending additional commands 216; in some implementations, the flash controller may continue to receive commands 216 via the bus 119, but the flash controller 125 may temporarily suspend translating the commands 216 to flash commands 219; in some implementations, the flash controller 125 may receive commands 216 and translate them, but the flash controller 125 may temporarily hold off issuing them to the flash memory 101 while the page buffer 110 is being transferred to one of the pages 104.

After the contents of the page buffer 110 have been transferred to one of the pages 104, the flash controller 125 may cause the page buffer 110 to be cleared, for example, by using a "ClearPageBuffer" command 231. After the page buffer 110 has been cleared, the flash controller 125 may resume translating commands 216 to flash commands 219. As shown, the commands 234 correspond to the command 216e.

To control the overall process of translating architecture-independent commands 216 to architecture-dependent flash commands 219, the flash controller 125 may employ a controller 237 and a translation unit 240. The controller 237 (e.g., a finite state machine) may control the overall operations of the flash controller. For example, the controller 237 may track the receipt of commands 216 relative to the internal architecture of the flash memory 101. More particularly, the controller 237 may manage the number of commands 216 to fill the page buffer 110 before transferring the contents of the page buffer 110 to one of the pages 104 (e.g., with the flash commands 225). The controller 237 may also track the pages 104 in order to sequentially fill the flash memory 101 with data. The flash controller 125 also includes a translation unit 240. The translation unit 240 may, under the control of the controller 237, translate the commands 216 to flash commands 219. The translation process may involve parsing the incoming commands 216 into data and address components, translating the data component into a write-to-the-data-register-204 command, and translating the address component into a write-to-the-address-register-201 command. Translating the address component may require certain processing. For example, the command 216a ("Write ADDRl DATAl") includes the address component "ADDRl," but its corresponding flash command may have a "Fn(ADDRl)" component that represents a function applied to the ADDRl value. More particularly, the function may extract a portion of the ADDRl value. As described above, lower bits of the ADDRl value may be used to index a word within the page buffer 110, while higher bits of the ADDRl value may be used to index one of the pages 104. In addition to merely mapping address and data components (or portions thereof) from commands 216 to flash commands 219, the translation unit 240 may perform additional processing. For example, in some implementations, the translation unit 240 may apply an algorithm in order to scramble or encrypt either or both of the data or address components. As a more specific example, the translation unit 240 may translate ADDRl to Fn(ADDRl), where Fn(ADDRl) represents an encrypted or scrambled address value. Such encryption or scrambling may be used, for example, to protect the data from unauthorized access or to protect a portion of the system against hacking or reverse-engineering. Similar translations may be applied data. Fig. 3 is a flow diagram that further illustrates a method 300 for translating architecture-independent commands to architecture-dependent flash commands. The method 300 is illustrated with reference to three devices that are shown in Fig. 1: the remote controller 116, the local controller 125 and the flash memory device 101. The method 300 may determine whether writes to the flash controller

(e.g., a "local controller") have been suspended (301). For example, if the page buffer 110 is currently being written to one of the pages 104 of the flash memory 101, further writes by the remote controller 116 may be temporarily suspended. In some implementations, this determination 301 is not made; rather write commands issued by the remote controller 116 may be buffered and translation of the commands may be suspended. In some implementations, commands may be translated, but the translated flash commands may be buffered and not issued to the flash memory while the contents of the page buffer 110 are being written to one of the pages 104. Absent an optional suspend signal (301), the remote controller 116 issues

(304) a write command to the flash controller. For example, the remote controller 116 may issue a two-operand command specifying only an "absolute" address and a data value to be written to the flash memory 101. The two- operand write command may be independent of internal architecture of the flash memory, and the two-operand write command may be issued to the flash controller 125 via the bus 119. The remote controller 116 may determine (305) whether another write is to be issued, and if so, the remote controller 116 may issue repeated write commands. The flash controller receives (307) a write command. As described above, the received write command may include a data value, or logical data unit. In some implementations, the logical data unit may include one byte of data. In some implementations, the logical data unit may be a word that includes more than one byte of data. The size of the logical data unit may be based on the width of the bus 119 and the format of the write command. For example, a write command that is formatted to be completely transferred in a single bus cycle over a 16-bit bus may include a 4-bit operation code (opcode), a 4-bit address value, and eight bits (one byte) of immediate data content; in this case, the logical data unit may be one byte. As another example, a write command may be formatted to be completely transferred in two bus cycles over a 16-bit bus, and the write command may include an 8-bit opcode, 8 bits of address information, and two bytes of immediate data content; in this case, the logical data unit may be two bytes. As another example, a write command may be formatted to be completely transferred in 24 bus cycles over a single -bit serial bus, and the write command may include a four-bit opcode, four bits of address information, and two bytes of immediate data content; in this case, the logical data unit may also be two bytes.

The size of the logical data unit may also be based on the format of the data itself. In some implementations, the logical data unit may include one or more units of data as well as one or more bits of control or check information. For example, a logical data unit may include 7 bits of data and one bit of parity. As another example, a logical data unit may be formatted to support error checking and correction (ECC) and may, accordingly, include, e.g., 4 bytes of data and 1 byte of ECC information to allow the integrity of the data to be verified or maintained. Some logical data units may also include data and corresponding header or wrapper information, which may be used to route the data over various buses or networks external to the flash memory 101.

The flash controller 125 translates (310) the write command into a plurality of flash commands. For example, referring to Fig. 2, the flash controller 125 may translate the command 216a ("Write ADDRl DATAl") into the flash commands 222 ("STORE ADDR_REG Fn(ADDRl)," "STORE DATA_REG DATAl" and "STORE CMND_REG Write2PageBuffer").

The flash commands may be executed (313) to transfer the logical data unit to the page buffer 110. That is, the commands 222 may be issued by the flash controller 125 to the flash device 101, via the bus 210. The commands 22 may be executed (313) such that, for example, appropriate values are written to the registers 201, 204 and 207.

Upon receipt of appropriate values in the registers 201, 204 and 207, a state machine (not shown) in the flash memory 101 may cause the logical data unit to be received in the page buffer 110. Based on the size of the data register 204, more operations may be required than are described above. For example, to receive a two-byte logical data unit over an 8-bit bus 210, two data writes may be required, and the data register 204 may actually include a "data low" register and a "data high" register. A single data register 204 is shown for purposes of illustration only, and the exact architecture of the flash memory 101 is not critical to the systems, methods and apparatus described herein.

The flash controller 125 determines (319) whether the page buffer 110 is full. For example, the controller 237 within the flash controller 125 may track a number of logical data units that have been transferred to the page buffer 110. If the page buffer 110 has not been filled, the flash controller 125 may receive (307) another write command, translate (310) the write command to a plurality of flash commands, and execute (313) the flash commands to transfer another logical data unit to the page buffer 110. If the page buffer is determined (319) to be full, the flash controller 125 may cause its contents to be transferred to one of the pages 104 of flash memory 101. For example, referring to Fig. 2, the flash controller 125 may issue flash commands 225 to specify a page address and cause the content of the page buffer 110 to be transferred to a page corresponding to the specified page address.

In response, the flash memory 101, under the control of an internal state machine (not shown), may transfer (325) the contents of the page buffer 110 to one of the pages 104 of the flash memory 101. As described above, this transfer may take some time, during which a suspend signal may be generated (328), or part of the above-described process may otherwise be temporarily halted or suspended.

Upon completion of the transfer 325, the flash controller 125 may determine (331) whether to write another page of data to the flash memory 101. If another page is to be written, the flash controller 125 may receive (307) additional write commands, translate (301) them, and execute (313) them to fill the page buffer 110 again. Between sequences of filling the page buffer 110, the flash controller 125 may clear the contents of the page buffer 110, for example, by issuing the command 231. In some instances, the remote controller 116 may only provide enough write commands to partially fill the page buffer 110. In such instances, the flash controller 125 may generate additional flash commands with "filler" logical data units, in order to transfer the actually provided logical data units to the flash memory 101. Alternatively, the flash controller 125 may simply issue a command to cause the partially filled page buffer 110 to be transferred to a page in its partially filled state, without generating and writing "filler" logical data units to the page buffer 110.

Cycling of flash memory In some implementations, cycling of flash memory is facilitated (e.g., by a flash controller). Fig. 4 is a block diagram illustrating a system 400 in which embedded memory may be cycled concurrently with testing of one or more functional units. In particular, Fig. 4 illustrates a printed circuit board (PCB) 401 that includes integrated circuit components 404, 405 and 408 (hereinafter, "components"). As shown, the integrated circuit component 404 (e.g., a microcontroller and hereinafter referred to as "microcontroller 404") includes embedded memory 409 (e.g., flash memory).

To facilitate testing, the integrated circuits 404, 405 and 408 may be coupled by a serial test interface 412, such as, for example, a boundary scan test interface that complies with IEEE (Institute of Electrical and Electronics Engineers) standard 1149.1 or 11491a — sometimes referred to as a "JTAG" interface (Joint Test Action Group interface). During testing, the serial test interface 412 may be coupled to a corresponding test interface 415 of a tester 416. Through the serial test interface 412, the tester 416 may be able to verify the integrity of the manufacturing process of the PCB 401, or of various components on the PCB 401. In particular, the tester 416 may be able to verify component connectivity and component functionality. The tester 416, through the serial test interface 412, may test various components by placing the components into a known state, supplying known input data, and capturing the response of the components or of other components in the system to the known input data. The captured response may be compared to an expected response to verify functionality or connectivity. For example, test circuitry within the various components may respond to commands and test patterns from the serial test interface 412 to place component pins into a specific logic state or to capture the logic state of a component pin.

By using the test circuitry (not shown) in the first component 405 to place a pin 419 into a particular logic state, and by using test circuitry (not shown) in a second component 404 to capture a corresponding logic state of another pin 420 that is physically connected (or that should be physically connected) to the first component pin 419, the tester 416, using the serial test interface 412, may verify connectivity. This mode of testing may be particularly advantageous, for example, for testing internal functionality of components, or for testing connectivity between components on a dense PCB, where test access points may not be otherwise accessible (e.g., under a ball-grid array (BGA) component, such as component 408).

Functional testing may also be possible. For example, the tester may set various inputs of a circuit to a known state, and the tester may capture a logic state(s) of an output of the circuit in order to verify functionality. More particularly, the tester may set inputs of a circuit within the microcontroller 404 to a certain state (e.g., inputs 420 and 423), and capture state of a corresponding output 424. As another example, the tester 416 may verify functionality of internal blocks, such as, for example, the functional unit 427. To place various components into a known state, test circuitry within a device under test (DUT) may receive a serial input stream (e.g., on the TDI line of a JTAG interface) of commands and test patterns. Test circuitry within the DUT may generate a corresponding serial output stream (e.g., on the TDO line of a JTAG interface) that may capture the state of components in response to the serial input stream. The input and output streams may be synchronized by a clock signal (e.g., the TCLK line of a JTAG interface), and the serial output stream may be compared to an expected serial output stream; if the streams match, the corresponding tests may be deemed to have been passed. Connectivity and functional testing may be performed in a production test environment where integrated circuits or systems are presented for functional testing and configuration. For example, as shown in Fig. 4, the tester 416 may execute tests on individual components (e.g., integrated circuit components 404, 405 and 408) or on whole systems (e.g., PCB 401) using the serial test interfaces 415 and 412 and a corresponding serial test protocol (e.g., a JTAG boundary scan protocol). In particular, the tester 416 may connect to the serial test interface 412 through test probes or through a test connection 430.

In some implementations, the serial test interface 412 may also be used to program memory elements, such as the embedded flash 409, or to configure other programmable or configurable devices that are connected to the serial test interface 412. Some memory elements may require initialization or configuration prior to being programmed. For example, the embedded flash memory 409, may require initial configuration or cycling to dissipate charge that may have accumulated during a fabrication process. In some implementations, the serial test interface 412 may be used to perform this initial configuration or cycling process.

Generally, configuring or programming memory, such as the flash memory 409, is time-intensive relative to other testing. As such, it may be advantageous to configure the flash memory 409 concurrently with other testing (e.g., testing of connectivity of nets on the PCB 401 and other functional testing, such as testing of the component 405 and the functional unit 427). One way to facilitate concurrent memory configuration and other testing is to provide a flash controller (shown in Fig. 5) to configure the memory. In some implementations, the flash controller frees up the serial test interface 412 for other concurrent testing. Without such a flash controller, the tester 416 may need the serial test interface 412 to directly configure the memory, which may consume more test time. In some implementations, a parallel interface may be used in place of the serial interfaces 412 and 415 that are described above. Fig. 5 is a block diagram of an exemplary microcontroller 404 that includes embedded flash memory 409, which can be configured or cycled via the serial test interface 412. The embedded flash memory 409 may be controlled by a flash controller 503, and the flash controller 503 may be connected to the serial test interface 412 by a serial interface 507 (e.g., a JTAG interface) in the microcontroller 404. The serial interface 507 may transfer data and commands to the flash controller 503, from the serial test interface 412 for configuration or cycling of the embedded flash memory 409.

The flash controller 503 generally manages reads and writes of data in the embedded flash memory 409. Reading from and writing to the flash memory may require a specific protocol, based on the internal architecture of the flash. More particularly, as is described in more detail with reference to Fig. 6, flash memory is generally arranged in pages, and flash is generally erased and written in page increments, through use of a page buffer. The flash controller 503 may track page boundaries and generally manage filling the page buffer and causing the page buffer to be written to a page of flash memory. The flash controller 503 may also be used to initially cycle or configure the embedded flash memory 409.

The embedded flash memory 409 may be programmed in a number of ways. For example, during operation of the microcontroller 404, program code that is executed by the microcontroller 404 may cause data to be stored in or retrieved from the embedded flash memory 409, through the flash controller 503. As another example, initial data may be received from the serial test interface 412 and stored in the embedded flash memory 409, through the flash controller 503. Before data can be initially stored in the embedded flash memory 409, the embedded flash memory 409 may require initial cycling or configuration. This is because charge may accumulate in the embedded flash during the manufacturing process, and for the embedded flash memory 409 to function properly, the accumulated charge may need to be dissipated. Dissipating accumulated charge may require sequentially erasing and writing various data patterns to the embedded flash memory 409.

Certain data patterns may be particularly effective in dissipating accumulated charge. For example, one method of configuring embedded flash memory 409 may include erasing each page, writing a first pattern to each page (e.g., a "checkerboard pattern of alternating bits, such as 101010 ..."), again erasing each page, writing a second pattern to each page (e.g., an "inverse checkerboard pattern" of alternating bits arranged as the inverse of the first pattern, such as "010101 ..."), again erasing each page, writing a third pattern to each page (e.g., a pattern of all Os), and again erasing each page in the embedded flash memory 409. Other patterns or combinations of patterns may be used in place of those just described, and a sequence of erase and write patterns may be repeated one or more times.

As shown in Fig. 5, the embedded flash memory 409 is included in a microcontroller 404. The microcontroller 404 includes various other functional units that are common to microcontrollers. In the example shown, the microcontroller 404 includes an instruction decoder 512 to initially process instructions, registers 515 to store operands used by instructions as they are executed, SRAM 532 to store data processed by the instructions, and various other functional units (e.g., a program counter 509, timer 518, interrupt unit 524, etc.) As shown, the microcontroller 404 also includes a central processing unit (CPU) 527, which itself includes an arithmetic logic unit (ALU) 529. The microcontroller 404 may include other units (not shown), such as, for example, analog units (e.g., output drivers or digital-to-analog converters), additional logic units or other memories. Devices having embedded flash memory may take many forms, and the exact form is not critical to this document.

Fig. 6 is a block diagram illustrating additional details of the embedded flash memory 409 and the flash controller 503 that are shown in Fig. 5. As described above, embedded flash memory 409 is generally arranged in "pages." As shown in Fig. 6, the embedded flash memory 409 has four pages 621, and each page has four words. Fig. 6 is simplified for the purposes of illustration. An actual flash device would generally have more pages, and each page would have more words. For example, a typical embedded flash memory may be arranged as 512 pages, where each page stores 512 bytes of data. In addition, the embedded flash memory 409 has a page buffer 624 that is used to write data to the flash pages 621. The page buffer 624 generally has the same capacity as an individual page of the embedded flash memory 409, such that the page buffer 624 may fill one page of flash memory. Other sizes including larger and smaller sizes for the page buffer 624 are possible. Data is generally first written to the page buffer 624, and the contents of the page buffer are then transferred to a particular page 621.

The page buffer 624 may be indirectly accessed through registers. For example, the embedded flash memory 409 may include an address register 627, a data register 630 and a command register 633. Writing a word to the page buffer 624 may involve writing a value in the address register 627, specifying the word address within the page buffer 624; writing a data value in the data register 630, and writing a command that causes a state machine (not shown) within the embedded flash memory 409 to transfer the contents of the data register 630 to the word in the page buffer 624 that corresponds to the contents of the address register 627. This process may be repeated for each word in the page buffer 624, and when the page buffer 624 is full, it may be transferred to a page of memory. To transfer the page buffer 624 to a page of memory, an address of the page may be written to the address register 627, and a command may be written to the command register 633 — the command specifying that the page buffer 624 is to be transferred to a page having an address that corresponds to the contents of the address register 627.

The embedded flash memory 409 may perform other operations in response to various other commands. For example, writing certain values to the address register 627 and command register 633 may cause the page buffer 624 to be erased. In response to other commands, individual pages may be erased, the entire device may be erased, values may be read, or other operations may be performed.

In some implementations, a word may be a single byte, and in some implementations, a word may be two or more bytes. The size of the registers 627, 630 and 633 may vary accordingly, and may further vary based on the width of a data bus 605 through which the embedded flash memory 409 is accessed. For example, in implementations with two-byte words and a one-byte bus 605, the data registers may each include two registers — a "high" register and a "low" register — and writing data to a page of memory may include additional cycles not described above.

The flash controller 503 may execute a sequence that includes erasing data in the embedded flash memory 409 and writing specific patterns. Such a sequence may be repeated several times in order to configure the embedded flash memory 409 by dissipating charge that may have accumulated during a fabrication process. In some implementations, to determine a number of sequences of erase and write operations necessary to configure the embedded flash memory 409, the flash controller 503 may measure a voltage associated with a flash write operation (e.g., voltage corresponding to an output of an internal charge pump (not shown) used in a flash write operation). The voltage may reflect a level of accumulated charge remaining in the embedded flash memory 409. In some implementations, a number of sequences of erase and write operations may be determined based on whether a pattern is successfully read back after having been written to the embedded flash memory 409. A comparator 612 may be used for this purpose. For example, if the pattern read back from the flash memory 409 matches the pattern written (as determined by the comparator 612), accumulated charge may be deemed to be sufficiently dissipated. If the pattern read back does not match the pattern written, the embedded flash memory may still include accumulated charge, and one or more additional sequences may be required to further dissipate the charge. If another sequence is needed, a finite state machine 615 may execute another sequence of erase and write operations.

To cycle or configure memory, the finite state machine 615 may employ a pattern generator 618 and an address generator 609. The pattern generator 618 may store or generate specific patterns that are useful to cycling the embedded flash memory 409, such as all zeros 618a, a checkerboard pattern 618b, or an inverse checkerboard pattern 618c. In some implementations, the pattern generator 618 may also store or generate an all Is pattern (not shown); in other implementations, the finite state machine 615 may perform an erase operation to write all Is to the embedded flash memory 409. The address generator 609 may be used to generate an address that appropriately identifies a word within the page buffer 624 or a page within the embedded flash memory 409. The address generator 609 may be a complex counter that increments based on the state of the finite state machine 615 and the internal architecture of the embedded flash memory 409. For each word of each page of the embedded flash memory device 409, the flash controller 503 may write an appropriate address value to the address register 627, a data value to the data register 630, and command value to the command register 633, in order to fill and transfer the page buffer 624 to each actual page of the embedded flash memory 409.

By employing the finite state machine 615 and the pattern generator 618, the flash controller 503 may free up devices outside of the flash controller from having to repeatedly write data to the embedded flash memory 409. For example, the flash controller 503 may initiate the above-described information process in response to a single command received via an interface 606, which may be coupled to the serial test interface 412 that is shown in the Fig. 5. The flash controller 503 may also free up external devices from having to write data in accordance with the particular internal architecture of the embedded flash memory 409. Rather, with a single command to the flash controller 503, a cycling operation for the embedded flash memory 409 may be automated, regardless of the internal architecture of the embedded flash memory 409 (details of which are instead captured in the finite state machine 615). Writing the single command to the flash controller 503 may be completed in one bus cycle. (One bus cycle generally refers to a single transaction between two processing units; thus, in one bus cycle, the finite state machine 615 in the flash controller 503 can write a value to one register in the embedded flash memory 409.)

Since the single command may invoke the flash controller 503 to begin cycling memory, further bus cycles (external to the flash controller 503) may be unnecessary to actually carry out the memory configuration. Therefore, other testing external to the flash controller 503 may be performed substantially concurrently with the flash configuration.

Use of the flash controller 503 as described above may significantly free up a serial interface, which may otherwise be used to cycle memory. In addition, the flash controller 503 may provide a level of "abstraction," that hides the internal architecture of the embedded flash memory 409 from devices external to the flash controller 503. That is, devices outside of the flash controller 503 may not need to track words within a page buffer or pages within an embedded flash memory device.

Fig. 7 is a flow diagram of a method for concurrently configuring flash memory and performing other testing. Referring to Fig. 4, the method 700 may be used to initiate configuration of the embedded flash memory 409 from the serial test interface 412, while substantially concurrently testing other functional units, such as, for example, the functional unit 427 within the microcontroller 404, or the component 405.

The method includes receiving a command to configure flash memory (704). For example, the tester 416 (shown in Fig. 4) may issue a command via the serial interfaces 415 and 412 to configure the embedded flash memory 409; the command may be appropriately formatted such that it is relayed to the microcontroller 404; and the command may be received by the interface 606 in the flash controller 503 (see Figs. 2 and 3).

The method 700 configures the embedded flash memory 409 (707). For example, receipt of the command by the flash controller 503 may cause the finite state machine 615 to begin configuring the embedded flash memory 409 (710). More particularly, the finite state machine 615 may cause appropriate values to be written to registers 627, 630 and 633 to cause each page 621 of the embedded flash memory 409 to be erased (713). Subsequently, the finite state machine 615 may cause appropriate values to be written to the registers 627, 630, and 633 to cause specific data patterns to be written (716) to each page 621 of flash memory 409. The finite state machine 615 may cause the pattern generator 618 to generate, or otherwise provide, a data pattern for the flash memory 409. The provided data may be loaded into flash pages 621 by being first written to the page buffer 624 through appropriate writes to the address register 627, data register 630 and command register 633, as controlled by the finite state machine 615. To generate appropriate addresses, the finite state machine 615 may employ the address generator 609.

In some implementations, the sequence 710 of erasing (713) the flash and writing (716) a pattern may be automatically repeated (719) a predetermined number of times. For example, the flash 409 may first be erased (713), then written (716) with an all Os pattern 618a, then erased (713), then written (716) with a checkerboard pattern 618b, then erased (713), then written (716) with an inverse-checkerboard pattern. In some implementations, the entire example erase-write-erase-write- erase- write sequence may also be repeated a variable number of times. The variable number may depend on whether accumulated charge from a fabrication process of the flash memory 409 has been sufficiently dissipated. Whether any accumulated charge has been sufficiently dissipated may be determined (722) in a number of ways. In some implementations, a voltage may be measured that is associated with a charge pump (not shown) internal to the embedded flash memory 409. Accumulated charge that has not been sufficiently dissipated may affect this voltage. Thus, if the voltage is within one range, the finite state machine 615 may determine (722) that accumulated charge has not been sufficiently dissipated; if the measured voltage is within another range, the accumulated charge may be deemed to have been dissipated, and the sequence may not be repeated.

In some implementations, other methods may be used to determine (719) whether to repeat the example erase-write (or e.g., erase-write-erase-write-erase- write) sequence. For example, the finite state machine 615 may cause data to be read back from the embedded flash memory 409 and compared, by the comparator 612, to the last data pattern written to the flash memory 409. If the pattern read back does not match the last-written pattern, the finite state machine 615 may execute another example sequence. As another example, the sequence may simply be repeated a predetermined number of times. More particularly, the sequence of erasing (713), writing (716) an all Os pattern 618a, erasing (713), writing (716) a checkerboard pattern 618b, erasing (713), and writing (716) an inverse-checkerboard pattern 618c may be repeated, for example, five times. In some implementations, the predetermined number of times may be hard-coded into the finite state machine 615, based on, for example, initial empirical testing of particular flash memory, during the design and verification of the particular embedded flash memory 409. In some implementations, the predetermined number of times may be specified in a command that is received by the flash controller 503 to configure the embedded flash memory 409. For example, the flash controller 503 may receive, via the serial interface 412 and the interface 606, a command having the format CYCLE_FLASH n, where n specifies a number of predetermined sequences to execute.

Substantially concurrently with the action 707 configuring the embedded flash memory 409, the method 700 tests or otherwise commands, monitors or interfaces with (728) at least one additional functional unit. For example, while the flash controller 503 is configuring the embedded flash memory 409 in response to a command received from the serial test interface 412, other commands may be received over the same serial test interface 412 to test one or more other functional units (728). More specific examples are now provided. For example, the tester 416 may test, via the serial interfaces 415 and 412, functionality of the component 405 (731). Alternatively, the tester 416 may test functionality of a functional unit 427 that is internal to the device 404, which includes the embedded flash memory 409 (E.g., SRAM 532) (734). The tester 416 may test functionality of another functional unit internal to the device 404 (e.g., the instruction decoder 512) (737). The tester 416 may test connectivity between various components (e.g., connectivity between pin 419 and pin 420) (740). (Note that as used herein, "functional component" includes PCB traces or other connections between devices whose connectivity may be verified through testing, such as boundary scan testing or direct-probe testing (e.g., with a "bed- of-nails" test fixture)).

The method 700 may provide status of the configuration and testing (743). For example, in some implementations, after the flash memory is configured and at least one of other functional components are tested (728-740), status may be provided, for example, via the serial test interface 412, or through a status bit or status signal. In some implementations, failure of the configuration process 707 or of any other test 728-740 may cause the method 700 to immediately provide (743) status and/or terminate, rather than continuing on with other tests.

Implementations may be embodied, at least in part, in hardware or software or in any combination thereof. Hardware may include, for example, analog, digital or mixed-signal circuitry, including discrete components, integrated circuits (ICs), or application- specific ICs (ASICs). Implementations may also be embodied, in whole or in part, in software, firmware or microcode, which may cooperate with hardware. Processors for executing instructions may retrieve instructions from a data storage medium, such as EPROM, EEPROM, NVRAM, ROM, RAM, a CD-ROM, a HDD, and the like. Computer program products may include storage media that contain program instructions for implementing implementations described herein.

A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of this disclosure. For example, certain patterns of data and certain sequences are described above for purposes of illustration only; other patterns or sequences may also be used. As another example, implementations may include a parallel test or programming interface in place of a serial interface. Accordingly, other implementations are within the scope of the following claims

Claims

WHAT IS CLAIMED IS:

1. A method of writing to a page of flash memory that is arranged to contain a first number of logical data units, the method comprising:

(a) receiving at a local controller from a remote controller via a bus, a write command comprising one logical data unit and an address;

(b) translating the write command to a plurality of flash memory commands;

(c) executing the flash memory commands to transfer the one logical data unit to a page buffer within the flash memory; (d) executing (a)-(c) a number of times equal to a first number, in order to fill the page buffer; and

(e) causing contents of the page buffer to be transferred to the page of flash memory.

2. The method of claim 1, where the bus is a serial test interface that is compliant with IEEE (Institute of Electrical and Electronics Engineers) standard 1149.1 or 1149.1a.

3. The method of claim 1, where the bus is a programming interface, and the remote controller is a dedicated device programmer.

4. The method of claim 1, where the flash memory and the local controller are embedded in a microcontroller device, and where the remote controller is external to microcontroller device.

5. The method of claim 1, where the logical data unit comprises one byte of data or one word of data, the one word comprising a plurality of bytes of data.

6. The method of claim 1, where translating the write command comprises generating a page buffer address that corresponds to the address.

7. The method of claim 1, further comprising calculating a page address corresponding to the page of flash memory.

8. The method of claim 7, where calculating the page address comprises calculating the page address based on at least one address received in (a).

9. A method of writing to a page of embedded flash memory comprising:

(a) receiving at an embedded flash programming unit, via a bus and from a controller remote from the embedded flash programming unit, a two-operand write command, the two-operand write command having a first operand specifying an address and a second operand specifying a data unit;

(b) translating the two-operand write command into a plurality of flash commands; (c) executing (a)-(b) for a number of two-operand write commands corresponding to a number of data units in a page buffer;

(d) executing the flash commands to fill the page buffer; and

(e) upon filling the page buffer, writing contents of the page buffer to the page of embedded flash memory.

10. The method of claim 9, further comprising suspending executing the plurality of commands to fill the page buffer while writing contents of the page buffer to the page of flash memory.

11. The method of claim 10, wherein suspending executing the plurality of commands comprises suspending translating the two-operand write command into the plurality of commands.

12. The method of claim 10, wherein suspending executing the plurality of commands comprises generating a halt signal to prevent the controller from transmitting, via the bus, additional two-operand write commands to the embedded flash programming unit.

13. A system for storing data comprising: a flash memory being arranged in a plurality of pages and having a page buffer, each page of the plurality of pages storing a first number of logical data units, the page buffer also storing the first number of logical data units; and a flash programming unit comprising: an interface coupled to a controller remote from the flash programming unit that receives two-operand write commands from the controller, each two-operand write command having a first operand specifying an address and a second operand specifying at least a portion of a logical data unit; a translation unit that translates each two-operand write command to a plurality of flash commands, the plurality of flash commands causing the at least a portion of a logical data unit to be written to the page buffer; and a controller to initiate the writing of the contents of the page buffer to a page of the plurality of pages when the page buffer has been written with the first number of logical data units.

14. The system of claim 13, wherein the logical data unit comprises one byte of data or one word of data, the one word comprising a plurality of bytes of data.

15. The system of claim 13, wherein the interface suspends receiving the two-operand write commands while the page buffer is written to the page of the plurality of pages .

16. A method of testing an integrated circuit that has a serial interface, embedded memory, an embedded memory controller and at least one functional unit, the method comprising: receiving, from a serial interface, a first command to cycle an embedded memory of an integrated circuit; cycling the embedded memory with an embedded memory controller in response to receiving the first command; during the cycling of the embedded memory, receiving a second command from the serial interface to test at least one functional unit of the integrated circuit; and executing the second command to test the at least one functional unit substantially concurrently with the cycling of the embedded memory.

17. The method of claim 16, where cycling the embedded memory comprises executing one or more sequences of initiating erasure of the embedded memory and initiating the writing of data having a specific pattern to the embedded memory.

18. The method of claim 17, where the specific pattern is selected from the group consisting of an all Os pattern, an all Is pattern, a checkerboard pattern, and an inverse-checkerboard pattern.

19. The method of claim 17, where executing one or more sequences comprises:

(a) initiating erasure of the embedded memory; (b) initiating the writing of data having a first pattern to the embedded memory;

(c) initiating erasure of the embedded memory;

(d) initiating the writing of data having a second pattern to the embedded memory, wherein the first pattern and the second pattern are different; and

(e) repeating (a)-(d) until a voltage level associated with initiating the writing of data crosses a predetermined threshold level.

20. The method of claim 16, further comprising determining whether to repeat a sequence of writes to the embedded memory based on whether a charge is substantially dissipated in the embedded memory.

21. The method of claim 16, further comprising determining whether charge accumulated in the embedded memory during a fabrication process is substantially dissipated.

22. The method of claim 21, where determining whether the charge is substantially dissipated comprises writing data having a test pattern to the embedded memory, reading data back from the embedded memory, and determining whether the data read back from the embedded memory exactly corresponds to the test pattern.

23. The method of claim 16, where the at least one additional functional unit is selected from the group consisting of an instruction decoder, a program counter, a timer, a comparator, an interrupt unit, an arithmetic logic unit (ALU), a microcontroller, an analog unit, an additional logic unit, and a memory; and where testing the at least one additional functional unit comprises configuring the at least one additional functional unit or verifying that the at least one additional functional unit was properly fabricated.

24. The method of claim 16, where the serial interface is a boundary scan interface that complies with IEEE (Institute of Electrical and Electronic Engineers) Standard 1149.1 or 1149.1a.

25. The method of claim 16, further comprising providing status output after completing cycling of the embedded memory and executing the second command.

26. The method of claim 25, where the embedded memory is flash memory; cycling the flash memory comprises cycling flash memory having at least 4096 bytes; executing the second command to test the at least one functional unit comprises testing a reduced instruction set microcontroller; and providing status output comprises providing status output within 200 milliseconds (mS) of receiving the command to cycle the flash memory, the status output specifying that substantially all accumulated charge has been dissipated by cycling the embedded memory and further specifying that the reduced instruction set microcontroller has passed a functional test.

27. A method of testing an integrated circuit that has an interface, embedded memory, an embedded memory controller and at least one functional unit, the method comprising: receiving, from an interface, a first command to cycle an embedded memory of an integrated circuit; cycling the embedded memory with an embedded memory controller in response to receiving the first command; during the cycling of the embedded memory, receiving a second command from the interface to test at least one functional unit of the integrated circuit; and executing the second command to test the at least one functional unit substantially concurrently with the cycling of the embedded memory.

28. The method of claim 27, where the interface is a parallel interface.

29. The method of claim 27, where executing one or more sequences comprises:

(a) initiating erasure of the embedded memory;

(b) initiating the writing of data having a first pattern to the embedded memory;

(c) initiating erasure of the embedded memory;

(d) initiating the writing of data having a second pattern to the embedded memory, wherein the first pattern and the second pattern are different; and (e) repeating (a)-(d) until a voltage level associated with initiating the writing of data crosses a predetermined threshold level.