EP2005551A2

EP2005551A2 - Polyphase power conditioning circuits

Info

Publication number: EP2005551A2
Application number: EP07754755A
Authority: EP
Inventors: Michael W. Januszewski; Leonard E. Webster
Original assignee: Leveler LLC
Current assignee: Leveler LLC
Priority date: 2006-03-31
Filing date: 2007-04-02
Publication date: 2008-12-24
Also published as: EP2005551A4; JP2009533012A; CA2647813A1; WO2007117449A4; AU2007235535A1; WO2007117449A3; ZA200808425B; WO2007117449A2; WO2007117449A8; AU2007235535B2

Abstract

A polyphase power conditioning circuit for conditioning power supplied by a power source at a nominal frequency over line, neutral and ground conductors for each of a number of phases includes first, second and third impedances coupled to the line, neutral and ground conductors, respectively, and to output lines for each phase. Each of the impedances prevents power at frequencies greater than the nominal frequency from reaching the output lines.

Description

Polyphase Power Conditioning Circuits

TECHNICAL FIELD

The present application relates generally to power conditioning circuits and methods, and more particularly, to power conditioning circuits and methods that protect attached polyphase load equipment from voltage and current surges due to, for example, lightning strikes or other power disturbances.

BACKGROUND ART

Power conditioning circuits have long been used to protect sensitive load equipment from transients caused by lightning strikes, noise and other power line disturbances. Traditionally, filter elements are used in the line and neutral conductors which trap and/or shunt unwanted power frequencies away from the load. See, for example, Speet et al. U.S. Pat. No. 4,814,941 and Taylor et al. U.S. Pat. No. 5,490,030.

Muelleman U.S. Pat. No. 5,448,443 discloses a power conditioning device and method including an isolation transformer having primary and secondary sides and a ground impedance connected between the secondary side of the isolation transformer at a safety ground and an earth ground. The Muelleman device prevents ground current loops by redirecting transient ground currents to neutral, but does not provide current limiting or noise suppression.

Redbum et al. U. S. Patent No. 6,166,458, owned by the assignee of the present application and the disclosure of which is hereby incorporated by reference herein, discloses a power conditioning circuit for conditioning single-phase power supplied by a power source at a nominal frequency over line, neutral and ground conductors. The power conditioning circuit includes first through third impedances coupled to the line, neutral and ground conductors, respectively, and to output lines wherein each of the impedances prevents power at frequencies greater than the nominal frequency from reaching the output lines. Preferably, the first through third impedances comprise first through third inductors coupled in series with the line, neutral and ground conductors, respectively, between the power source and the output lines. Means may also be provided for limiting voltages across the line, neutral and ground conductors. The limiting means may comprise at least one metal oxide varistor or at least one zener diode. The power conditioning circuit is simple in design, yet effective to limit damaging transients.

SUMMARY

A polyphase power conditioning circuit for conditioning power supplied by a polyphase power source at a nominal frequency over line, neutral and ground conductors for each of a number of phases includes first, second and third impedances coupled to the line, neutral and ground conductors, respectively, for each phase and to output lines for each phase. Each of the impedances prevents power at frequencies greater than the nominal frequency from reaching the output lines.

The present power conditioning circuit traps unwanted frequencies and/or shunts such frequency components between the line, neutral and ground conductors of each of a plurality of phases so that such frequencies are diverted away from sensitive load equipment to prevent damage thereto.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 comprises a schematic diagram of a first embodiment of a polyphase power conditioning circuit;

FIG. IA comprises a schematic diagram of a second embodiment of a polyphase power conditioning circuit; and

FIGS. 2A and 2B are schematic diagrams of alternative embodiments of a polyphase power conditioning circuit.

BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENT It should be noted that like elements are given like reference numerals in the drawings and specification.

Referring first to FIG. 1, a power conditioning circuit 20 is connected between polyphase line, neutral and ground conductors 22A-22C, 24A-24C, and 26A-26C and output lines 28A-28C, 30A-30C, and 32A-32C. The line, neutral and ground conductors 22A-22C, 24A-24C, and 26A-26C may be connected to a commercial source of power 33 or any other power source. The output lines 28A-28C, 30A-30C, and 32A-32C may be connected to one or more polyphase loads 34 in either delta or wye (star) configurations. Although the power source 33 and load(s) 34 are shown as being three-phase, it should be understood that the power source and load(s) may have any number of phases more than one.

The power conditioning circuit 20 further includes, for each phase, first, second and third inductors Ll, L2 and L3 connected in series between the line, neutral and ground conductors 22, 24 and 26 and the output lines 28, 30 and 32 for that phase. More particularly, a first inductor Ll A is connected in series between the line conductor 22 A and the output line 28 A whereas inductors LIB and LlC are connected in series between the neutral conductor 24A and the output line 3OA and between the ground conductor 26A and the output line 32A. Inductors L2A, L2B, and L2C are respectively connected in series between the line conductor 22B and the output line 28B, between the neutral conductor 24B and the output line 3OB, and between the ground conductor 26B and the output line 32B. In like fashion, inductors L3A, L3B, and L3C are respectively connected in series between the line conductor 22C and the output line 28C, between the neutral conductor 24C and the output line 30C, and between the ground conductor 26C and the output line 32C.

First through third metal oxide varistors MOVl, M0V2, and MOV3 are preferably connected across the line and neutral conductors 22, 24, the line and ground conductors 22, 26 and the neutral and ground conductors 24, 26, respectively, - for each phase. Thus, for example, metal oxide varistors MOVl-I, MOV1-2, and MOVl -3 are connected across the line, neutral and ground conductors 22 A, 24A, and 26A, respectively of phase A. Likewise, metal oxide varistors MOV2-1, MOV2-2, and MOV2-3 are connected across the line, neutral and ground conductors 22B, 24B, and 26B, respectively of phase B while metal oxide varistors MOV3-1, MOV3-2, and MOV3-3 are connected across the line, neutral and ground conductors 22C, 24C, and 26C, respectively of phase C.

Further, crowbar circuits 40A-40C may be coupled between the neutral and ground output lines 3OA and 32A, 3OB and 32B, and 30C and 32C, respectively. The crowbar circuits 40A-40C may be identical to one another and hence only the crowbar circuit 4OA will be described in detail, it being understood that the reference numerals and designations for phases B and C differ only in the use of "B" or "C" as a suffix for each element. The crowbar circuit 4OA includes a pair of cross-connected SCR' s, triacs, or other controllable switches QlA and Q2A coupled across the neutral and ground output lines 30A and 32A, and a biasing circuit 42A and 44A associated with the switches QlA and Q2A, respectively. The biasing circuit 42A includes a zener diode DlA and a resistor Rl A whereas the biasing circuit 44A comprises a series connection of a zener diode D2A and a resistor R2A

If desired, capacitors and/or silicon avalanche diodes may be coupled between conductors on the power supply side and/or the load side. These elements (or any other additional circuit elements) may be substituted for or used in addition with any of the circuit elements described above. For example, metal oxide varistors MOV 1-4, 1-5, 1-6, 2-4, 2-5, 2-6, 3-4, 3-5, and 3-6 may be coupled across the output lines 28A- 28C, 30A-30C, and 32A-32C in the fashion shown in FIG. IA. Alternatively a like number of silicon avalanche diodes may be coupled across the lines 28, 30. and 32 as shown in FIG. IA, if desired.

Preferably, although not necessarily, the inductance values of all of the inductors L1-L3 are equal. Also all of the metal oxide varistors MOVl and MOV2 must be sized large enough to dissipate large voltage spikes caused, for example, by a lightning strike and should, for example, typically have clamping voltages on the order of 330-400 volts, although substantially lower clamping voltage ratings may be employed in certain cases.

In operation, transients appearing on any of the line, neutral and ground conductors 22, 24 and 26 of any of the phases A, B, or C having one or more frequency components in excess of the nominal (typically 60 Hz) frequency of the power supplied thereto are attenuated by the inductors L1-L3, which have an increasing impedance with frequency. In addition, the metal oxide varistors MOVl- MO V3 limit the voltage magnitudes appearing across the line, neutral and ground conductors 22-26 for each phase.

The actual inductance values for the inductors L1-L3 may be selected so as to obtain the desired filtering characteristics on the lines 28-32.

Referring next to FIGS. 2A and 2B, alternative circuits are disclosed that utilize fewer components. The embodiment of FIG. 2A is particularly useful for wye (star) polyphase connected loads, although the circuit could be used for delta connected loads, if desired (in the latter case, no connection would be made to the neutral and possibly the ground load lines). The embodiment of FIG. 2B is useful with delta connected loads. Beginning with FIG. 2A, a polyphase power conditioning circuit 58 includes inductors L4-L6 connected in series between the phase A, phase B, and phase C input conductors 6OA, 6OB, and 6OC and output lines 62A, 62B, and 62C, respectively. Inductors L7 and L8 are connected in series between neutral and ground input conductors 66, 68 and neutral and ground output lines 70, 72, respectively. A pair of metal oxide varistors MOV4 and MOV5 are connected between the phase A and phase B input conductors, a metal oxide varistor MOV6 is connected between the phase C input conductor 6OC and the neutral input conductor 66, and a metal oxide varistor MOV7 is connected between the neutral and ground input conductors 66, 68, respectively.

Referring next to FIG. 2B, a polyphase power conditioning circuit 80 is identical to the circuit 58 of FIG. 2A, with the exception that there is no neutral input conductor 66 and the MOV 6 and the inductor L7 are omitted. In addition, the MOV 7 is connected between the phase C input conductor 6OC and the ground input conductor 68.

If necessary or desirable, crowbar circuits similar or identical to the crowbar circuits 40A-40C of FIG. 1 described above may be connected between any or all of the output lines 62A-62C, 70, and/or 72 in either of the circuits of FIGS. 2A and 2B.

It should further be noted that the circuits of FIGS. 1, 2 A and/or 2B can be modified by omitting and/or substituting for one or more of the elements therefrom. Thus, for example, one or more of the varistors MOVl -MO V7 of one or more of the phases may be omitted, as may one or more of the crowbar circuits 40A-40C. Alternatively, or in addition, any or all of the circuit elements shown in the FIGS, of U. S. Patent No. 6,166,458 may be utilized in one or more of the phase interconnections between the power source and load(s), as desired.

In each embodiment, protection against transients resulting from line disturbances is afforded in a simple and inexpensive manner.

Claims

I/WE CLAIM

1. A power conditioning circuit for conditioning power supplied by a power source over conductors in a polyphase system, comprising: first and second phase input conductors; and first and second inductors connected in series between the first and second phase input conductors and first and second phase output lines, wherein all of the power flowing between the first and second phase input conductors and the first and second phase output lines flows through the first and second inductors.

2. The power conditioning circuit of claim 1, including a metal oxide varistor connected across the first phase input conductor and a ground conductor.

3. The power conditioning circuit of claim 1, including a metal oxide varistor connected across the first phase output line and the ground conductor.

4. The power conditioning circuit of claim 1, including a third inductor connected between a neutral input conductor and a neutral output line.

5. The power conditioning circuit of claim 1, wherein inductance values of the first and second inductors are equal.' <

6. A power conditioning circuit for conditioning power supplied by a power source over conductors in a polyphase system, comprising: first, second, and third inductors coupled in series between first, second and third phase line conductors of the power source, and corresponding first, second, and third output line conductors, respectively, wherein all of the power flowing between the power source and the first, second and third output lines flows through the first, second and third inductors, each of the first, second and third inductors blocking power at frequencies greater than the nominal frequency from passing therethrough; and fourth and fifth inductors coupled in series between neutral and ground conductors of the power source, respectively, and neutral and ground output lines, respectively, wherein all of the power flowing between the power source and the neutral and ground output lines flows through the fourth and fifth inductors, each of the fourth and fifth inductors blocking power at frequencies greater than the nominal frequency from passing therethrough.

7. The power conditioning circuit of claim 6, further including sixth and seventh inductors coupled in series between first and second additional neutral conductors of the power source and first and second additional neutral output lines, wherein all of the power flowing between the first and second additional neutral conductors of the power source and the first and second additional neutral output lines flows through the sixth and seventh inductors, each of the sixth and seventh inductors blocking power at frequencies greater than the nominal frequency from passing therethrough.

8. The power conditioning circuit of claim 6, further including eighth and ninth inductors coupled in series between first and second additional ground conductors of the power source and first and second additional ground output lines, wherein all of the power flowing between the first and second additional ground conductors of the power source and the first and second additional ground output lines flows through the eighth and ninth inductors, each of the eighth and ninth inductors blocking power at frequencies greater than the nominal frequency from passing therethrough.

9. The power conditioning circuit of claim 6, wherein the inductors have different inductance values.

10. The power conditioning circuit of claim 6, wherein the inductors have inductance values ranging from 0.2mH to 2.OmH.

11. The power conditioning circuit of claim 6, further including means for limiting voltages across the line, neutral and ground conductors of each phase.

10. The power conditioning circuit of claim 11, wherein the limiting means comprises a silicon avalanche diode and a metal oxide varistor coupled in parallel relationship.

12. The power conditioning circuit of claim 6, further including an additional means for limiting voltage across the neutral and ground conductors at a point between the inductors and the output lines.

13. The power conditioning circuit of claim 12, wherein the additional limiting means comprises two silicon controlled rectifiers (SCRs) connected in anti- parallel relationship.

14. The power conditioning cirbuit of claim 12, wherein the additional limiting means comprises two zener diodes connected in anti-parallel relationship.

15. The power conditioning circuit of claim 12, wherein the additional limiting means comprises a metal oxide varistor.

16. The power conditioning circuit of claim 12, wherein the additional limiting means comprises a silicon avalanche diode.

17. The power conditioning circuit of claim 12, wherein the additional limiting means comprises a double wound inductor.