EP1971925A2 - Procédés et systèmes destinés à restreindre l'utilisation d'un canal dma - Google Patents

Procédés et systèmes destinés à restreindre l'utilisation d'un canal dma

Info

Publication number
EP1971925A2
EP1971925A2 EP06846672A EP06846672A EP1971925A2 EP 1971925 A2 EP1971925 A2 EP 1971925A2 EP 06846672 A EP06846672 A EP 06846672A EP 06846672 A EP06846672 A EP 06846672A EP 1971925 A2 EP1971925 A2 EP 1971925A2
Authority
EP
European Patent Office
Prior art keywords
channel
access
dma
secure
privilege
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06846672A
Other languages
German (de)
English (en)
Other versions
EP1971925A4 (fr
Inventor
Gregory R. Conti
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/557,298 external-priority patent/US9740887B2/en
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Priority to EP06846672A priority Critical patent/EP1971925A4/fr
Publication of EP1971925A2 publication Critical patent/EP1971925A2/fr
Publication of EP1971925A4 publication Critical patent/EP1971925A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • G06F21/606—Protecting data by securing the transmission between two devices or processes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/82—Protecting input, output or interconnection devices
    • G06F21/85—Protecting input, output or interconnection devices interconnection devices, e.g. bus-connected or in-line devices

Definitions

  • This relates to data processing security in general; and, in particular, to methods and systems for restricting usage of a direct memory access (DMA) channel.
  • DMA direct memory access
  • Mobile electronic devices such as personal digital assistants (PDAs) and digital cellular telephones are increasingly used for electronic commerce (e-commerce) and mobile commerce (m-commerce).
  • Programs that execute on the mobile devices to implement e-commerce and/or m-commerce functionality may need to operate in a secure mode to reduce the likelihood of attacks by malicious programs (e.g., virus programs) and to protect sensitive data.
  • malicious programs e.g., virus programs
  • processors provide two levels of operating privilege: a first level of privilege for user programs; and a higher level of privilege for use by the operating system.
  • the higher level of privilege may or may not provide adequate security for m-commerce and e-commerce, given that this higher level relies on proper operation of operating systems with highly publicized vulnerabilities.
  • some mobile equipment manufacturers implement yet another third level of privilege, or secure mode, that places less reliance on corruptible operating system programs, and more reliance on hardware-based monitoring and control of the secure mode.
  • An example of one such system may be found in U.S. Patent Publication No. 2003/0140245, entitled "Secure Mode for Processors Supporting MMU and Interrupts.”
  • DMA channels are subject to security attacks that enable malicious hackers to break the secure mode described above without being detected by the hardware firewalls. Breaking the secure mode enables a malicious user to change a mobile electronic device's International Mobile Equipment Identity (IMEI) or defeat a Subscriber Identity Module Lock (SIMLOCK) mechanism.
  • IMEI International Mobile Equipment Identity
  • SIMLOCK Subscriber Identity Module Lock
  • a system comprises a processor and a direct memory access (DMA) subsystem coupled to the processor.
  • the system further comprises a component coupled to the DMA subsystem via an interconnect employing security rules, wherein, if the component requests a DMA channel, the DMA subsystem restricts usage of the DMA channel based on the security rules.
  • DMA direct memory access
  • a DMA subsystem comprises a configuration firewall configured to receive DMA channel configuration requests.
  • the DMA subsystem further comprises a violation handler coupled to the configuration firewall, wherein, if a received DMA channel configuration request violates security rules of the configuration firewall, a security violation signal is asserted by the configuration firewall to the violation handler.
  • a method comprises accessing a direct memory access (DMA) subsystem. The method further comprises determining if the access is a secure mode access and, if the access is determined to be a secure mode access, allowing a DMA channel to be configured as either one of a secure channel and a public channel.
  • DMA direct memory access
  • FIG. 1 shows a system in accordance with one or more embodiments.
  • FIG. 2 shows the system of FIG. 1 with qualifiers in accordance with one or more embodiments.
  • FIGS. 3A-3B show a DMA subsystem in accordance with one or more embodiments; and FIGS. 4-9 show methods of restricting DMA channel configurations in accordance with one or more embodiments.
  • Embodiments of the invention implement a hardware security architecture that interconnects a plurality of components compatible with Direct Memory Access (DMA) techniques.
  • DMA Direct Memory Access
  • the term "hardware security architecture” is intended to mean the mechanisms and/or methodologies that connect several initiators (e.g., Advanced RISC Machine (ARM) components, Digital Signal Processor (DSP) components, Direct Memory Access DMA components, or Universal Serial Bus (USB) components) to several targets (e.g., memory components or peripherals) while complying with security rules that guarantee or at least increase the security robustness of a system.
  • DMA- compatible components are integrated with the hardware security architecture such that DMA channel configurations support the security rules and/or hardware constraints of the hardware security architecture.
  • FIG. 1 shows a system 100 in accordance with one or more embodiments of the invention.
  • the system 100 shows components of a mobile device such as a cellular telephone, personal digital assistant (PDA), text messaging system, or a device that combines the functionality of a messaging system, personal digital assistant and a cellular telephone.
  • a mobile device such as a cellular telephone, personal digital assistant (PDA), text messaging system, or a device that combines the functionality of a messaging system, personal digital assistant and a cellular telephone.
  • PDA personal digital assistant
  • text messaging system or a device that combines the functionality of a messaging system, personal digital assistant and a cellular telephone.
  • the system 100 includes a multiprocessing unit (MPU) subsystem 102 having a MPU 104 coupled to an interrupt handler 106.
  • the MPU 104 includes a processor core 110 that executes programs and a core security controller (CSC) 112, which aids the MPU 104 in entering a secure mode for execution of secure programs on the core 110.
  • the core 110 may be any processor suitable for integration into a system on a chip (SoC), such as the ARM 1136 series of processors.
  • SoC system on a chip
  • the core 110 may be a processor that includes some or all of the functionality of the core security controller 112 as described herein, such as the ARM 1176 series of processors.
  • the ARM 1136 and 1176 technology may be obtained from ARM Holdings pic of Cambridge, United Kingdom, and/or ARM, Inc. of Austin, Texas, USA.
  • the MPU subsystem 102 couples to a DMA subsystem 122 that enables memory accesses between DMA-compatible components ("targets") of the system 100.
  • the DMA subsystem 122 has a DMA engine 124 with programmable DMA channels 134.
  • the DMA subsystem 122 also has internal registers 126 such as DMA channel configuration registers 128 and DMA channel rights registers 130.
  • the DMA channel configuration registers 128 are implemented to configure the DMA channels 134 as read channels or as read/write channels during DMA requests.
  • the DMA channel rights registers 130 control the access rights of each DMA channel 134.
  • interconnect qualifier or “qualifier” is intended to mean a signal embedded in an access (e.g., an Open Core Protocol (OCP) access).
  • OCP Open Core Protocol
  • the qualifier reflects the state of the component that initiated the access at the time the access was initiated.
  • the DMA subsystem 122 also may comprise DMA status registers, source address registers, destination address registers, DMA length registers, DMA control registers, or other registers (not shown for convenience).
  • the DMA subsystem 122 is interconnected to DMA-compatible components (i.e., the source locations or destination locations) via a hardware security architecture such as an L3 interconnect 116 having firewalls 150, 152, 154, and 156 and an L4 interconnection having a firewall 158.
  • the DMA subsystem 122 also comprises a configuration firewall 132 that allows and restricts the usage of DMA channel qualifiers as will later be described.
  • the L3 interconnect 116 and the L4 interconnect 140 described herein are implemented in some embodiments, alternative embodiments may implement other existing or future interconnect architectures.
  • the DMA-compatible components mentioned previously comprise a SDRAM Memory Scheduler (SMS) component 160 having a firewall 170, a General Purpose Memory Controller (GPMC) component 162, an on-chip read-only memory (ROM) 164, an on-chip random access memory (RAM) 166, and an Image Video Accelerator (IV A2) component 168.
  • SMS Secure Digital
  • GPMC General Purpose Memory Controller
  • ROM read-only memory
  • RAM on-chip random access memory
  • IV A2 Image Video Accelerator
  • additional components, fewer components or different DMA-compatible components may be included.
  • the system 100 further comprises an L4 interconnect core component 142 having logic that supports functions such as the Advanced Encryption Standard (AES), the Data Encryption Standard (DES) 5 the Secure Hash Algorithm 1 (SHAl), Public Key Authentication (PKA), Random Number Generators (RNG), Universal Asynchronous Receiver/Transmitters (UARTs), and General Purpose Input/Outputs (GPIOs).
  • AES Advanced Encryption Standard
  • DES Data Encryption Standard
  • SHAl Secure Hash Algorithm 1
  • PKA Public Key Authentication
  • RNG Random Number Generators
  • UARTs Universal Asynchronous Receiver/Transmitters
  • GPIOs General Purpose Input/Outputs
  • the L4 interconnect core component 142 may support additional functions, fewer functions or different functions.
  • the system 100 further comprises a control module 144 that interfaces the L4 interconnect 140 to the DMA subsystem 122. As shown, the firewall 132 of the DMA subsystem 122 is configured
  • the DMA channels 134 support usage of interconnect "qualifiers" that determine access rights to different protected memory spaces of the DMA-compatible components. Enforcement of the access rights associated with the interconnect qualifiers is based on firewalls such as the firewalls 150, 152, 154, 156, 158 and 132. In at least some embodiments interconnect qualifiers such as "MReqType”, “MReqPrivilege”, “MReqDebug” and “MReqSecure” are used. Table 1 shows a definition and description of these qualifiers. Table 1
  • IRQ interrupt request
  • FIQ fast interrupt request
  • a privilege mode access enables operations that are not available to user mode accesses.
  • qualifiers MReqType, MReqPrivilege, MReqDebug and MReqSecure are simply used for convenience in describing embodiments that implement ARM components. However, these qualifiers should also be understood as being applicable to any system with different modes and different security levels.
  • the DMA channels 134 are configured based on the different interconnect qualifiers. The DMA channel configuration process may occur once, periodically, or randomly (as needed).
  • the configuration firewall 132 is implemented to allow or restrict certain qualifiers on the DMA channels 134.
  • the firewall 132 is accessible and the DMA channels 134 are configurable (or re-configurable) via the L4 interconnect 140.
  • the MPU 104 accesses the firewall 132 via the L4 interconnect 140 to configure the DMA channels 134.
  • in-band errors refer to errors that are embedded in a response transaction to the initiator.
  • a response transaction may include status information such as an "OK” indicator or a "FAIL” indicator that is returned to the initiator.
  • out-band errors refer to errors that are out of the initiator execution flow.
  • the firewalls may generate error signals that are outside the initiator execution flow.
  • the out-band errors can be used to update status registers and/or to cause an interrupt such as the MPU interrupt 138 previously mentioned.
  • the MPU interrupt 138 can be used to notify a user of the system 100, to disable one or more functions of the system 100, or to perform some other action in response to a security violation.
  • FIG. 2 shows the system 100 of FIG.
  • the qualifiers e.g., MReqType, MReqPrivilege, MReqDebug and MReqSecure
  • the MPU 104 issues access requests or transactions with the qualifiers 182 to the L3 interconnect 116.
  • other components 108 e.g., Digital Signal Processors (DSPs), modems, or videos accelerators (IV A2)
  • DSPs Digital Signal Processors
  • IV A2 videos accelerators
  • These access requests or transactions along with the qualifiers 182 are propagated through the L4 interconnect 140 to the firewall 132 of the DMA subsystem 122.
  • the function of the firewall 132 is shown in FIGS. 3A-3B in greater detail.
  • FIGS. 3A-3B show a DMA subsystem 122 in accordance with one or more embodiments.
  • the DMA subsystem 122 comprises the firewall 132 which, in some embodiments, couples to the L4 interconnect 140 via an on-chip protocol (OCP) bus 148.
  • OCP on-chip protocol
  • the firewall 132 receives an address signal "MADDR”, a data signal “MDATA”, qualifier bits signals "MREQINFO”, and a command signal "MCMD” from the L4 interconnect 140.
  • the MREQINFO signals include the qualifiers MReqSecure, MReqPrivilege, MReqType, and MReqDebug as will later be described.
  • the MADDR, MDATA, MREQINFO, and MCMD signals are representative of access requests or transactions that are issued by the MPU 104 or other components 108 that support the system's hardware security architecture.
  • the firewall 132 uses these signals to configure DMA channel 0 for use with a given access request or transaction or to assert the security violation signal 136.
  • the function of the firewall 132 with respect to DMA channel 0 is illustrated using pseudo-code.
  • the pseudo-code represents software, firmware, or hardware functions of the firewall 132 in response to the MADDR, MDATA, MREQINFO, and MCMD signals and the contents of the DMA registers 126.
  • the function of the firewall 132 in accordance with at least some embodiments, is additionally or alternatively described hereafter.
  • the security violation signal 136 is used to generate in-band errors and/or out-band errors.
  • the violation handler 192 receives the security violation signal 136 from the firewall 132 and asserts an in-band error "SRESP" 137 to the initiator that accessed the firewall 132 (via the L4 interconnect 140). Any out-band error generated due to the security violation signal 136 may be converted into an MPU interrupt 138 that enables the system 100 to appropriately handle the security violation.
  • DMA subsystem 122 also comprises DMA registers 126 that support the configuration and access rights of DMA channels 0 to "n".
  • FIGS. 3A- 3B illustrate DMA registers associated with DMA channel 0.
  • the DMA channel configuration registers 128A-128N and DMA channel rights register 130 are associated with DMA channel 0.
  • Additional DMA registers associated with DMA channels 1 to n are not shown for convenience. Accordingly, parts of the description herein focus on one channel (DMA channel 0), though the discussion should be understood as applying to other channels as well. Also, other logic besides registers could be implemented in some embodiments. Using registers is simple one way to configure DMA channels to support the different security levels of the system 100. Table 2 shows a summary of DMA registers 126 in accordance with some embodiments. Table 2
  • DMA channels 0 to n a plurality of DMA channels (e.g., channels 0 to n) are illustrated. For each channel, parameters such as offset, register name, description, size and access are described.
  • the DMA channel 0 is associated with a plurality of configuration registers 128A-128N having the names "DMA_CHANNEL0_CONF0" to "DMA_CHANNEL0_CONFn ". These configuration registers enable read or read/write operations on DMA channel 0.
  • the DMA channel (e.g., DMA channel 0) is configured for read/write operations. Otherwise, the DMA channel 0 is configured for read operations only.
  • the MReqType qualifier is not used to Configure the channel configuration registers 128A-128N and the DMA channel rights register 130, but is provided during DMA channel operations by the DMA subsystem 122 to distinguish between data accesses intended to store data in a non-executable memory space and instruction accesses intended to store data in an executable memory space.
  • Table 3 shows a summary of bits in a DMA_CHANNEL0_CONFn register in accordance with some embodiments. Table 3
  • DMA_CHANNEL_CONFn register parameters such as bits, field name, function, reset value and access are illustrated.
  • the DMA_CHANNEL0_CONFn register is a 32-bit register.
  • the DMA_CHANNEL0_CONFn register is configured such that if an access request or transaction on the DMA channel 0 includes a MreqDebug, MReqPrivilege, MReqType or MReqSecure qualifier, the DMA channel 0 allows read/write operations. Otherwise, the DMA channel 0 allows read operations only.
  • the DMA_CHANNEL0_CONFn register may have a reset value OxO.
  • the access rights of DMA channel 0 are set by a DMA channel rights register 130 (named "DM A_CH ANNELO").
  • DMA_CHANNEL0 register controls the access rights based on data bits which correspond to qualifiers such as MReqType, MReqPrivilege, MReqDebug and MReqSecure.
  • the DMA_CHANNEL0 register also controls a lock bit which enables/disables the qualifier bits associated with DMA_CHANNEL0 qualifier bits from being modified.
  • DMA_CHANNEL0 register bits such as bit#, field name, function, reset value and access are illustrated.
  • Bit 0 corresponds to an MReqSecure qualifier bit. If the MReqSecure bit is set to 0, the DMA channel 0 is a public channel. In some embodiments, the MReqSecure bit can be set to 0 if the access to program the DMA channel 0 is made by a public user access, a public privilege access, a secure user access or a secure privilege access. If the MReqSecure bit is set to 1, the DMA channel 0 is a secure channel. In some embodiments, the MReqSecure bit can only be set to 1 if the access to program the DMA channel 0 is made by a secure user access or a secure privilege access. If a public user access US2006/062277
  • Bit 1 corresponds to a MReqPrivilege bit (or "privilege" bit). If the MReqPrivilege bit is set to 0, the DMA channel 0 is a public user channel. In some embodiments, the MReqPrivilege bit can be set to 0 if the access to program the DMA channel 0 is made by a public user access, a public privilege access, a secure user access or a secure privilege access. If the MReqPrivilege bit is set to 1, the DMA channel 0 is a privilege channel.
  • privilege channels include “supervisor” channels, a “system” channels, an “interrupt request” (IRQ) channels, “fast interrupt request” (FIQ) channels, “abort” channels, "undefined” channels or “monitor” channels.
  • IRQ interrupt request
  • FIQ fast interrupt request
  • a privilege channel enables operations that are not available to public user channels.
  • both the MReqPrivilege and MReqSecure bits are used.
  • these bits allow the DMA channel 0 to be configurable as a public user channel, a public privilege channel, a secure user channel or a secure privilege channel. For example, if both the MReqSecure and MReqPrivilege bits are set to 0, the DMA channel 0 is a public user channel. If the MReqSecure bit is set to 0 and the MReqPrivilege bit is set to 1, the DMA channel 0 is a public privilege channel. If the MReqSecure bit is set to 1 and the MReqPrivilege bit is set to 0, the DMA channel 0 is a secure user channel.
  • both the MReqSecure and MReqPrivilege bits are set to 1, the DMA channel 0 is a secure privilege channel.
  • both the MReqSecure and MReqPrivilege bits can only be set to 1 (simultaneously) if the access to program the DMA channel 0 is made by a secure privilege access.
  • Bit 2 corresponds to a MReqType qualifier bit. This qualifier bit can be used together with the MReqSecure and MReqPrivilege bits. If the MReqType bit is set to 0, the DMA channel 0 is a data access channel, intended for transferring data to a non- executable memory space (e.g., a peripheral or a memory data buffer) by an initiator. In some embodiments, the MReqType bit can be set to 0 for use with a public user access, a public privilege access, a secure user access or a secure privilege access. If the MReqType bit is set to 1, the DMA channel 0 is an instruction channel, intended for transferring data to an executable memory space by an initiator.
  • the DMA channel 0 may be a public user instruction channel, a public privilege instruction channel, a secure user instruction channel or a secure privilege instruction channel.
  • the MReqType qualifier is not used to Configure DMA channels, but is provided during DMA transactions to distinguish between data that is intended to be stored in non-executable memory space and data that is intended to be stored in executable memory space.
  • DMA channel 0 can be set as a public user instruction channel only if the access to program the DMA channel 0 is made by a public privilege access, a secure user access or a secure privilege access.
  • the DMA channel 0 can be set as a public privilege instruction channel only if the access to program the DMA channel 0 is made by a secure user access or a secure privilege access.
  • the DMA channel 0 can be set as a secure user instruction channel only if the access to program the DMA channel 0 is made by a secure privilege access.
  • the DMA channel 0 can be set as a secure privilege instruction channel only if the access to program the DMA channel 0 is made by a secure privilege access.
  • an access attempts to use to a DMA channel improperly e.g., if a secure user access attempts to use the DMA channel 0 as secure user instruction channel
  • the action is discarded or is otherwise nullified.
  • using the DMA channel 0 as an instruction channel requires a higher security level than using the DMA channel 0 as a data access channel. For example, a secure user 2006/062277
  • DMA channel 0 is able to use the DMA channel 0 as a secure user channel (for data access), but is not able to use the DMA channel 0 as a secure instruction channel (i.e., only a secure privilege access is able to use the DMA channel as a secure user instruction channel).
  • DMA parameters such as source address, destination address or other parameters.
  • the DMA subsystem 122 uses (e.g., generates as necessary) the qualifiers set in the channel rights register 130 to issue transactions on the hardware security architecture.
  • the lock bit should be set to 1 throughout the DMA channel operation to ensure that changes are not made to DMA channel's configuration or access rights during the DMA channel operation.
  • the DMA channel configuration registers 128 and DMA channel rights registers 130 related to the completed DMA channel operation are cleared (set to 0). As shown, bits 5-31 of the DMA_CHANNEL0 register are reserved for future use.
  • FIGS. 4-9 show methods of restricting DMA channel configurations in accordance with one or more embodiments.
  • a method 400 comprises accessing a system DMA (block 402). If the access is determined to be a public access (determination block 404), the method 400 allows a DMA channel to be configured as a public channel, but not a secure channel (block 408). If the access is determined to be a secure access (determination block 404), the method 400 allows a DMA channel to be configured as either a secure channel or a public channel (block 406).
  • a method 500 comprises accessing a system DMA (block 502). If the access is determined to be a user access (determination block 504), the method 500 allows a DMA channel to be configured as a user channel, but not a privilege channel (block 508). For example, the user access may be a public user access or a secure user access. If the access is determined to be a privilege access (determination block 504), the method 500 allows a DMA channel to be configured as either a privilege channel or a user channel (block 506). For example, if the access is a public privilege access, the method 500 allows a DMA channel to be configured as either a public privilege channel or a public user channel. If the access is a secure privilege access, the method 500 allows a DMA channel to be configured as either a secure privilege channel, a public privilege channel, a secure user channel or a public user channel.
  • a method 600 comprises accessing a system DMA (block 602). If the access is determined to be a debug access (determination block 604), the method 600 allows a DMA channel to be configured as a debug channel, but not a functional channel (block 608). If the access is determined to be a functional access (determination block 604), the method 600 allows a DMA channel to be configured as either a functional channel or a debug channel (block 606).
  • a method 700 comprises accessing a system DMA (block 702). If the access includes a qualifier for data accesses (determination block 704), the method 700 allows a DMA channel to be used as a data channel, but not an instruction channel (block 708). If the access includes a qualifier for instruction accesses (determination block 704), the method 700 allows a DMA channel to be used as either a data channel or an instruction channel (block 706).
  • a method 800 comprises accessing a system DMA (block 802). If an access is determined to be a public privilege access (determination block 804), the method 800 allows a DMA channel to be configured as a public user channel or a public privilege channel (block 806). If an access is determined to be a secure user access (determination block 808), the method 800 allows a DMA channel to be configured as a public user channel, public privilege channel or a secure user channel (block 810). If an access is determined to be a secure privilege access (determination block 812), the method 800 allows a DMA channel to be configured as a public user channel, a public privilege channel, a secure user channel or a secure privilege channel (block 814). If an access is determined to be neither a public privilege access, a secure user access, or a secure privilege access (determination blocks 804, 808, 812), the method 800 allows a DMA channel to be configured as a public user channel (block 816).
  • a method 900 comprises accessing a system DMA (block 902). If an access is determined to be a public privilege access (determination block 904), the method 900 allows a DMA channel to be used as a public user instruction channel (block 906). If an access is determined to be a secure user access (determination block 908), the method 900 allows a DMA channel to be used as a public user instruction channel or a public privilege instruction channel (block 910). If an access is determined to be a secure privilege access (determination block 912), the method 900 allows a DMA channel to be used as a public user instruction channel, a public privilege instruction channel, a secure user instruction channel or a secure privilege instruction channel (block 914). If an access is determined to be neither a public privilege access, a secure user access, or a secure privilege access (determination blocks 904, 908, 912), the method 900 does not allow a DMA channel to be used as an instruction channel (block 916).
  • the above discussion is meant to be illustrative of the principles and various embodiments of the invention. Numerous variations and modifications will become apparent to those skilled in the art, once the above disclosure is fully appreciated.
  • the locking mechanism may restrict configuration of a DMA channel or restrict changes to a DMA channel after a valid configuration occurs. It is intended that the claimed invention be interpreted to embrace all such variations and modifications.

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Abstract

L'invention concerne un système (100) comprenant un processeur et un sous-système d'accès direct en mémoire (DMA) (122) couplé au processeur. Le système comprend en outre un composant couplé au sous-système DMA par l'intermédiaire d'une interconnexion faisant appel à des règles de sécurité. Si le composant demande un canal DMA (134), le sous-système DMA restreint l'utilisation du canal DMA sur la base de ces règles de sécurité.
EP06846672A 2005-12-23 2006-12-19 Procédés et systèmes destinés à restreindre l'utilisation d'un canal dma Withdrawn EP1971925A4 (fr)

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EP05927886 2005-12-23
US11/557,298 US9740887B2 (en) 2005-12-23 2006-11-07 Methods and systems to restrict usage of a DMA channel
EP06846672A EP1971925A4 (fr) 2005-12-23 2006-12-19 Procédés et systèmes destinés à restreindre l'utilisation d'un canal dma
PCT/US2006/062277 WO2007076340A2 (fr) 2005-12-23 2006-12-19 Procédés et systèmes destinés à restreindre l'utilisation d'un canal dma

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Citations (6)

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