EP1967581B1 - CMOS-kompatibles Verfahren zum Herstellen von Mikronadelstrukturen - Google Patents

CMOS-kompatibles Verfahren zum Herstellen von Mikronadelstrukturen Download PDF

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Publication number
EP1967581B1
EP1967581B1 EP08075154.8A EP08075154A EP1967581B1 EP 1967581 B1 EP1967581 B1 EP 1967581B1 EP 08075154 A EP08075154 A EP 08075154A EP 1967581 B1 EP1967581 B1 EP 1967581B1
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EP
European Patent Office
Prior art keywords
microneedles
insulating layer
microneedle
layer
channel
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EP08075154.8A
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English (en)
French (fr)
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EP1967581A1 (de
Inventor
Roeland Huys
Carmen Bartic
Josine Loo
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Katholieke Universiteit Leuven
Interuniversitair Microelektronica Centrum vzw IMEC
Original Assignee
Katholieke Universiteit Leuven
Interuniversitair Microelektronica Centrum vzw IMEC
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/061—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using biological neurons, e.g. biological neurons connected to an integrated circuit
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N33/00—Investigating or analysing materials by specific methods not covered by groups G01N1/00 - G01N31/00
    • G01N33/48—Biological material, e.g. blood, urine; Haemocytometers
    • G01N33/483—Physical analysis of biological material
    • G01N33/487—Physical analysis of biological material of liquid biological material
    • G01N33/48707—Physical analysis of biological material of liquid biological material by electrical means
    • G01N33/48728—Investigating individual cells, e.g. by patch clamp, voltage clamp
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61M—DEVICES FOR INTRODUCING MEDIA INTO, OR ONTO, THE BODY; DEVICES FOR TRANSDUCING BODY MEDIA OR FOR TAKING MEDIA FROM THE BODY; DEVICES FOR PRODUCING OR ENDING SLEEP OR STUPOR
    • A61M37/00—Other apparatus for introducing media into the body; Percutany, i.e. introducing medicines into the body by diffusion through the skin
    • A61M37/0015—Other apparatus for introducing media into the body; Percutany, i.e. introducing medicines into the body by diffusion through the skin by using microneedles
    • A61M2037/0053—Methods for producing microneedles
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61M—DEVICES FOR INTRODUCING MEDIA INTO, OR ONTO, THE BODY; DEVICES FOR TRANSDUCING BODY MEDIA OR FOR TAKING MEDIA FROM THE BODY; DEVICES FOR PRODUCING OR ENDING SLEEP OR STUPOR
    • A61M37/00—Other apparatus for introducing media into the body; Percutany, i.e. introducing medicines into the body by diffusion through the skin
    • A61M37/0015—Other apparatus for introducing media into the body; Percutany, i.e. introducing medicines into the body by diffusion through the skin by using microneedles

Definitions

  • the invention relates to electronic devices for sensing and/or actuating comprising at least one microneedle and to a method for making such electronic devices.
  • Sensors comprising micro-electrode arrays are used fof measuring electrical activity in small networks of neurons. These sensors are often relatively big and only small matrices or arrays of micro-electrodes can be made.
  • Current state-of-the art micro-electrode arrays may contain a maximum of 64 electrodes with a minimal spacing of 100 ⁇ m between neighbouring electrodes.
  • the electrodes are often made of flat TiN pads with a diameter of maximum 10 ⁇ m. For some applications smaller spacings, e.g. ⁇ 10 ⁇ m, and a larger number of electrodes, e.g. >60000, may be required.
  • On-chip single cell recording of electrical activity using field-effect transistors has been demonstrated for large neurons or tissue slices (see P. Bergveld et al., IEEE Transactions on Biomedical Engineering, 1976 ; P. Fromherz et al., Science, may 1991 ; A. Cohen et al, Biosensors and Electronics, January 2004 ).
  • mammalian neurons e.g. hippocampal neurons
  • the cells are much smaller, which leads to a less efficient electrical coupling.
  • the cells need to be tightly attached onto the chip surface and make a reliable electrical contact between the cell membrane and the recording device.
  • EP-0803702 a microneedle apparatus is described whereby a probe arm with a microneedle is cantilevered over an electronic circuit. In this case only one microneedle is attached to the electronic circuit. Fixing of the probe arm on the electronic circuit is not straightforward because assembly of micro-fabricated parts is not easy.
  • an IC processed microneedle including an interface region and a shaft.
  • a shell defines an enclosed channel to form a shaft.
  • the shaft has ports to permit fluid movement therethrough.
  • KAWANO T. et al "Three-dimensional multichannel Si microprobe electrode array chip for analysis of the nervous system", ELECTRON DEVICES MEETING, 2004. IEDM TECHNICAL DIGEST; IEEE INTERNATIONAL SAN FRANCISCO, CA, USA DEC. 13-15, 2004, PISCATAWAY, NJ, USA, 13 December 2004, pages 1013-1016 , a sensor chip device is reported including a needle-like penetrating microprobe electrode array for simultaneous analysis of neurons in tissue.
  • KAWANO T. et al "Neuron size Si probe array fabricated on integrated circuits for multichannel electrode", TRANSDUCERS, SOLID-STATE SENSORS, ACTUATORS AND MICROSYSYTEMS, 12TH INTERNATIONAL CONFERENCE ON, 2003, PISCATAWAY, NJ, USA, IEEE, vol.2, 9 June 2003, pages 1679-1682 , a technique is presented for multichannel electrode of penetrating Si microprobe array with on-chip integrated circuits (ICs) for use in neuroscience and biomedical engineering.
  • ICs integrated circuits
  • MCALLISTER D V et a "Microfabricated microneedles for gene and drug delivery", ANNUAL REVIEW OF BIOMEDICAL ENGINEERING, ANNUAL REVIEW INC., PALO ALTO, CA, US, vol.2, 1 January 2000, pages 289-313 , microfabricated microneedles for gene and drug delivery are disclosed.
  • a device for the transport of fluids through a biological barrier which includes a number of microneedles projecting from the front face of a substrate.
  • an array of micro-needles is created by forming an array pattern on the upper surface of a silicon wafer and etching through openings in the pattern to define micro-needle sized cavities having a desired depth.
  • the method according to embodiments of the invention is CMOS compatible.
  • the device may comprise different types of microneedles on one substrate.
  • microneedles in the electronic device may be combined with integrated circuitry and/or microfluidic channels in the substrate on which the device is formed, as well as with extra sensing devices on top of the microneedles.
  • an electronic device for sensing and/or actuating comprises at least one microneedle on a substrate, each of the microneedles comprising at least one channel surrounded by an insulating layer.
  • An advantage of the electronic device is the fact that the devices can be made by CMOS processing which allows the combination with CMOS devices in the substrate and devices for sensing and/or actuation purposes on top of the microneedles.
  • An electronic device makes it possible to be used with small cells, such as neurons.
  • microneedle is meant, when the substrate is lying in a plane, a structure oriented substantially perpendicular to the plane of the substrate and having a width between 50 nm and 10 ⁇ m, for example between 100 nm and 6 ⁇ m and a height of between 150 nm and 50 ⁇ m.
  • the present disclosure provides an electronic device for sensing and/or actuating, the electronic device comprising at least one microneedle on a substrate, each of the microneedles comprising at least one channel surrounded by an insulating layer, wherein at least one of the microneedles comprises a channel that is at least partly filled.
  • At least one of the microneedles may comprise at least one channel that is filled with a filling material.
  • At least one of the microneedles may comprise at least one channel that is hollow, or in other words, which is not filled.
  • At least one of the microneedles may comprise at least one channel that is at least partly filled with a filling material.
  • the electronic device When being filled with e.g. a conductive material, preferably a metal, the electronic device can be used for electrical stimulation.
  • the conductive material can also be used for read-out purposes or for activating active devices on top of the microneedles.
  • drugs or chemicals for stimulation can be applied through the hollow or empty channel.
  • the filling material may a conductive material selected from the group consisting of Cu, Al, and W.
  • the electronic device may furthermore comprise at least one active or passive element on top of the at least one microneedle.
  • At least one active or passive element on top of the at least one microneedle may comprise a chip or electronic circuitry.
  • the insulating layer may have a thickness of between 50 nm and 1000 nm.
  • the at least one microneedle may have a diameter between 100 nm and 6 ⁇ m and a height between 150 nm and 50 ⁇ m and an aspect ratio between 0.5 and 10.
  • the at least one microneedle may have a diameter between 100 nm and 6 ⁇ m and a height between 150 nm and 50 ⁇ m and an aspect ratio between 0.5 and 10.
  • the electronic device may furthermore comprise a further insulating layer covering at least part of the substrate in between the microneedles.
  • the insulating layer and/or the further insulating layer may comprise at least one material being an electrically insulating layer or a diffusion barrier layer.
  • the insulating layer and/or the further insulating layer may comprise at least one material selected from the group consisting of SiO 2 , SiC or SiN.
  • the electronic device may furthermore comprise electronic circuitry in the substrate.
  • the electronic device may furthermore comprise at least one microfluidic channel in the substrate.
  • the invention provides a method for manufacturing an electronic device for sensing and/or actuating.
  • the method comprises providing on a substrate at least one microneedle comprising at least one channel surrounded by an insulating layer.
  • Providing at least one microneedle may be performed by using CMOS process technology.
  • CMOS processing allows the combination with CMOS devices in the substrate and devices for sensing and/or actuation purposes on top of the microneedles.
  • CMOS processing also allows making small size needles making it possible to contact small cells, such as neurons.
  • CMOS processing allows to make arrays of needles (at once, as easy as making one needle on its own, as the same processing steps are used), such that always one needle is correctly placed to contact for example a neuron on the correct contacting location for measurement and/or stimulation (with drugs or electrically).
  • Providing at least one microneedle may comprise:
  • Providing at least one microneedle may furthermore comprises at least partly filling at least one of the at least one hole with a filling material.
  • providing at least one microneedle may comprise:
  • the method may furthermore comprise removing at least one of the studs of filling material.
  • the method may furthermore comprise providing at least one active or passive element on top of at least one microneedle.
  • Providing at least one active or passive element on top of at least one microneedle may be performed by providing a layer of material, a chip, or electronic circuitry on top of the at least one microneedle.
  • the method may furthermore comprise fabricating electronic circuitry in the substrate.
  • Fabricating electronic circuitry may be performed by using CMOS process technology.
  • the method may furthermore comprise fabricating at least one microfluidic channel in the substrate.
  • the present invention provides an electronic device formed by the method according to embodiments of the invention.
  • top, bottom, over, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. The terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein can operate in other orientations than described or illustrated herein.
  • actuators and sensors may be integrated with dimensions comparable to the size of biologic cells, for example neurons, or comparable to the size of parts of the cells, for example cell organelles or mitochondria. Therefore sensors need to be scaled to a size that approaches the dimensions of one cell or a region-of-interest of this cell. This can be done with for example microneedles.
  • CMOS-compatible methods to fabricate microneedle structures with sub-micron dimensions can be developed.
  • CMOS compatible processing for fabricating the sensors reduces the risk of problems with the underlying circuitry such as contamination or the use of too high temperatures.
  • the use of lithography and DRIE-etch techniques to create the microneedles facilitates the reproducibility of the shape of the sensors. That way matrices of microneedles with sub-micron dimensions or bigger can be produced on top of an integrated circuit, e.g. on top of a chip surface using CMOS-compatible processes.
  • microneedles or nails which may be arranged on a substrate randomly or in an array, on top of an integrated circuit, the microneedles having a shaft and isolated electric conductors and/or micro-fluidic channels inside the shaft.
  • active or passive sensors can be made on top of the nails. Also a method to produce these nails on top of a substrate is presented.
  • the proposed technology enables the creation of 3D-topologies with several kinds of materials, or combinations of materials, like metals, oxides, nitrides, carbides, polymers, organic materials, chemical reactive components, catalysts, biomolecules, enzymes, and other materials used in the field of micromachining or micro-electro-mechanical systems (MEMS).
  • MEMS micro-electro-mechanical systems
  • the 3D-topology increases the surface area, which can be advantageous in many applications where a high surface in a miniaturized scale is required.
  • By using high-density lithography different electrodes or 3D structures separated from each other with a minimal distance can be created, which can be used in many applications where a small distance between contacts is required, e.g.
  • This technology can be used in following applications, but is not limited thereto: integrated 3D-capacitors, 3D inter-digitated sensor electrodes, batteries, small-scale fuel cells, microreactors, catalysts systems, small-scaled thermopiles, small-scale heat exchangers, solar cells.
  • the present disclosure provides an electronic device for sensing and/or actuating.
  • the electronic device comprises at least one microneedle on a substrate lying in a plane, each of the microneedles comprising at least one channel surrounded by an insulating layer, also referred to as "shaft", the channel having a longitudinal axis which is directed in a direction substantially perpendicular to the plane of the substrate.
  • the shaft is the material surrounding the at least one channel, formed by the insulating material.
  • microneedle is meant a structure which is oriented in a direction substantially perpendicular to the plane of the substrate and which has a width between 50 nm and 10 ⁇ m, for example between 100 nm and 6 ⁇ m and a height of between 150 nm and 50 ⁇ m.
  • the microneedles may have a total width or diameter of between 50 nm and 10 ⁇ m, or between 100 nm and 6 ⁇ m, for example between 150 nm and 5 ⁇ m, or between 500 nm and 2 ⁇ m or between 500 nm and 1500 nm, and a height of between 150 nm and 50 ⁇ m, for example between 500 nm and 1500 nm.
  • the lower boundary of dimensions may be determined by limitations of known processes available to form such microneedles.
  • the device and method according to embodiments is CMOS compatible.
  • the device may comprise different types of microneedles on one substrate.
  • the microneedles in the electronic device according to embodiments of the invention may be combined with integrated circuitry and/or microfluidic channels in the substrate on which the device is formed, as well as with extra sensing devices on top of the microneedles.
  • Embodiments of the present invention enable integration of sensors with readout electronics and data processing on a large scale. Also cell stimulation sites can be integrated, e.g. electrical stimulation or controlled release of chemicals through micro-fluidic channels.
  • Figure 1 and Figure 3 to Figure 5 show cross-sections and Figure 2 shows a three-dimensional view of implementations of electronic devices according to embodiments.
  • the electronic device comprises three microneedles 10, also referred to as nails, on top of a substrate 1, while in Figure 5 the electronic device comprises one microneedle 10.
  • Microneedles may be provided separately or in groups. When in groups, they may be provided in a regular or in irregular array. When providing arrays of microneedles, always one microneedle may correctly be placed to contact for example a neuron on the correct contacting location for measurement and/or stimulation (with drugs or electrically).
  • microneedles and nails may be used next to each other and are meant to indicate the same entities, i.e. a vertical structure on a substrate or in other words, when the substrate 1 is lying in a plane, a structure having a longitudinal axis oriented in a direction substantially perpendicular to the plane of the substrate 1.
  • the term "substrate” may include any underlying material or materials that may be used, or upon which a device, a circuit or an epitaxial layer may be formed.
  • this "substrate” may include a semiconductor substrate such as e.g. a doped silicon, a gallium arsenide (GaAs), a gallium arsenide phosphide (GaAsP), an indium phosphide (InP), a germanium (Ge), or a silicon germanium (SiGe) substrate.
  • a semiconductor substrate such as e.g. a doped silicon, a gallium arsenide (GaAs), a gallium arsenide phosphide (GaAsP), an indium phosphide (InP), a germanium (Ge), or a silicon germanium (SiGe) substrate.
  • the "substrate” may include for example, an insulating layer such as a SiO 2 , a Si 3 N 4 or a sapphire layer in addition to a semiconductor substrate portion.
  • the term substrate also includes silicon-on-glass, silicon-on sapphire substrates.
  • the term “substrate” is thus used to define generally the elements for layers that underlie a layer or portions of interest.
  • the "substrate” may be any other base on which a layer is formed, for example a glass or metal layer.
  • the substrate may optionally be planarised. This may be done by for example depositing a planarisation layer of a photoresist, which may for example be an epoxy- or novolac-based polymer, onto the substrate.
  • the substrate 1 may be silicon or sapphire.
  • the substrate 1 may comprise electronic circuitry 2 and/or microfluidic channels 3.
  • electronic circuitry 2 can be included in the substrate 1.
  • Other functionality of the electronic circuitry 2 located below the microneedles 10 may be, but is not limited to, matrix addressing circuitry, electrical biasing of electrodes optionally present on top of the microneedle, applying stimulation signals, amplifying recorded signals, transporting data outside the matrix or analog-to-digital conversion.
  • the electronic circuitry 2 in the substrate 1 may be formed by CMOS technology.
  • the electronic circuitry can be made starting from a CMOS integrated circuit, for example 0.35 micron technology, 0.25 micron technology, 0.18 micron technology. Also smaller or larger technologies can be used. This may include CMOS front end of line with transistors, contacts and metal layers in the backend of line. Wiring of the circuitry is typically done in the backend of line. For backend metallization for example Al, W, and/or Cu are used. But any other metal known in the art can be used.
  • the microneedles 10 may be used for sensing and/or actuating purposes. According to embodiments, the microneedles 10 may be arranged randomly on the substrate 1. According to other embodiments, the microneedles 10 may be arranged in a matrix comprising rows and columns. The microneedles 10 can thus be located in random patterns or in matrices, with a minimal distance between the microneedles 10 of between 10 nm and 1 ⁇ m, depending on the technology used. In fact, there is no limit on the maximum distance between the microneedles 10, nor on the way the microneedles 10 are patterned.
  • the substrate 1 may comprise a microfluidic channel 3 which extends up to a hollow channel 8 of at least one microneedle 10 (see further).
  • the microneedles 10 comprise an insulating layer 6, also called shaft, surrounding at least one channel 8, also referred to as cavity 8, or in other words, the microneedles 10 comprise at least one channel 8 surrounded by an insulating layer 6.
  • the diameter d ch of the channel or cavity 8 of the microneedle 10 may vary between 50 nm and 5 ⁇ m, for example between 500 nm and 1000 nm.
  • the insulating layer 6 may be adapted to have the function of an electrically insulating layer, (for example SiO, SiN, SiC, and other electrically insulating materials known by a person skilled in the art) or a thermally insulating layer.
  • an electrically insulating layer for example SiO, SiN, SiC, and other electrically insulating materials known by a person skilled in the art
  • a thermally insulating layer for example SiO, SiN, SiC, and other electrically insulating materials known by a person skilled in the art
  • the insulating layer 6 may be adapted to have the function of a diffusion barrier for preventing diffusion of material from the inner side of the microneedle 10 through the insulating layer 6 or from outside the microneedle to the inner side of the microneedle or both.
  • the insulating layer 6 may prevent the liquid to diffuse from outside the microneedle 10 towards the channel 8 of the microneedle 10.
  • the insulating layer 6 may furthermore reduce parasitic capacitance of the electronic device and may, in case of a channel filled with conductive material, improve insulation of the filled channel.
  • SiC or SiN may be used as a diffusion barrier.
  • the insulating layer 6 may have a thickness of between 50 nm and 1000 nm, for example between 100 nm and 200 nm.
  • the insulating layer 6 may, for example, comprise silicon oxide (SiO 2 ), silicon carbide (SiC), silicon nitride (SiN), a polymer such as e.g. polymide, PTFE (poly(tetrafluoroehtylene)), parylene, or any other suitable material that can be used for electrical insulation and/or as a diffusion barrier.
  • the electronic device may comprise at least one microneedle 10 comprising a channel 8 which is hollow, i.e. a channel 8 which is not filled with any solid material.
  • the hollow channel 8 may extend to a microfluidic channel 3 present in the substrate 1 (see Figure 1 , 3 and 4 ).
  • the electronic device may comprise at least one microneedle 10 comprising a channel 8 which is completely filled with a material, also called "filling material", for example with a conductive material, such as for example doped Si, SiGe, Al, Au, Pt or Cu.
  • the channel 8 may be filled with a biogel, e.g. enzymatic gel, or with a piezoelectric material or a nanostructure e.g. a nanowire, may be provided in the channel 8.
  • the electronic device may comprise at least one microneedle 10 comprising a channel 8 which is partly filled with a material, for example with a conductive material.
  • the channel 8 being partly filled can be implemented in two ways. One way may be in case that the microneedle 10 comprises one channel 8. In that case, the channel 8 may be partly filled, i.e. may be filled for e.g. 1/2 or 1/3 or 2/3 of the height of the channel 8, see for example Figure 3 where the left microneedle 10 is partly filled with a material, e.g. a conductive material.
  • a second way to implement a partly filled channel 8 is in case the microneedle 10 comprises a plurality of channels 8, and some of the plurality of channels 8 are filled with a material, e.g. conductive material and some of the plurality of channels 8 are hollow, i.e. are not filled, see for example Figure 4 where the left microneedle 10 comprises three filled channels 7 and two hollow channels 8.
  • any combination of any number of microneedles comprising a hollow channel 8, microneedles 8 comprising a filled channel and microneedles comprising a plurality of filled channels 7 and hollow channels 8 is disclosed.
  • the electronic device may comprise a combination of microneedles 10 comprising a completely filled channel 7 and microneedles 10 comprising a hollow channel 8 (see Figure 1 and Figure 2 ).
  • Another example may be an electronic device comprising a combination of microneedles 10 comprising a completely filled channel 7, microneedles 10 comprising a hollow channel 8 and microneedles 10 comprising a channel 8 which is partly filled, e.g. filled for 1/2 of its height (see Figure 3 ).
  • Still another example may be an electronic device comprising a combination of microneedles 10 comprising a completely filled channel 7, microneedles 10 comprising a hollow channel 8 and microneedles 10 comprising a combination of filled channels 7 and hollow channels 8 (see Figure 4 ).
  • the microneedles 10 may have an aspect ratio of between 0.5 and 10, for example between 1 and 10, the aspect ratio of a microneedle 10 being defined by the height h of the microneedle 10 divided by its diameter d (see Figure 1 ).
  • the diameter d of the microneedle 10 is defined by the outer diameter of the insulating layer as is indicated in Figure 1 .
  • the height h of the microneedles 10 may vary between 150 nm and 50 ⁇ m, for example between 500 nm and 1500 nm.
  • the channel 8 may partly be filled with a conductive material, thereby forming a conducting wire 7 in the channel.
  • the conducting wire 7 may serve for providing electrical contact from the electric circuitry 2 in the substrate 1 through the microneedles 10 towards the outside world, e.g. to external electric circuitry, for, for example, providing electrical stimulation and/or sensing functions to the electronic device.
  • the bottom of the conducting wire 7 makes electrical contact to the electric circuitry 2.
  • the conducting wire 7 may, for example, contact bond pads or other areas of the top metal level of the CMOS backend, but is can also contact areas in other metal levels in the CMOS backend. Typically the top metal of the backend of line is used for contacting the bottom of the microneedles.
  • the metal layers of the CMOS backend form the interconnection between the electronics and the microneedles 10 that can be used as a sensor.
  • the top of the conducting wires 7 can be used for sensing and/or actuation.
  • the conducting wires 7 may also be referred to as sensors.
  • the conducting wires 7 may comprise any suitable conductive material that can be used for contacting the electric circuitry 2 in the substrate 1 and which can then serve as a sensor.
  • CMOS technology for compatibility with CMOS technology for example Cu, Al or W may be used, but any other conductive material that is compatible with respect to temperature budget and/or contamination with CMOS technology may, according to embodiments of the present invention, be used for the conducting wires 7.
  • Other conductive materials that may be used for the conducting wires 7 may be metals such as e.g. Pt, Au, Al, Cu, Ag, doped Si or SiGe.
  • the microneedles 10 may have different shapes (see Figure 6 and Figure 7 ).
  • Figure 6 shows examples of microneedles 10 with different shapes according to embodiments of the invention as seen from the top of the microneedle 10, i.e. from that side of the microneedle 10 opposite to the side that is attached to the substrate 1.
  • a top surface of the microneedle 10 may be circular, oval, square, rectangular, star-shaped, triangular, or may have any other suitable shape.
  • Figure 7 shows examples of microneedles 10 with different shapes on the substrate 1 of the electronic device. The shape and/or dimensions of the microneedles at their top may be different from the shape and/or dimensions of the microneedles at the substrate.
  • microneedles 10 comprising an insulating layer 6 surrounding a channel 7 that is filled with a material, e.g. conductive material. It has to be understood that the shapes illustrated in Figure 6 and figure 7 also apply to microneedles 10 comprising an insulating layer 6 surrounding a hollow channel 8, i.e. a channel that is not filled or to microneedles 10 comprising an insulating layer 6 surrounding a channel 8 that is partly filled with a material, e.g. conductive material, as was described above.
  • a material e.g. conductive material
  • An inner and/or an outer side of the insulating layer 6 may be straight, curved, or may have any other suitable shape.
  • the inner and outer side of the insulating layer 6 may make an angle with each other.
  • the shape of the inner and outer side of the second insulating layer 6 may, but does not have to be the same.
  • the shape of the inner and the outer side of the insulating layer 6 may be chosen such that the insulating layer 6 surrounds the channel 8 such that conduction through the conducting wire 7 or fluid transport through the hollow channel is guaranteed.
  • a further insulating layer 5 may be present which at least partly covers the substrate 1.
  • This further insulating layer 5 may be used for electrically insulating and/or protecting the underlying electronic circuitry 2 during further processing of the electronic device.
  • the further insulating layer 5 may be adapted to have the function of an electrically insulating layer. Electrically insulating layers may, for example, be SiO 2 , SiN, SiC, and other materials used in the field.
  • the further insulating layer 5 may be adapted to have the function of a diffusion barrier for preventing diffusion of material from the substrate 1 to the outside world or from the outside world to the substrate 1 or both.
  • a diffusion barrier for example for Cu can be SiN or SiC.
  • the further insulating layer 5 may cover only part of the substrate 1.
  • the further insulating layer 5 may cover at least the electronic circuitry present in the substrate 1, but it can also cover the whole substrate 1 in between the microneedles 10.
  • the thickness of the further insulating layer 5 may be between 50 nm and 1000 nm, for example between 300 m and 700 nm or between 400 nm and 600 nm. It has to be noted that this further insulating layer 5 is optional and does, for particular applications, not have to be present.
  • a further insulating layer 5 may not be required.
  • electronic circuitry is present in the substrate 1 but if the device is used in air or vacuum, which is by itself sufficiently insulating, there is also no need for an additional insulating layer 5.
  • non-electrically isolating environments e.g. liquids, plasmas, ionized gasses
  • there is a need for an additional insulating layer there is a need for an additional insulating layer.
  • the use of the device in corrosive environments, environments with a high temperature, etc.. also requires the presence of a further insulating layer 5.
  • the further insulating layer 5 may, for example, comprise silicon oxide (SiO 2 ), silicon carbide (SiC), silicon nitride (SiN), a polymer e.g. polyimide, PTFE, Parylene, or any other suitable material that can be used for electrical isolation and/or as a diffusion barrier.
  • the further insulating layer 5 may be made of one material or may be made of different materials, for example of different layers (see Figure 5 ). Different layers can be used for example for adhesion purposes, as a barrier layer against diffusion of materials from the microneedles 10 towards the underlying electronic circuitry 2 in the substrate 1. For example, before other layers are provided for the purpose of forming a further insulating layer 5, a first layer 4 may be provided on a major surface of the substrate 1 to reduce stress of the subsequently provided layers, for preventing material to diffuse from the microneedles 10 towards the underlying electronic circuitry 2 in the substrate 1 or vice versa, or for any other reason that requires a particular layer to be provided on the substrate 1 before other insulating layers are provided.
  • the further insulating layer 5 and the insulating layer 6 surrounding the channel 8 may be made of a same material. According to other embodiments, the further insulating layer 5 and the insulating layer 6 surrounding the channel 8 may be made of a different material.
  • one or more extra layers 9 may be added to the microneedles 10 (see Figure 5 ).
  • one or more of diffusion barriers or layers facilitating the provision, e.g. growth, of the conductive material in the channel 8 can be added in between the insulating material of layer 6 and the conductive material and/or at the bottom of the conducting wire 7.
  • These extra layers 9 may, for example, comprise Ti, TiN, Ta, TaN or any other suitable material known in the field.
  • a method for manufacturing an electronic device for sensing and/or actuating.
  • the method comprises forming at least one microneedle 10 comprising at least one channel 8 surrounded by an insulating layer 6 on a substrate 1 lying in a plane, the channel 8 having a longitudinal axis which extends in a direction substantially perpendicular to the plane of the substrate 1.
  • Forming at least one microneedle 10 may be performed in different ways. Any method known in the art can be used. When using CMOS technology, there are different options, such as damascene processing with metallization, for example Cu metallization, (see Figure 8(a) to 8(f) ) or metal patterning using for example Al metallization (see Figure 9(a) to 9(h) ) for example for making conducting needles. Often higher aspect ratios for the microneedles can be achieved with a damascene process. The two approaches will be described in detail below. It has to be understood that this is not intended to limit the invention in any way and that any other approach known by a person skilled in the art can be used with the method according to embodiments of the invention.
  • CMOS technology allows making very small features with dimensions even in the nm scale, in a reproducible way.
  • an insulating layer 14 is provided, e.g. deposited (see Figure 8(a) ).
  • the insulating layer 14 can be a single layer, such as SiO 2 , SiC, or SiN.
  • the insulating layer 14 can also be a combination of layers.
  • a thin SiC layer with a thickness of between 10 nm and 100 nm may first be provided and may later serve as a Cu diffusion barrier and on top of the SiC layer a thick SiO 2 layer may then be provided.
  • a thin layer facilitating lithography can be provided, e.g. deposited.
  • the thickness of the insulating layer 14 may correspond to the length of the channel 8 of the microneedle or may preferably be a little bit thicker as some material may be removed at the top of the structure during further processing.
  • the insulating layer 14 may have a thickness of between about 10% to 25% larger than the length of the channel 8.
  • the exact thickness of the insulating layer 14 needs to be defined based on the planarising characteristics of the following CMP step and the exact topology of the needles. Hence, strictly spoken the thickness of the insulating layer 14 may be the sum of the length of channel 8 and optionally the amount of material that may be removed during further processing.
  • holes 11 may be provided, e.g. etched, through the insulating layer 14 extending down to the underlying substrate 1.
  • the holes 11 may be provided, e.g. etched down to metal bond pads of electronic circuitry present in the substrate 1 (see Figure 8(b) ).
  • Providing holes 11 in the insulating layer 14 may be performed by any suitable method, e.g. with lithography and dry and/or wet etching, for example deep reactive ion etching (DRIE).
  • DRIE deep reactive ion etching
  • the holes 11 provided in the insulating layer 14 may have different shapes, for example, seen from a top surface the holes may be circular, cylindrical, square, rectangular, star shaped or may have any other suitable shape in cross-section. All kinds of shapes which allow formation of a channel 8 may be used.
  • the holes 11 may have a diameter of between 50 nm and 5 ⁇ m, for example between 500 nm and 1000 nm.
  • the holes 11 may optionally be filled with a filling material 18, e.g. a conductive material such as a metal (see Figure 8(c) ).
  • the conductive material may be Cu or may be any other material that allows filling narrow holes 11.
  • Providing the filling material, e.g. conductive material may be performed with any suitable technique known by a person skilled in the art such as e.g. electroplating, electroless plating, sputtering or chemical vapour deposition.
  • a barrier layer may first be deposited on at least a bottom of the holes 11 (not shown in the figures) in order to facilitate filling of the holes 11 and to, later on during further processing and/or use of the electronic device, act as a diffusion barrier for preventing material to diffuse from outside the microneedle 10 to inside the microneedle 10 and/or vice versa.
  • one or more extra layers may be deposited onto the barrier layer prior to filling the holes 11, for example layers for facilitating filling of the holes 11.
  • the barrier layer may, for example, be combination of Ta/TaN or Ti/TiN.
  • a Cu electroplating seed layer may first be deposited.
  • CMP chemical mechanical polishing
  • microneedles 10 comprising hollow channels 8 are to be formed, or in other words channels which are not filled
  • filling of the holes 11 with a filling material 18 is not necessary.
  • Such channels may, for example, serve as microfluidic channels of the electronic device, according to embodiments of the invention.
  • hollow channels may also be formed by first filling the holes 11 with a material, e.g. conductive material used as sacrificial metal, and then forming the channel 8 by removing the material from the holes 11 in a later phase by, for example, etching (see further). In case electrical connections between the electronic circuitry in the substrate 1 and the outside world, filling of the holes 11 may be done at this stage.
  • the holes 11 may first be filled completely. Next, part of the material the holes 11 are filled with may be removed by, for example, selective etching. According to other embodiments, the holes 11 may just partly be filled with material, e.g. conductive material.
  • the holes 11 may first be completely filled as described above and the material of the channels of the microneedles 10 which need to be hollow may then be removed from the channels (see Figure 8(e) ). Therefore, a lithography step may be used.
  • the lithography step may comprise covering the substrate 1 with a resist except on the locations where the hollow channels or cavities 8 need to be formed and the sacrificial material, e.g. conductive material can be etched away from the holes. These channels can be created by etching away the sacrificial conductor, creating a hollow channel 8.
  • openings in the resist may be provided at locations of the insulating layer 16. Where the insulating layer 16 is not covered with the resist, holes may be etched in the insulating material 16.
  • the technique chosen to form hollow channels 8 may depend on the etching capabilities of the conductive material 17 and/or the insulating material 16.
  • dots of resist may be formed on the top of the structure as illustrated in Figure 8(e) at locations which are not to be removed, i.e. on top of the filled channels and on top of the hollow channels. This may be done by, for example, using lithography.
  • the dots covering the hollow and filled channels may be slightly larger than the diameter of the hollow and filled channels.
  • the extra area of the dots, i.e. the area larger than the diameter of the hollow and filled channels defines the width of the insulating layer 6 surrounding the channels 7, 8.
  • the dots may have a diameter of between 100 nm and 6 ⁇ m or between 600 nm and 1200 nm.
  • the insulating layer 6 surrounding the channels 7, 8 may be etched (for example by DRIE), leaving a thin layer 6 of insulating material of between 50 nm and 1000 nm, for example between 100 nm and 200 nm surrounding the channels 7, 8.
  • the total width or diameter of the microneedles 10 (channels 7, 8 + insulating layer 6) may be between 100 nm and 6 ⁇ m, for example between 600 nm and 1200 nm.
  • an insulating layer 5 with a thickness of between 50 nm and 1000 nm or between 300 nm and 700 nm or between 400 nm and 600 nm remains.
  • the amount of insulating material that is removed in between the microneedles 10 when looking from the top surface defines the length of the microneedles. Thereby voids 12 are created in between the microneedles 10.
  • the amount of material removed in between the microneedles when looking from the top surface, or else the length or height of the microneedles can be between 150 nm and 50 ⁇ m or between 500 nm and 1500 nm.
  • the diameter of these microneedles can vary between 50 nm and 10 ⁇ m, or between 100 nm and 6 ⁇ m, or between 150 nm and 5 ⁇ m, or between 500 nm and 1500 nm.
  • the aspect ratio (height/diameter) can vary between 0.5 and 10.
  • the microneedles 10 may be located in random patterns or in matrices, with a minimal distance in between the microneedles of between 10 nm and 1 ⁇ m, depending on the technology used. In fact there is no limit on the maximum distance between the microneedles 10, nor on the way the microneedles 10 are patterned.
  • Control of the etching of the insulating material can be done when knowing the etch rate of the insulating material 14. In that case, the etch time may depend on the amount of material that needs to be removed. Another way to control the amount of material that is etched in between the microneedles 10 may be by introducing an intermediate etch stop layer in the insulating layer 14.
  • FIG. 9(a) to 9(h) Another approach for making the microneedles 10 is illustrated in Figure 9(a) to 9(h) .
  • This approach uses deposition of a filing material and patterning. This approach may, for example, be used in case of Al, but can also be used for other materials.
  • a substrate 1 which, for example, comprises a CMOS integrated circuit with transistors, contacts and metal layers (not shown in the figures) an insulating material 15 may be deposited and patterned (see respectively Figures 9(a) and 9(b) ).
  • This insulating layer 15 may, for example, be an electrically insulating layer and/or a diffusion barrier.
  • the insulating layer 15 may for example be a low-epsilon dielectric such as SiO 2 , or SiC, or SiN.
  • the insulating layer 15 may, according to embodiments of the invention also comprise a stack comprising different layers.
  • a SiC layer can be included as a diffusion barrier for Cu. This avoids the diffusion of Cu towards underlying transistors of the CMOS integrated circuit.
  • an etch stop layer may be provided, for example SiC when SiO 2 is used as an insulating layer 15.
  • the thickness of the insulating layer 15 may be the thickness that is required for good electrical isolation.
  • the thickness of the insulating layer may be between 50 nm and 1000 nm, for example between 300 nm and 700 nm or between 400 nm and 600 nm.
  • the insulating layer 15 may be patterned so as to provide holes in it. These holes may be used in case of channels 7 filled with a conductive material of the microneedles 10 to be formed need to be able to contact underlying circuitry 2 or in case hollow channels or cavities 5 need to extend to microfluidic channels 3 in the substrate 1. Therefore, the holes need to be provided in the insulating layer 15 at locations where microneedles 10 have to be formed (see Figure 9(b) ). Patterning the insulating layer 15 may be performed by any suitable method, for example, lithography and dry and/or wet etching.
  • a layer 17 of filling material for example a conductive material such as Al, may be provided, e.g. deposited (see Figure 9(c) ).
  • the thickness of the layer 17 of filling material defines the length of the channel 7, 8 of the microneedles 10.
  • the thickness of the layer 17 of filling material may, for example, be between 150 nm and 50 ⁇ m or between 500 nm and 1500 nm.
  • the layer 17 of filling material may be patterned. This may, for example, be performed by using lithography and dry and/or wet etching. After deposition of the filling material 17, a lithography step using a photo-mask may be performed to make patterns of resist, and a dry and/or wet etching step may then be used to etch away the filling material at the location where no microneedles 10 have to be formed. As a consequence studs of filling material, for example conducting studs, at the locations of the microneedles will be realized (see Figure 9(d) ).
  • gaps that are formed in between the studs 17 by patterning the layer 17 of filling material may be filled with an insulating material 16, such as for example SiO 2 , Si 3 N 4 , Ta 2 O 5 , or a polymer (see Figure 9(e) ). Filling the gaps may be done by any method suitable to deposit a material in high aspect-ratio gaps, such as for example high density plasma chemical vapour deposition (HDP CVD), or spin-on-glass.
  • the insulating material 16 may comprise one material or may comprise different materials. Insulating materials 15 and 16 may comprise a same material or may comprise different materials. Insulating materials 15 and 16 may consist of different materials.
  • excess of insulating material 16 may be removed in any suitable way. This may be done by removing a top of the insulating material down to the filling material of the studs 17 in order to be able to contact the microneedles 10 from above, i.e. from their top (see Figure 9(f) ). Removing excess insulating material 16 and in the mean time possibly flattening a top surface of the insulating layer 16, may be done by any suitable method, for example, etching back or chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • microneedles 10 are required with a filled channel 7, no filling material has to be removed. In case, however, at least one microneedle 10 is required with a hollow channel 8, the filling material may be selectively removed by, for example etching. This may be done at this stage (see Figure 9(g) ). Therefore, a lithography step may be used.
  • the lithography may comprise covering the substrate 1 with a resist except on locations where hollow channels or cavities 8 have to be formed. This can be at the location where a stud 17 is present or at locations on the insulating layer 16. Where the insulating layer 16 is not covered with the resist, holes may be etched in the insulating material 16.
  • the filling material may be selectively removed, e.g. etched (see Figure 9(g) ).
  • the technique chosen to form hollow channels 8 may depend on the etching capabilities of the filling material 17 and/or the insulating material 16.
  • dots of resist may be formed on the top of the structure as illustrated in Figure 9(g) at locations which are not to be removed, i.e. on top of the filled channels and on top of the hollow channels. This may be done by any suitable method, for example by using lithography.
  • the dots covering the hollow and filled channels may be slightly larger than the diameter of the hollow and filled channels.
  • the extra area of the dots, i.e. the area larger than the diameter of the hollow and filled channels defines the width of the insulating layer 6 surrounding the channels 7, 8.
  • the dots may have a diameter of between 100 nm and 6 ⁇ m or between 600 nm and 1200 nm.
  • the insulating layer 6 surrounding the channels 7, 8 may be removed, for example by etching (for example by DRIE), leaving a thin layer 6 of insulating material of between 50 nm and 1000 nm, for example between 100 nm and 200 nm surrounding the channels 7, 8.
  • the total width or diameter of the microneedles 10 (channels 7, 8 + insulating layer 6) may be between 100 nm and 6 ⁇ m, for example between 600 nm and 1200 nm.
  • This insulating material 6 forming the sidewalls of the microneedles 10 may, if the channel of the microneedle 10 is filled, seal the filling material inside the microneedle 10 from the outside world, for example from liquids or other materials. In case of a conductive filling material, it also reduces the parasitic capacitance of the electronic device and improves the electrical insulation of the microneedle 10.
  • an insulating layer 5 with a thickness of between 50 nm and 1000 nm or between 300 nm and 700 nm or between 400 nm and 600 nm remains.
  • the amount of insulating material that is removed in between the microneedles 10 when looking from the top surface defines the length of the microneedles.
  • the amount of material removed in between the microneedles when looking from the top surface, or else the length of the microneedles can be between 150 nm and 50 ⁇ m or between 500 nm and 1500 nm. Thereby voids between the microneedles 10 may be created.
  • the microneedles 10 may be located in random patterns or matrices, with a minimal distance between the microneedles 10 of between 10 nm and 1 ⁇ m, depending on the technology used. In fact there is no limit on the maximum distance between the nails, nor on the way the nails are patterned.
  • Control of the etching of the insulating material can be done when knowing the etch rate of the insulating material 15, 16. In that case, the etch time may depend on the amount of material that needs to be removed. Another way to control the amount of material that is etched in between the microneedles 10 may be by introducing an intermediate etch stop layer in the insulating layers 15, 16. Still another option is to select different insulating materials for layers 15 and 16 such that insulating material 15 acts as an etch stop layer for the chemistry that is used for etching insulating material 16.
  • Finishing of the electronic device which may be e.g. a sensor or an actuator, can be done in different ways, depending on the application. Extra components can be added on top of the microneedle 10.
  • Extra components can be added on top of the microneedle 10.
  • some examples will be discussed on how microneedles 10 can be finished. These examples are intended for illustration purposes only and are not intended to limit the invention in any way.
  • the different parts may, even if not mentioned, comprise same materials as described in the embodiments above and may be formed using same techniques as described earlier. Any combination of materials and techniques used and described in the different embodiments above may be combined in order to make electronic devices and microneedles 10 which are described hereinafter.
  • the microneedle 10 may comprise an insulating layer 6 surrounding a filled channel 7.
  • the conductive material of the filled channel 7 may be in contact, e.g. electrical contact with underlying electronic circuitry 2 which is provided in the substrate 1.
  • the conductive material may be in contact with a bonding pad of a top metal level, which may for example comprise Al or Cu, of the backend of line, or in other words with wiring towards the underlying electronic circuitry 2.
  • an additional layer 4 may be present in between insulating layer 5 and the substrate 1. This may, for example, be a diffusion barrier layer.
  • the diffusion barrier layer may, e.g.
  • this additional layer 4 may be an etch stop layer.
  • the etch stop layer may, e.g. in case insulating layer 5 comprise an oxide, for example be SiC.
  • Insulating layer 5 may, as already discussed above, be an electrically insulating layer or a dielectric material to reduce parasitic capacitances between neighbouring filled channels 7, also referred to as conductors, or between the filled channels 7 and the surrounding atmosphere, for example gas or liquid. It also protects and shields the conducting material of the filled channel 7 from surrounding atmosphere, for example gas or liquid.
  • the microneedle 10 illustrated in Figure 10(a) may comprise an extra layer 9 in between the conductive material and the insulating layer 6.
  • This extra layer 9 may, for example have the function of a diffusion barrier for preventing diffusion from outside the microneedle 10 to the inside of the microneedle 10 and/or vice versa or may have the function of facilitating deposition of the conductive material in the channel, depending on the technique used to form the microneedles 10 (see earlier).
  • the extra layer 9 may comprise a combination of TaN and Ta.
  • the electronic device illustrated in Figure 10(a) may be used as a capacitive sensor, a battery or organic optical devices, organic solar cells, chemical sensors, biosensors. Therefore, it may comprise an additional layer 21 on top of the structure.
  • the additional layer 21 may be an insulating layer and may, for example, be formed by deposition of a thin insulating layer with a thickness of between 10 nm and 200 nm at a last stage of the manufacturing process, i.e. after the microneedles 10 have been formed.
  • an insulating layer 21 which may for example comprise 100 nm of Ta 2 O 5 or a thin oxide layer or a high-k dielectric, such as Ta 2 O 5 , HfO 2 , Ti 2 O, SiC, polymers or biomolecules
  • the microneedle 10 may become a passive electrode.
  • the thin insulating layer 21 may form a barrier between the conductive material 7 of the microneedle 10 and the outside world, for example a liquid.
  • the electronic device illustrated in Figure 10(a) may serve as a capacitive sensor.
  • the additional layer 21 may comprise a conductive material or a combination of conductive materials, such as e.g. Au, Pt, Ti, Al, Cu, Zn, and/or C.
  • a conductive material such as e.g. Au, Pt, Ti, Al, Cu, Zn, and/or C.
  • an electronic device comprising microneedles 10 having a channel 7 filled with carbon, covered with a layer 21 of conductive material and brought in contact with a suitable electrolyte can be used as a 3D Li-ion microbattery.
  • the additional layer 21 may comprise a polymer.
  • the additional layer 21 may comprise a semiconductive material.
  • the microneedle 10 may comprise an insulating layer 6 surrounding a filled channel 7.
  • the electronic device illustrated in Figure 10(b) may function as a passive sensor or passive electrode.
  • the microneedle 10 comprises on a top surface a dot 22 of material, e.g. a noble metal or a semiconductor material.
  • the dot 22 may be formed by, for example, depositing the material through a shadow mask or by providing a layer of the material and patterning the material using e.g. lift-off techniques. Also lithography techniques combined with dry and/or wet etching may be used for this purpose.
  • the top surface on which the lithography has to be performed needs to be substantially flat to have sufficient depth of focus for lithography.
  • Provision of the dots 22 may, for example, be performed before final formation of the microneedles 10 by etching the insulating material as was illustrated in Figure 8(d) or 8(e) or Figure 9(f) or 9(g) depending on the technique used to form the microneedles 10.
  • the dots 22 may comprise a noble metal such as, for example, Au or Pt.
  • Au may, for example, be deposited by electroplating or electroless (chemical) plating.
  • Pt may, for example, be deposited by electroless (chemical) plating.
  • the dot 22 can be used as an electrical sensor or stimulator for measuring activity of, or stimulating electrically active cells, such as e.g. neurons.
  • the dots 22 may comprise a semiconductor material.
  • the dots 22 may comprise an insulating material, for example a thin oxide layer or a high-k dielectric, such as e.g. Ta 2 O 5 , HfO 2 , Ti 2 O, SiC, a polymer or a biomolecule, for use as a capacitive sensor.
  • a thin oxide layer or a high-k dielectric such as e.g. Ta 2 O 5 , HfO 2 , Ti 2 O, SiC, a polymer or a biomolecule, for use as a capacitive sensor.
  • the dots 22 may also comprise a polymer for use as organic optical devices, organic solar cells, chemical sensors or biosensors.
  • the dot 22 may be bio-functionalized.
  • the electronic device may be used as a sensor for protein detection, antigen detection, DNA detection, microparticle or nanoparticle detection, or detection of any other type of molecule.
  • the sensor may also be used in other types of measurements and experiments, such as e.g. amperometric measurements or impedance-spectroscopy measurements.
  • An active sensor may be formed by depositing a Si layer and creating doped areas and interconnect patterns. Similar as described above, for lithography, the top surface on which the lithography has to be performed needs to be substantially flat, as represented in Figures 8(d) or 8(e) or in Figures 9(f) or 9(g) .
  • the simplest implementation of an active sensor may be an ISFET (ions-sensitive field effect transistor) made of a p-silicon bulk, n-doped source and drain areas, contacts to connect to the vias through the microneedle 10, and a thin oxide on top.
  • the sensor may also be an organic based ISFET.
  • the microneedle 10 may comprise an insulating layer 6 surrounding a partly filled channel thereby forming two filled channels 7 isolated from each other by an insulating material.
  • This may also be referred to as a microneedle 10 comprising multiple conductors 7 isolated from each other by an insulating material.
  • each of the filled channels or conductors 7 may be connected with a different electronic circuitry 2 present in the substrate 1. According to other embodiments, however, all filled channels or conductors 7 may connected to a same electronic circuitry 2 present in the substrate 1 (not shown in the figures).
  • the devices on top of the needles in Figures 10(c) and 10(d) can be fabricated after steps (d) or (e) in Figure 8 or steps (f) or (g) in Figure 9 .
  • a protecting insulator 23 is deposited, followed by the deposition of a semiconductor layer 24, e.g. silicon.
  • holes, in the example given two holes may be etched through the semiconductor layer 24 and the insulation layer 23.
  • the holes can be filled with a filling material.
  • This filling material can be a conducting material.
  • the excess of filling material can be removed with for example CMP.
  • an etching step is performed so as to realise the needles.
  • first layers 23 and 24 can be deposited onto the insulating layer 14. Then holes may be etched through the layers 24 and 23, and through insulating layers 5 and 6 underneath. The holes are filled with a conducting material followed by removal of excess of conductive material by e.g. CMP as described in Figures 6(c), and (d) . Finally an etching step may be performed so as to realise the needles.
  • electronic devices which comprise a sensor may be formed on top of the needles. This may be done as follows.
  • a layer of semiconductor material such as e.g. silicon, may be deposited.
  • Filled channels 8 through the silicon can be made by a patterned implantation of a p-type doping material such as e.g. boron.
  • Active parts of the sensor can be made by patterning p- and n-doped regions on top of the filled channels, thus forming semiconductor circuits.
  • a sensor can be made by depositing an electrode comprising, for example, Au, TiN, Pt, or any other appropriate metal, or by depositing a thin oxide layer such as e.g. SiO 2 or a high-k dielectric, such as e.g.
  • a chip or electronic circuitry on top of the microneedle 10 can be made as follows.
  • a chip may be formed using the following processing steps: patterning for doped regions, providing metal layers and circuits.
  • Many types of active sensors can be formed, such as e.g. ISFETs, photoreceptors, or other chips.
  • the chip outline around the microneedle 10 may be etched to isolate the chips on top of the microneedle 10.
  • finishing of the active electrode depends on the type of active sensor required. In case of an ISFET, it may, for example, be required to add a layer of a high-k dielectric material.
  • the microneedle 10 may comprise an insulating layer 6 surrounding a filled channel 7 and a hollow channel 8 isolated from each other by an isolating material.
  • the hollow channel 8 may function as a microfluidic channel.
  • the filled channel 7 may be connected to electronic circuitry 2 present in the substrate 1 and the hollow channel 8 may be connected with a microfluidic channel 3 present in the substrate 1.
  • the filled channel 7 and the hollow channel 8 may be formed by any technique as described above and may be formed before creating a chip or electronic circuitry on top of the microneedle 10. This can be done performed after step (d) in Figure 8 or step (f) in Figure 9 , before creating a chip or a sensor or any other electronic circuitry on top of the microneedle 10.
  • a sensor e.g. pH sensor, ISFET or biosensor
  • a sensor may be formed to, for example, detect an amount of liquid released by a microfluidic channel 7 of the device.
  • This may, for example, be used to detect chemical reactions in close vicinity of the microneedle 10 between the released liquid and a medium outside the microneedle 10, to detect bio-molecules released by a cell with the outside the microneedle 10, to detect bio-molecules released by a cell with the microneedle 10 inserted into the cell, to measure and quantify an amount of liquid released by the microfluidic channel 7 of the device, or to perform a micro-dialysis method, which requires an inlet and an outlet.
  • microfluidic chips may be electrophoresis-driven microfluidic actuators (micro-pumps to pump in or out the liquid), piezo-electric driven actuators or MEMS based valves.
  • nanoparticles can be transported through the microfluidic channels 3, 8.
  • a nanoparticle sensor could be added, e.g. of an electrostatic type.
  • nanoparticle actuators can be added on top of the microneedle 10 to drive the nanoparticles. This can be used to inject nanoparticles inside a cell.
  • the nanoparticles can be bio-functionalized to bind specific molecules, and the nanoparticles can afterwards be detected using the sensor on top of the microneedle 10, or even be transported back outside the cell to analyze it using the electronic circuitry below the microneedles 10, i.e. the electronic circuitry 2 in the substrate 1. This could also be performed in a micro-dialysis type of approach.
  • microneedle 10 has to be noted that, although the presence of electronic circuitry or a chip on top of the microneedle 10 is only illustrated for the electronic devices of Figure 10(c) and 10(d) in combination with a microneedle 10 having a channel that is partly filled, according to embodiments of the invention electronic circuitry or a chip may also be provided on top of microneedles 10 having any configuration as described in the above discussed embodiments.
  • Microneedles 10 with a width of ⁇ 250 nm and a height of 1 ⁇ m were produced using a Cu damascene approach.
  • the microneedles 10 were further oxidized or electroplated with a noble metal to prevent Cu-induced cytotoxicity.
  • Cu microneedles 10 comprising an SiO 2 isolation layer 6 have been made using CMOS processing techniques. The different processing steps are described below. The steps refer to the steps as presented in Figure 11 .
  • a layer 35 of oxide was deposited (see Figure 11 (b) ).
  • the layer 35 of oxide had a thickness of 1.4 ⁇ m.
  • a lithographic step was then performed, with used a dark-field mask with holes of 250 nm to 1000 nm to form holes 36 in the oxide layer 35.
  • the holes 36 were etched with DRIE etch through the oxide down to the SiC layer 34 which acts as an etch stop layer. In another etching step, the SiC layer 34 was then removed.
  • a TaN/Ta barrier layer 39 of 10 nm TaN and 5 nm Ta was deposited (see Figure 10(c) ).
  • the TaN/Ta barrier layer 39 will acts as a diffusion barrier for preventing Cu diffusion.
  • the holes 36 were filled with Cu 37 by Cu plating. This was followed by CMP step in order to remove the excess Cu on the oxide layer 35 in between the holes 36 (see Figure 11 (e) ).
  • a lithographic step was performed using a bright-field mask with dots 40 with dimensions, e.g. diameters ranging from 500 nm to 1.25 ⁇ m, thereby covering an area slightly larger than the holes 36, as was described earlier (see Figure 11 (g) ).
  • This was followed by a DRIE etch, which was timed in such a way that 1 ⁇ m of oxide was removed.
  • a SiO 2 layer 36 with a thickness of 125 nm remains to form sidewalls of the microneedles 10. This serves for two major purposes: sealing the Cu inside the microneedles 10 from contaminants from the outside world (for example liquids) and reduction of parasitic capacitance thereby improving the isolation.
  • Finishing the sensor as a passive electrode was done by depositing a 100 nm layer 38 of Ta 2 O 5 (see Figure 11(h) ).
  • the electronic device formed serves as a capacitive sensor, and prevents the Cu inside the microneedles 10 to come in contact with the environment (such as liquids).
  • Figures 12(a) , 12(b) and 12(c) show SEM pictures of microneedles 10 formed in the experiment described above. Various types of microneedles 10 with several dimensions were made.
  • Figure 12(a) an array of microneedles 10 is shown obtained with a method according to the present experiment.
  • Figure 12(b) shows one microneedle 10 from the array of microneedles 10 shown in Figure 12(a) .
  • the microneedle10 shown Figure 12 (b) has a width w 1 of 500 nm at the top and a width w 2 of 550 nm at the bottom.
  • the length L is 1050 nm.
  • FIG 12(c) another array of microneedles 10 is shown obtained with a same method according to the present experiment.
  • microneedles 10 may be provided in a matrix comprising logically organised columns and rows.
  • FIG. 13(a) shows an array of microneedles 10 formed by the method as described above, each of the microneedles 10 comprising a Au electrode 40 on top.
  • Figure 13(b) shows another array of microneedles 10 comprising Au electrodes 40 on top and formed by the present experiment.
  • Figure 13(c) shows a detail of the array of microneedles 10 of Figure 13(a) .
  • Tungsten microneedles 10 with an aspect ratio (height/diameter) of 1, and thus with equal dimensions in height and diameter of ⁇ 1.5 ⁇ m, with a SiO 2 insulating layer and TiN top electrodes were produced as follows. The process was performed on top of Si wafers with a SiO 2 dielectric, but the process can also be performed on top of a wafer with metal contacts (for example Cu damascene or Al metal lines) in order to connect the nail electrode to, for example CMOS circuits.
  • metal contacts for example Cu damascene or Al metal lines
  • a barrier layer of 50 nm SiC was deposited in order to prevent diffusion of toxic components from underlying circuitry 2 present in the substrate 1 to the conductive material 7 of the microneedle 10.
  • a dielectric layer of 3 ⁇ m SiO 2 was deposited.
  • a lithography step was performed prior to a DRIE-etch in order to etch holes through the 3 ⁇ m SiO 2 layer.
  • the SiC was then removed with a second etch step.
  • Ti/TiN is deposited, resulting in a 10 nm/20 nm Ti/TiN layer at the sidewalls of the holes.
  • This Ti/TiN layer will function as a diffusion barrier layer for the Tungsten.
  • the holes were filled with tungsten by CVD (chemical vapour deposition).
  • the wafer was planarized with a CMP step, which exposes the 3 ⁇ m SiO 2 at the top, and leaving the holes filled with tungsten. Thereafter, a 100nm layer of TiN was deposited, followed by a lithography step, leaving dots of resist centred on top of the tungsten-filled holes.
  • a DRIE etch step is performed to etch through the TiN and through the SiO 2 .
  • a DRIE etch step is performed to etch through the TiN and through the SiO 2 .
  • the DRIE etch By correctly timing the DRIE etch, only the top 1.5 ⁇ m of SiO 2 is removed, which results in a remaining 1.5 ⁇ m of SiO 2 dielectric. Due to the shadow effect of the DRIE etch with the dot of resist, the SiO 2 under the resist is not removed, resulting in an insulating channel of SiO 2 and Ti/TiN around the tungsten core.
  • Figure 11 (h) shows a SEM picture of a microneedle structure 10 obtained by the experiment described above, i.e. a microneedle 10 comprising a tungsten filled channel 8 and SiO 2 insulating layer 6 surrounding the channel 8 and a TiN electrode 40 on top of the microneedle 10.
  • tungsten other materials as core material, such as for example: doped Si, SiGe, Al, Au, Pt, Cu, ... or other materials as top electrode, for example: Au, Pt, SiO 2 , Ta 2 O 5 , ... or other materials as insulator: SiC, polymers, ...

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Claims (17)

  1. Verfahren zum Herstellen einer elektronischen Vorrichtung zum Abtasten und/oder Betätigen, wobei das Verfahren ein Bereitstellen zumindest einer Mikronadel (10) auf einer Trägerschicht (1) umfasst, die zumindest einen Kanal (8) umfasst, welcher von einem Schaft (6) aus Isolationsmaterial umgeben ist, wobei der Kanal (7, 8) eine Längsachse hat, welche sich in einer Richtung im Wesentlichen rechtwinklig zur Ebene der Trägerschicht (1) erstreckt, umfassend, in einer ersten Alternative, die Schritte:
    Bereitstellen einer strukturierten Isolationsschicht (14) auf der Trägerschicht (1), wobei die strukturierte Isolationsschicht (14) zumindest ein Loch (11) umfasst;
    Ätzen der Isolationsschicht (14), um den Schaft (6) zu bilden, welcher den zumindest einen Kanal (7, 8) umgibt,
    und umfassend, in einer zweiten Alternative, die Schritte:
    Bereitstellen einer strukturierten Schicht (17) aus Füllmaterial, wodurch Noppen aus Füllmaterial auf der Trägerschicht bereitgestellt sind;
    Bereitstellen eines Isolationsmaterials (16) zwischen und auf der Oberseite der Noppen aus Füllmaterial, und
    Ätzen der Isolationsschicht (16), um den Schaft (6) zu bilden, welcher zumindest einen Kanal (7, 8) umgibt.
  2. Verfahren nach Anspruch 1, beide Alternativen, wobei die Bildung des Schafts (6) die Schritte umfasst:
    - Bilden von Fotolackpunkten mit einem Durchmesser zwischen 100 nm und 6 µm auf der Oberseite der Isolationsschicht (14, 16) an Stellen, welche nicht zu entfernen sind (6, 7, 8);
    - Ätzen der Isolationsschicht (14, 16), welche die Kanäle (7, 8) umgibt, wobei eine dünne Schicht (6) aus Isolationsmaterial zwischen 50 nm und 1000 nm, welche die Kanäle (7, 8) umgibt, verbleibt und eine Isolationsschicht (5) auf der Trägerschicht (1) verbleibt, und Erzeugen von Hohlräumen (12) zwischen den Mikronadeln (10), wobei die Mikronadeln mit einer Höhe zwischen 150 nm und 50 µm, einem Durchmesser zwischen 50 nm und 10 µm und einem Aspektverhältnis zwischen 0,5 und 10 bereitgestellt sind.
  3. Verfahren nach Anspruch 1, erste Alternative, wobei die Löcher (11) vor dem Ätzen mit einem leitfähigen Material (18) gefüllt werden.
  4. Verfahren nach Anspruch 1 oder 3, wobei vor dem Ätzschritt das Füllmaterial (17, 18) von einigen der Kanäle (7, 8) entfernt wird, um eine Kombination aus hohlen Kanälen (8) und gefüllten Kanäle (7) zu erhalten.
  5. Verfahren nach Anspruch 1, zweite Alternative, wobei vor dem Füllen der Löcher (11) eine Sperrschicht (9) abgeschieden wird.
  6. Verfahren nach Anspruch 1, erste Alternative, wobei die strukturierte Isolationsschicht (14) eine Kombination von Schichten ist.
  7. Verfahren nach Anspruch 2, wobei die Fotolackpunkte auf der Oberseite der gefüllten und hohlen Kanälen gebildet sind.
  8. Verfahren nach Anspruch 7, wobei die Punkte ein wenig größer sein können als der Durchmesser der Kanäle, wodurch die Breite der Isolationsschicht (6) bestimmt wird, welche die Kanäle (7, 8) umgibt.
  9. Verfahren nach Anspruch 1 oder 2, wobei das Isolationsmaterial geätzt ist, um den Schaft mit einer Außenseite zu bilden, welche bei Betrachtung von oben eine vorbestimmte, lithografisch bestimmte Form hat.
  10. Verfahren nach Anspruch 9, wobei die Form aus der Gruppe von rund, oval, quadratisch, rechteckig, sternförmig, dreieckig, achteckig gewählt ist.
  11. Verfahren nach Anspruch 1 oder 4, wobei die zumindest eine Mikronadel sowohl einen hohlen Kanal als auch einen gefüllten Kanal umfasst.
  12. Verfahren nach Anspruch 1, wobei das Ätzen der Isolationsschicht (14, 16) oder des Isolationsmaterials (16) durch Einführen einer zwischenliegenden Ätzstoppschicht (4) kontrolliert ist.
  13. Verfahren nach Anspruch 1, wobei zusätzliche Komponenten auf der Mikronadel (10) hinzugefügt sind, um die elektronische Vorrichtung zu vervollständigen.
  14. Verfahren nach Anspruch 13, wobei eine Isolationsschicht (21) auf der Oberseite der Mikronadel (10) mit einem gefüllten Kanal (7) abgeschieden ist, um einen kapazitiven Sensor zu erhalten.
  15. Verfahren nach Anspruch 13, wobei ein aktiver Sensor auf der Oberseite der Mikronadel (10) durch Abscheiden einer Siliziumschicht und Erzeugen dotierter Areale und Zwischenverbindungsstrukturen gebildet ist.
  16. Verfahren nach Anspruch 1, wobei die Mikronadel (10) einen Schaft (6) umfasst, welcher einen teilweisen gefüllten Kanal umgibt, wodurch zwei gefüllte Kanäle (7) gebildet werden, welche voneinander durch ein Isolationsmaterial isoliert sind.
  17. Verfahren nach Anspruch 13 oder 16, wobei zuerst ein schützender Isolator (23) auf der Mikronadel (10) abgeschieden wird, gefolgt vom Abscheiden einer Halbleiterschicht (24), wonach Löcher durch die Halbleiterschicht (24) und den Isolator (23) geätzt und die Löcher mit einem Füllmaterial gefüllt werden.
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