EP1962210A4 - Method for reconstructing statement, and computer system having the function therefor - Google Patents
Method for reconstructing statement, and computer system having the function thereforInfo
- Publication number
- EP1962210A4 EP1962210A4 EP06833778A EP06833778A EP1962210A4 EP 1962210 A4 EP1962210 A4 EP 1962210A4 EP 06833778 A EP06833778 A EP 06833778A EP 06833778 A EP06833778 A EP 06833778A EP 1962210 A4 EP1962210 A4 EP 1962210A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- reconstructing
- statement
- computer system
- function therefor
- therefor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005344894 | 2005-11-30 | ||
PCT/JP2006/323975 WO2007063957A1 (en) | 2005-11-30 | 2006-11-30 | Method for reconstructing statement, and computer system having the function therefor |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1962210A1 EP1962210A1 (en) | 2008-08-27 |
EP1962210A4 true EP1962210A4 (en) | 2010-03-17 |
Family
ID=38092290
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP06833778A Withdrawn EP1962210A4 (en) | 2005-11-30 | 2006-11-30 | Method for reconstructing statement, and computer system having the function therefor |
Country Status (6)
Country | Link |
---|---|
US (1) | US8200469B2 (en) |
EP (1) | EP1962210A4 (en) |
JP (1) | JP4968478B2 (en) |
KR (1) | KR101275727B1 (en) |
CN (1) | CN101351801B (en) |
WO (1) | WO2007063957A1 (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8341612B2 (en) * | 2007-05-16 | 2012-12-25 | International Business Machines Corporation | Method and apparatus for run-time statistics dependent program execution using source-coding |
JP5328447B2 (en) * | 2009-03-30 | 2013-10-30 | シャープ株式会社 | High-level synthesis apparatus and high-level synthesis method, semiconductor integrated circuit manufacturing method, control program, and readable storage medium |
US10958081B1 (en) * | 2015-03-15 | 2021-03-23 | AI Incorporated | Built in robotic floor cleaning system |
US9684746B2 (en) | 2015-10-13 | 2017-06-20 | Synopsys, Inc. | Signal reconstruction in sequential logic circuitry |
JP6667740B2 (en) * | 2017-12-18 | 2020-03-18 | 三菱電機株式会社 | Display control device, display system, display device, display method, and display program |
CN110990137B (en) * | 2019-11-28 | 2022-08-26 | 北京字节跳动网络技术有限公司 | Application program function module scheduling method, scheduling information processing method and device |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6223141B1 (en) | 1998-07-14 | 2001-04-24 | Nec Usa, Inc. | Speeding up levelized compiled code simulation using netlist transformations |
JP2000082091A (en) | 1998-09-08 | 2000-03-21 | Nec Corp | Device and method for function simulation and recording medium |
US7502728B1 (en) * | 2002-04-30 | 2009-03-10 | Unisys Corporation | Code coverage testing in hardware emulation |
EP1659486B1 (en) | 2003-08-29 | 2019-04-17 | Fuji Xerox Co., Ltd. | Data processing device |
US7409328B1 (en) * | 2003-11-13 | 2008-08-05 | Cadence Design Systems, Inc. | System and method for communicating simulation solutions between circuit components in a hierarchical data structure |
US7392170B1 (en) * | 2003-11-13 | 2008-06-24 | Cadence Design Systems, Inc. | System and method for dynamically compressing circuit components during simulation |
US7353162B2 (en) * | 2005-02-11 | 2008-04-01 | S2C, Inc. | Scalable reconfigurable prototyping system and method |
US7971168B1 (en) * | 2007-06-01 | 2011-06-28 | Magna Design Automation, Inc. | Method for repeated block timing analysis |
-
2006
- 2006-11-30 JP JP2007548006A patent/JP4968478B2/en not_active Expired - Fee Related
- 2006-11-30 WO PCT/JP2006/323975 patent/WO2007063957A1/en active Application Filing
- 2006-11-30 CN CN2006800501314A patent/CN101351801B/en active Active
- 2006-11-30 EP EP06833778A patent/EP1962210A4/en not_active Withdrawn
- 2006-11-30 US US12/095,396 patent/US8200469B2/en not_active Expired - Fee Related
-
2008
- 2008-06-27 KR KR1020087015815A patent/KR101275727B1/en active IP Right Grant
Non-Patent Citations (6)
Title |
---|
CHARLTON C C ET AL: "LAZY SIMULATION OF DIGITAL LOGIC", COMPUTER AIDED DESIGN, ELSEVIER PUBLISHERS BV., BARKING, GB, vol. 23, no. 7, 1 September 1991 (1991-09-01), pages 506 - 513, XP000236522, ISSN: 0010-4485 * |
CHARLTON C C ET AL: "MATTRESS: an integrated environment for the design, analysis and programming of digital systems", 19900101, 1 January 1990 (1990-01-01), pages 241 - 246, XP006517264 * |
CLIFTON MITCHELL H: "Comparison of space requirements for short-circuit and full evaluation of Boolean expressions", PROCEEDINGS OF THE ANNUAL SOUTHEAST CONFERENCE 1998 ACM, 1998, pages 261 - 267, XP002566669 * |
DUNNE P E ET AL: "Sequential and parallel strategies for the demand-driven simulation of logic circuits", MICROPROCESSING AND MICROPROGRAMMING, ELSEVIER SCIENCE PUBLISHERS, BV., AMSTERDAM, NL, vol. 38, no. 1-5, 1 September 1993 (1993-09-01), pages 519 - 525, XP024233290, ISSN: 0165-6074, [retrieved on 19930901] * |
LEUPERS R ET AL: "A BDD-based frontend for retargetable compilers", EUROPEAN DESIGN AND TEST CONFERENCE, 1995. ED&TC 1995, PROCEEDINGS. PARIS, FRANCE 6-9 MARCH 1995, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 6 March 1995 (1995-03-06), pages 239 - 243, XP010148010, ISBN: 978-0-8186-7039-8, DOI: 10.1109/EDTC.1995.470389 * |
See also references of WO2007063957A1 * |
Also Published As
Publication number | Publication date |
---|---|
WO2007063957A1 (en) | 2007-06-07 |
US20090210211A1 (en) | 2009-08-20 |
US8200469B2 (en) | 2012-06-12 |
KR20080089575A (en) | 2008-10-07 |
KR101275727B1 (en) | 2013-06-14 |
CN101351801B (en) | 2011-06-15 |
CN101351801A (en) | 2009-01-21 |
JPWO2007063957A1 (en) | 2009-05-07 |
EP1962210A1 (en) | 2008-08-27 |
JP4968478B2 (en) | 2012-07-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 20080630 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR |
|
A4 | Supplementary search report drawn up and despatched |
Effective date: 20100216 |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: FUJI XEROX CO., LTD. |
|
17Q | First examination report despatched |
Effective date: 20100712 |
|
DAX | Request for extension of the european patent (deleted) | ||
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
18D | Application deemed to be withdrawn |
Effective date: 20150408 |