EP1934845A4 - Hardware acceleration system for logic simulation using shift register as local cache - Google Patents
Hardware acceleration system for logic simulation using shift register as local cacheInfo
- Publication number
- EP1934845A4 EP1934845A4 EP06803124A EP06803124A EP1934845A4 EP 1934845 A4 EP1934845 A4 EP 1934845A4 EP 06803124 A EP06803124 A EP 06803124A EP 06803124 A EP06803124 A EP 06803124A EP 1934845 A4 EP1934845 A4 EP 1934845A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- shift register
- local cache
- hardware acceleration
- logic simulation
- acceleration system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/238,505 US7444276B2 (en) | 2005-09-28 | 2005-09-28 | Hardware acceleration system for logic simulation using shift register as local cache |
US11/291,164 US20070073999A1 (en) | 2005-09-28 | 2005-11-30 | Hardware acceleration system for logic simulation using shift register as local cache with path for bypassing shift register |
PCT/US2006/034865 WO2007037935A2 (en) | 2005-09-28 | 2006-09-07 | Hardware acceleration system for logic simulation using shift register as local cache |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1934845A2 EP1934845A2 (en) | 2008-06-25 |
EP1934845A4 true EP1934845A4 (en) | 2010-05-19 |
Family
ID=37900218
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP06803124A Withdrawn EP1934845A4 (en) | 2005-09-28 | 2006-09-07 | Hardware acceleration system for logic simulation using shift register as local cache |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP1934845A4 (en) |
TW (1) | TW200731104A (en) |
WO (1) | WO2007037935A2 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030105617A1 (en) * | 2001-12-05 | 2003-06-05 | Nec Usa, Inc. | Hardware acceleration system for logic simulation |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6766445B2 (en) * | 2001-03-23 | 2004-07-20 | Hewlett-Packard Development Company, L.P. | Storage system for use in custom loop accelerators and the like |
JP3979998B2 (en) * | 2002-04-18 | 2007-09-19 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | VLIW processor with data spinning means |
-
2006
- 2006-09-07 WO PCT/US2006/034865 patent/WO2007037935A2/en active Application Filing
- 2006-09-07 EP EP06803124A patent/EP1934845A4/en not_active Withdrawn
- 2006-09-26 TW TW095135604A patent/TW200731104A/en unknown
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030105617A1 (en) * | 2001-12-05 | 2003-06-05 | Nec Usa, Inc. | Hardware acceleration system for logic simulation |
Non-Patent Citations (2)
Title |
---|
CADAMBI S ET AL: "A fast, inexpensive and scalable hardware acceleration technique for functional simulation", PROCEEDINGS - DESIGN AUTOMATION CONFERENCE 2002 INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS INC. US; [PROCEEDINGS OF THE DESIGN AUTOMATION CONFERENCE],, vol. CONF. 39, 10 June 2002 (2002-06-10), pages 570 - 575, XP002275521, ISBN: 978-1-58113-461-2 * |
WEINHARDT M ET AL: "Memory access optimisation for reconfigurable systems", IEE PROCEEDINGS E. COMPUTERS & DIGITAL TECHNIQUES, INSTITUTION OF ELECTRICAL ENGINEERS. STEVENAGE, GB LNKD- DOI:10.1049/IP-CDT:20010514, vol. 148, no. 3, 23 May 2001 (2001-05-23), pages 105 - 112, XP006016645, ISSN: 0143-7062 * |
Also Published As
Publication number | Publication date |
---|---|
TW200731104A (en) | 2007-08-16 |
WO2007037935A3 (en) | 2009-05-07 |
EP1934845A2 (en) | 2008-06-25 |
WO2007037935A2 (en) | 2007-04-05 |
WO2007037935A9 (en) | 2008-05-08 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 20080331 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR |
|
AX | Request for extension of the european patent |
Extension state: AL BA HR MK RS |
|
R17D | Deferred search report published (corrected) |
Effective date: 20090507 |
|
A4 | Supplementary search report drawn up and despatched |
Effective date: 20100416 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
18D | Application deemed to be withdrawn |
Effective date: 20100402 |