EP1933221A1 - Spannungsregler mit verbessertem transientem Ansprechverhalten - Google Patents

Spannungsregler mit verbessertem transientem Ansprechverhalten Download PDF

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Publication number
EP1933221A1
EP1933221A1 EP06025990A EP06025990A EP1933221A1 EP 1933221 A1 EP1933221 A1 EP 1933221A1 EP 06025990 A EP06025990 A EP 06025990A EP 06025990 A EP06025990 A EP 06025990A EP 1933221 A1 EP1933221 A1 EP 1933221A1
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EP
European Patent Office
Prior art keywords
voltage
output voltage
terminal
load current
iload
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Granted
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EP06025990A
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English (en)
French (fr)
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EP1933221B1 (de
Inventor
Emanuele Bodano
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Infineon Technologies AG
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Infineon Technologies AG
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Priority to EP20060025990 priority Critical patent/EP1933221B1/de
Publication of EP1933221A1 publication Critical patent/EP1933221A1/de
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Publication of EP1933221B1 publication Critical patent/EP1933221B1/de
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices

Definitions

  • the present invention relates to voltage regulators, especially to voltage regulators having a low voltage drop, a low current consumption and a fast transient response.
  • a low voltage drop over the voltage regulator is achieved by the use of a MOSFET as a voltage regulating element together with a charge pump providing a sufficiently high gate potential which has to be higher than the output voltage of the voltage regulator, in the case of a low drop regulator even higher than the input voltage of the voltage regulator.
  • the gate of the voltage regulating MOSFET (e.g. a power MOSFET) is supplied with a bias current provided by a charge pump and controlled by a closed loop control system. That is, the output voltage of the voltage regulator is received by a controller which controls the gate current (and therefore the gate voltage) of the voltage regulating MOSFET such, that the output voltage of the voltage regulator remains substantially constant.
  • the output voltage In response to an upward step of the load current (i.e. the output current) the output voltage will slightly drop due to the higher voltage drop over the voltage regulating MOSFET. Triggered by this voltage drop the controller will increase the gate current for charging the gate-source-capacitance of the voltage regulating MOSFET in order to increase the conductivity of the voltage regulating MOSFET thus re-adjusting the output voltage to its desired value.
  • the load current i.e. the output current
  • the time which is needed to compensate for the disturbance in the output voltage induced by the step in a load current is determined by the loop bandwidth of the closed loop control system and especially dependent on the value of the gate-source-capacitance of the voltage regulating MOSFET.
  • the speed of the closed loop control system can only be increased by increasing the gate current which charges the gate of the MOSFET.
  • This gate current is supplied by a charge pump, as explained before, and, in order to minimize power consumption, an increase of the maximum gate current which would entail a more costly charge pump is not desirable.
  • the inventive voltage regulator comprises a power filed effect transistor having a threshold voltage, a drain terminal receiving an input voltage, a source terminal providing an output voltage and a load current, a gate terminal responsive to a control signal, and a bulk terminal.
  • the voltage regulator further comprises a control loop circuits responsive to the output voltage and providing the control signal.
  • the control loop circuit is adapted for adjusting said control signal to such a value that the output voltage is regulated to a desired (constant) value.
  • the threshold voltage of the power field effect transistor is modified dependent on the load current.
  • the threshold voltage can be modified dependent on the output voltage or on both, the output voltage and the load current.
  • the voltage regulator additionally comprises a switching circuit for modifying the threshold voltage.
  • the switching circuit is responsive to the output voltage and/or to the load current and it is adapted for connecting the bulk terminal of the field effect transistor with either the source terminal or a constant potential dependent on the load currents and/or the output voltage.
  • the invention also comprises a method for controlling the power field effect transistor which was defined above.
  • the method comprises the step of modifying the threshold voltage dependent on the load current and/or the output voltage. This can be done, for example, by a connecting the bulk terminal of the field effect transistor with either the source terminal or a constant potential dependent on the load current and/or the output voltage.
  • Figure 1 shows a simple voltage regulator using a power MOSFET Mp as a voltage regulating element.
  • a n-MOS transistor is used whose drain terminal D is connected to a first supply terminal receiving an input voltage Vin and whose source terminal S is connected to an output terminal providing an output voltage Vout and a load current Iload.
  • a capacitance Cout is connected between the source terminal S and a second supply terminal, e.g. a ground terminal GND.
  • the voltage regulator further comprises a feedback circuit 10 for regulating the output voltage Vout, i.e. the source potential of the power MOSFET, to a desired (e.g. constant) value.
  • the feedback circuit 10 comprises a controller 13 whose input is connected to the source terminal S and responsive to the output voltage Vout.
  • the output of the controller 13 provides a controller voltage Vc received by the gate of a controlling transistor 12 whose source terminal is connected to the ground terminal GND and whose drain terminal is connected to the gate G of the voltage regulating power MOSFET Mp and to a current source 11 providing a bias current Ibias to the gate G and to the controlling transistor 12.
  • the current source 11 is connected to a third supply terminal receiving a supply voltage Vcp provided by a charge pump (not shown).
  • FIG. 4 illustrates the step response of the output voltage Vout, the controller voltage Vc, and the gate voltage Vg to an upward step of the load current Iload.
  • the drain-source voltage Vds of the power MOSFET Mp has been adjusted by the feedback circuit 10 such, that drain-source voltage Vds (i.e. the product RDS ⁇ Iload of the drain-source resistance RDS and the load current Iload) is equal to the difference between the supply voltage Vin and the output voltage Vout.
  • An upward step of the load current Iload firstly results in a drop of the output voltage Vout.
  • the controller 13 reduces the controller voltage Vc, i.e. the gate voltage of the controlling transistor 12, thus increasing the fractional part of the bias current Ibias used for charging the gate (i.e. the gate-source-capacitance) of the power MOSFET Mp.
  • An increased gate charge results in a higher gate voltage Vg of the power MOSFET and in a lower drain-source voltage Vds (i.e. in a lower drain-source resistance RDS) which compensates for the higher load current Iload, thus readjusting the output voltage to its desired (constant) value.
  • the time which is needed to readjust the drop in the output voltage Vout to its desired constant value depends on the time the feedback circuit 10 needs to react to a drop in the output voltage, i.e. the loop delay time tL, the time which is needed to charge the gate-source capacitance of the power MOSFET Mp, i.e. the charging time tC.
  • the loop delay time tL depends on the bandwidth of the feedback circuit 10 and is usually much smaller than the charging time tC.
  • To decrease the overall delay time tD (TD tL + tC) it is necessary to reduce the charging time tC, which could be done by increasing the bias current Ibias which would entail higher costs for the current source 11 and the charge pump.
  • FIG. 2 Another possibility to improve the overall delay tD time without the need for increasing the bias current Ibias is shown in figure 2 .
  • a current measurement means 30 is connected in series to the drain-source path of the power MOSFET Mp.
  • the current measurement means is connected between the drain terminal D of the power MOSFET Mp and the supply terminal receiving Vin.
  • the current measurement means 30 provides a measurement signal S30 which depends on the load current Iload.
  • the voltage regulator further comprises a switching circuit 20 being responsive to the load current Iload (or, strictly speaking, to the measurement signal S30).
  • the switching circuit 20 is connected to the output terminal providing the output voltage Vout (i.e. the source potential) and with the bulk terminal B of the power MOSFET Mp.
  • the switching circuit comprises a switch SW responsive to the measurement signal S30.
  • the switch SW is adapted for connecting the bulk terminal B of the power MOSFET Mp with either the source terminal S or a constant potential V2 dependent on the value of the load current Iload or the measurement signal S30 respectively.
  • the constant potential V2 is preferably lower than the output voltage Vout and can also be equal to ground potential GND.
  • An "ordinary" MOSFET would have its bulk terminal B connected to its source terminal S.
  • the threshold voltage of the power MOSFET Mp increases, if the switch SW connects the bulk terminal B of the power MOSFET Mp with the constant potential V2 being lower than the source potential (Vout) of the power MOSFET Mp.
  • This state of the switch SW is further referred to as the second switching state.
  • the function of the circuit is explained in more detail by reference to figures 3 and 5 .
  • FIG. 3 shows the embodiment of figure 2 wherein the measurement means 13 and the switching circuit 20 are illustrated in more detail.
  • the measurement circuit 13 comprises a shunt resistor R, a voltage source providing the offset voltage Vos and a comparator 31.
  • the shunt resistor is connected to the drain terminal D of the power MOSFET Mp with its first terminal in series to the drain-source path of the power MOSFET.
  • a second terminal of the shunt resistor R is connected to a non-inverting input of the comparator 31 and the first terminal of the shunt resistor R is also connected to the inverting input of the comparator 31 via the voltage source providing the offset voltage Vos.
  • the output signal of the comparator assumes a first logic level, e.g.
  • the switching 20 circuit comprises a comparator 23, an AND-gate 22 with an inverting and a non-inverting input, and transistors M1, M2 provide the functionality of the switch SW.
  • the comparator 23 is adapted for comparing the output voltage Vout with a reference voltage Vref and for providing an output signal which assumes a first logic level, e.g. a high level, if the output voltage is higher than the reference voltage.
  • the output of the comparator 23 is connected with the non-inverting input of the AND-gate 22.
  • the inverting input of the AND-gate 22 is connected with the output of the comparator 31 which has been described above.
  • the AND-gate 22 provides a switching signal S22 controlling the switching states of the transistors M1, M2.
  • the switching signal S22 assumes a first logic level, e.g. a high level, if the load current Iload is lower than a reference current defined by the quotient Vos/R and the output voltage is higher than the reference voltage Vref. Then the first p-MOS transistor M1 is switched to an off-state and the n-MOS transistor M2 is switched to an on-state, thus isolating the bulk terminal B of the power MOSFET Mp from the output terminal providing the output voltage Vout (and also from its source terminal S) and connecting the bulk terminal B of the power MOSFET Mp with the constant potential V2 which is - in the current case - equal to the ground potential.
  • a first logic level e.g. a high level
  • the output logic level of one of the comparators 23, 31 will change and the output signal S22 of the AND-gate 22 will switch to a second logic level, e.g. a low level, thus switching on the p-MOS transistor M1 and switching off the n-MOS transistor M2 and the p-MOS transistor M3.
  • the bulk terminal B of the power MOSFET Mp is than connected to the source terminal S of the power MOSFET Mp and isolated from the constant potential V2.
  • FIG. 5 shows, like figure 4 , timing diagrams of the load current Iload, the output voltage Vout, the control voltage Vc, the gate voltage Vg, and the bulk voltage Vb.
  • the feedback circuit 10 can react much faster for regulating the output voltage Vout to its desired constant value and the charging time tC is greatly reduced, thus improving the overall performance of the voltage regulator.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)
EP20060025990 2006-12-14 2006-12-14 Spannungsregler mit verbessertem transientem Ansprechverhalten Ceased EP1933221B1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP20060025990 EP1933221B1 (de) 2006-12-14 2006-12-14 Spannungsregler mit verbessertem transientem Ansprechverhalten

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP20060025990 EP1933221B1 (de) 2006-12-14 2006-12-14 Spannungsregler mit verbessertem transientem Ansprechverhalten

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EP1933221A1 true EP1933221A1 (de) 2008-06-18
EP1933221B1 EP1933221B1 (de) 2012-03-21

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8253479B2 (en) 2009-11-19 2012-08-28 Freescale Semiconductor, Inc. Output driver circuits for voltage regulators
DE102018131859B3 (de) 2018-12-12 2020-04-30 Semikron Elektronik Gmbh & Co. Kg Patentabteilung Leistungshalbleitereinrichtung mit einem Leistungshalbleiterschalter und mit einer Steuereinrichtung
CN114448237A (zh) * 2021-12-06 2022-05-06 深圳市创芯微微电子有限公司 一种直流开关电源及其快速瞬态响应电路
CN114637355A (zh) * 2020-12-15 2022-06-17 炬芯科技股份有限公司 一种稳压电路及稳压控制方法
CN114740934A (zh) * 2022-04-29 2022-07-12 北京时代民芯科技有限公司 一种大驱动均衡式ldo电路

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020185681A1 (en) * 2001-06-06 2002-12-12 Takashi Nakano Power MOS transistor having capability for setting substrate potential independently of source potential
US6744288B1 (en) * 2002-10-15 2004-06-01 National Semiconductor Corporation Driver with bulk switching MOS power transistor
US20040239304A1 (en) * 2003-06-02 2004-12-02 Perez Raul A. Threshold voltage adjustment for MOS devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020185681A1 (en) * 2001-06-06 2002-12-12 Takashi Nakano Power MOS transistor having capability for setting substrate potential independently of source potential
US6744288B1 (en) * 2002-10-15 2004-06-01 National Semiconductor Corporation Driver with bulk switching MOS power transistor
US20040239304A1 (en) * 2003-06-02 2004-12-02 Perez Raul A. Threshold voltage adjustment for MOS devices

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
GABRIEL A RINCON-MORA ET AL: "A Low-Voltage, Low Quiescent Current, Low Drop-Out Regulator", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 33, no. 1, January 1998 (1998-01-01), XP011060653, ISSN: 0018-9200 *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8253479B2 (en) 2009-11-19 2012-08-28 Freescale Semiconductor, Inc. Output driver circuits for voltage regulators
DE102018131859B3 (de) 2018-12-12 2020-04-30 Semikron Elektronik Gmbh & Co. Kg Patentabteilung Leistungshalbleitereinrichtung mit einem Leistungshalbleiterschalter und mit einer Steuereinrichtung
CN114637355A (zh) * 2020-12-15 2022-06-17 炬芯科技股份有限公司 一种稳压电路及稳压控制方法
CN114637355B (zh) * 2020-12-15 2023-08-29 炬芯科技股份有限公司 一种稳压电路及稳压控制方法
CN114448237A (zh) * 2021-12-06 2022-05-06 深圳市创芯微微电子有限公司 一种直流开关电源及其快速瞬态响应电路
CN114740934A (zh) * 2022-04-29 2022-07-12 北京时代民芯科技有限公司 一种大驱动均衡式ldo电路
CN114740934B (zh) * 2022-04-29 2024-04-05 北京时代民芯科技有限公司 一种大驱动均衡式ldo电路

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