EP1891485A2 - Systeme de traitement de signal pour synthetiser des hologrammes - Google Patents

Systeme de traitement de signal pour synthetiser des hologrammes

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Publication number
EP1891485A2
EP1891485A2 EP06755786A EP06755786A EP1891485A2 EP 1891485 A2 EP1891485 A2 EP 1891485A2 EP 06755786 A EP06755786 A EP 06755786A EP 06755786 A EP06755786 A EP 06755786A EP 1891485 A2 EP1891485 A2 EP 1891485A2
Authority
EP
European Patent Office
Prior art keywords
data
holographic
image
subframe
hardware
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06755786A
Other languages
German (de)
English (en)
Inventor
Peter William Tudor Mash
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Light Blue Optics Ltd
Original Assignee
Light Blue Optics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GBGB0511962.3A external-priority patent/GB0511962D0/en
Application filed by Light Blue Optics Ltd filed Critical Light Blue Optics Ltd
Publication of EP1891485A2 publication Critical patent/EP1891485A2/fr
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03H—HOLOGRAPHIC PROCESSES OR APPARATUS
    • G03H1/00—Holographic processes or apparatus using light, infrared or ultraviolet waves for obtaining holograms or for obtaining an image from them; Details peculiar thereto
    • G03H1/04—Processes or apparatus for producing holograms
    • G03H1/08—Synthesising holograms, i.e. holograms synthesized from objects or objects from holograms
    • G03H1/0841—Encoding method mapping the synthesized field into a restricted set of values representative of the modulator parameters, e.g. detour phase coding
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03H—HOLOGRAPHIC PROCESSES OR APPARATUS
    • G03H1/00—Holographic processes or apparatus using light, infrared or ultraviolet waves for obtaining holograms or for obtaining an image from them; Details peculiar thereto
    • G03H1/22—Processes or apparatus for obtaining an optical image from holograms
    • G03H1/2294—Addressing the hologram to an active spatial light modulator
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03H—HOLOGRAPHIC PROCESSES OR APPARATUS
    • G03H1/00—Holographic processes or apparatus using light, infrared or ultraviolet waves for obtaining holograms or for obtaining an image from them; Details peculiar thereto
    • G03H1/22—Processes or apparatus for obtaining an optical image from holograms
    • G03H1/2294—Addressing the hologram to an active spatial light modulator
    • G03H2001/2297—Addressing the hologram to an active spatial light modulator using frame sequential, e.g. for reducing speckle noise
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03H—HOLOGRAPHIC PROCESSES OR APPARATUS
    • G03H2210/00—Object characteristics
    • G03H2210/20—2D object
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03H—HOLOGRAPHIC PROCESSES OR APPARATUS
    • G03H2225/00—Active addressable light modulator
    • G03H2225/30—Modulation
    • G03H2225/32—Phase only
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03H—HOLOGRAPHIC PROCESSES OR APPARATUS
    • G03H2226/00—Electro-optic or electronic components relating to digital holography
    • G03H2226/02—Computing or processing means, e.g. digital signal processor [DSP]
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03H—HOLOGRAPHIC PROCESSES OR APPARATUS
    • G03H2240/00—Hologram nature or properties
    • G03H2240/20—Details of physical variations exhibited in the hologram
    • G03H2240/40—Dynamic of the variations
    • G03H2240/41—Binary
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03H—HOLOGRAPHIC PROCESSES OR APPARATUS
    • G03H2240/00—Hologram nature or properties
    • G03H2240/20—Details of physical variations exhibited in the hologram
    • G03H2240/40—Dynamic of the variations
    • G03H2240/42—Discrete level

Definitions

  • This invention relates to hardware acceleration of signal processing systems for displaying an image using holographic techniques.
  • embodiments of the method aim to display an image by projecting light via a spatial light modulator (SLM) onto a screen.
  • SLM spatial light modulator
  • the SLM is modulated with holographic data approximating a hologram of the image to be displayed but this holographic data is chosen in a special way, the displayed image being made up of a plurality of temporal subframes, each generated by modulating the SLM with a respective subframe hologram.
  • These subframes are displayed successively and sufficiently fast that in the eye of a (human) observer the subframes (each of which have the spatial extent of the displayed image) are integrated together to create the desired image for display.
  • Each of the subframe holograms may itself be relatively noisy, for example as a result of quantising the holographic data into two (binary) or more phases, but temporal averaging amongst the subfiames reduces the perceived level of noise. Embodiments of such a system can provide visually high quality displays even though each subframe, were it to be viewed separately, would appear relatively noisy.
  • a scheme such as this has the advantage of reduced computational requirements compared with schemes which attempt to accurately reproduce a displayed image using a single hologram, and also facilitate the use of a relatively inexpensive SLM.
  • the SLM will, in general, provide phase rather than amplitude modulation, for example a binary device providing relative phase shifts of zero and ⁇ (+1 and -1 for a normalised amplitude of unity),
  • more than two phase levels are employed, for example four phase modulation (zero, ⁇ /2, ⁇ , 3 ⁇ /2), since with only binary modulation the hologram results in a pair of images one spatially inverted in respect to the other, losing half the available light, whereas with multi-level phase modulation where the number of phase levels is greater than two this second image can be removed.
  • embodiments of the method are computationally less intensive than previous holographic display methods it is nonetheless generally desirable to provide a system with reduced cost and/or power consumption and/or increased performance. It is particularly desirable to provide improvements in systems for video use which generally have a requirement for processing data to display each of a succession of image frames within a limited frame period.
  • a hardware accelerator for a holographic image display system the image display system being configured to generate a displayed image using a plurality of holographically generated temporal subframes, said temporal subframes being displayed sequentially in time such that they are perceived as a single reduced-noise image, each said subframe being generated holographically by modulation of a spatial light modulator with holographic data such that replay of a hologram defined by said holographic data defines a said subframe
  • the hardware accelerator comprising: an input buffer to store image data defining said displayed image; an output buffer to store holographic data for a said subframe; at least one hardware data processing module coupled to said input data buffer and to said output data buffer to process said image data to generate said holographic data for a said sub frame; and a controller coupled to said at least one hardware data processing module to control said at least one data processing module to provide holographic data for a plurality of said subframes corresponding to image data for a single said displayed image to said output
  • the hardware data processing module comprises a phase modulator coupled to the input data buffer and having a phase modulation data input to modulate phases of pixels of the image in response to an input which preferably comprises at least partially random phase data.
  • This data may be generated on the fly or provided from a non-volatile data store.
  • the phase modulator preferably includes at least one multiplier to multiply pixel data from the input data buffer by input phase modulation data. In a simple embodiment the multiplier simply changes a sign of the input data.
  • an output of the phase modulator is provided to a space-frequency transformation module such as a Fourier transform or inverse Fourier transform module.
  • a space-frequency transformation module such as a Fourier transform or inverse Fourier transform module.
  • these two operations are substantially equivalent, effectively differing only by a scale factor.
  • other space-frequency transformations may be employed (generally frequency referring to spatial frequency data derived from spatial position or pixel image data).
  • the space-frequency transformation module comprises a one-dimensional Fourier transformation module with feedback to perform a two-dimensional Fourier transform of the (spatial distribution of the) phase modulated image data to output holographic sub frame data. This simplifies the hardware and enables processing of, for example, first rows then columns (or vice versa).
  • the hardware data also includes a quantiser coupled to the output of the transformation module to quantise the holographic subframe data to provide holographic data for a subframe for the output buffer.
  • the quantiser may quantise into two, four or more (phase) levels.
  • the quantiser is configured to quantise real and imaginary components of the holographic subframe data to generate a pair of subframes for the output buffer.
  • the output of the space- frequency transformation module comprises a plurality of data points over the complex plane and this may be thresholded (quantised) at a point on the real axis (say zero) to split the complex plane into two halves and hence generate a first set of binary quantised data, and then quantised at a point on the imaginary axis, say Oj, to divide the complex plane into a further two regions (complex component greater than 0, complex component less than 0). Since the greater the number of subframes the less the overall noise this provides further benefits.
  • one or both of the input and output buffers comprise dual-ported memory.
  • the holographic image display system comprises a video image display system and the displayed image comprises a video frame.
  • the invention further provides a holographic image display system including a hardware accelerator as described above.
  • Figure 1 shows an outline block diagram of an embodiment of a hardware accelerator for a holographic image display system.
  • Figure 2 shows the operations performed within an embodiment of a hardware block as shown in Figure I .
  • Figure 3 shows the energy spectra of a sample image before and after multiplication by a random phase matrix.
  • Figure 4 shows an embodiment of a hardware block with parallel quantisers for the simultaneous generation of two subframes from the real and imaginary components of complex holographic sub frame data respectively.
  • Figure 5 shows an embodiment of hardware to generate pseudo-random binary phase data and multiply incoming image data, I xy , by the phase values to produce G xy .
  • Figure 6 shows an embodiment of hardware to multiply incoming image frame data, I xy , by complex phase values, which are randomly selected from a look-up table, to produce phase-modulated image data, G xy .
  • Figure 7 shows an embodiment of hardware which performs a 2 -D FFT on incoming phase-modulated image data, G xy , by means of a 1-D FFT block with feedback, to produce holographic data g uv .
  • FIG. 8 shows sequential interpretation of RBG bitplanes.
  • Figure 9 shows an outline block diagram of further hardware for a holographic image display system.
  • Figure 10 shows an example of a hologram replay field including a conjugate image.
  • Figure 11 shows a detailed block diagram of hardware for a holographic image display system.
  • Figure 12 shows an output collator for use with the holographic image display system of Figure 11.
  • Figure 13 shows conversion from a 4:2:2 to a 4:4:4 sampling scheme.
  • Figure 14 illustrates the display of collated data.
  • Figures 15a and 15b show, respectively, a holographic image display system incorporating a hardware accelerator, and a consumer electronic device incorporating the holographic image display system of Figure 15a.
  • the various stages of the hardware accelerator implement the algorithm listed below.
  • Statistical analysis of the algorithm has shown that such sets of holograms form replay fields that exhibit mutually independent additive noise.
  • Step 1 fonns N targets G[" r ] equal to the amplitude of the supplied intensity target I xy , but with independent identically-distributed (i.i.t), uniformly-random phase.
  • Step 2 computes the N corresponding full complex Fourier transform holograms g H ( ", ⁇ .
  • Steps 3 and 4 compute the real part and imaginary part of the holograms, respectively. Binarisation of each of the real and imaginary parts of the holograms is then performed in step 5: thresholding around the median of n ⁇ " ⁇ ensures equal numbers of -1 and 1 points are present in the holograms, achieving DC balance (by definition) and also minimal reconstruction error.
  • the median value of m ⁇ is assumed to be zero. This assumption can be shown to be valid and the effects of making this assumption are minimal with regard to perceived image quality. Further details can be found in the applicant's earlier application ⁇ ibid), to which reference may be made.
  • Figure 1 shows a block diagram of an embodiment of a hardware accelerator for a holographic image display system.
  • the input to the system is preferably image data from a source such as a computer, although other sources are equally applicable.
  • the input data is temporarily stored in one or more input buffer, with control signals for this process being supplied from one or more controller units within the system.
  • Each input buffer preferably comprises dual-port memory such that data is written into the input buffer and read out from the input buffer simultaneously.
  • the output from the input buffer shown in Figure 1 is an image frame, labelled I, and this becomes the input to the hardware block.
  • the hardware block which is described in more detail using Figure 2, performs a series of operations on each of the aforementioned image frames, I, and for each one produces one or more holographic subframes, h, which are sent to one or more output buffer.
  • Each output buffer preferably comprises dual-port memory.
  • Such subframes are outputted from the aforementioned output buffer and supplied to a display device, such as a SLM, optionally via a driver chip.
  • the control signals by which this process is controlled are supplied from one or more controller unit.
  • the control signals preferably ensure that one or more holographic subframes are produced and sent to the SLM per video frame period.
  • the control signals transmitted from the controller to both the input and output buffers are read / write select signals, whilst the signals between the controller and the hardware block comprise various timing, initialisation and flow-control information.
  • Figure 2 shows an embodiment of a hardware block as described in Figure 1, comprising a set of hardware elements designed to generate one or more holographic subframes for each image frame that is supplied to the block.
  • a hardware block as described in Figure 1, comprising a set of hardware elements designed to generate one or more holographic subframes for each image frame that is supplied to the block.
  • I xy preferably one image frame, I xy , is supplied one or more times per video frame period as an input to the hardware block.
  • the source of such image frames may be one or more input buffers as shown in Figure 1.
  • Each image frame, ⁇ xy is then used to produce one or more holographic subframes by means of a set of operations comprising one or more of: a phase modulation stage, a space-frequency transformation stage and a quantisation stage.
  • a set of N subframes is generated per frame period by means of using either one sequential set of the aforementioned operations, or a several sets of such operations acting in parallel on different subframes, or a mixture of these two approaches.
  • phase-modulation block shown in the embodiment of Figure 2 is to redistribute the energy of the input frame in the spatial-frequency domain, such that improvements in final image quality are obtained after performing later operations.
  • Figure 3 shows an example of how the energy of a sample image is distributed before and after a phase-modulation stage in which a random phase distribution is used. It can be seen that modulating an image by such a phase distribution has the effect of redistributing the energy more evenly throughout the spatial-frequency domain.
  • the quantisation hardware that is shown in the embodiment of Figure 2 has the purpose of taking complex hologram data, which is produced as the output of the preceding space-frequency transform block, and mapping it to a restricted set of values, which correspond to actual phase modulation levels that can be achieved on a target SLM.
  • the number of quantisation levels is set at two, with an example of such a scheme being a phase modulator producing phase retardations of 0 or ⁇ at each pixel.
  • the number of quantisation levels, corresponding to different phase retardations may be two or greater. There is no restriction on how the different phase retardations levels are distributed - either a regular distribution, irregular distribution or a mixture of the two may be used.
  • the quantiser is configured to quantise real and imaginary components of the holographic subframe data to generate a pair of sub frames for the output buffer, each with two phase-retardation levels. It can be shown that for discretely pixellated fields, the real and imaginary components of the complex holographic subframe data are uncorrelated, which is why it is valid to treat the real and imaginary components independently and produce two uncorrelated holographic subframes.
  • Figure 4 shows an embodiment of the hardware block described in Figure 1 in which a pair of quantisation elements are arranged in parallel in the system so as to generate a pair of holographic subframes from the real and imaginary components of the complex holographic subframe data respectively.
  • phase-modulation data may be produced.
  • pseudo-random binary-phase modulation data is generated by hardware comprising a shift register with feedback and an XOR logic gate.
  • Figure 5 shows such an embodiment, which also includes hardware to multiply incoming image data by the binary phase data.
  • This hardware comprises means to produce two copies of the incoming data, one of which is multiplied by -1, followed by a multiplexer to select one of the two data copies.
  • the control signal to the multiplexer in this embodiment is the pseudo-random binary-phase modulation data that is produced by the shift-register and associated circuitry, as described previously.
  • pre-calculated phase modulation data is stored in a look-up table and a sequence of address values for the look-up table is produced, such that the phase-data read out from the look-up table is random.
  • N the number of entries in the look-up table, is greater than the value, m, by which the address value increases each time, that m is not an integer factor of N, and that the address values 'wrap around' to the start of their range when N is exceeded.
  • N is a power of 2, e.g. 256, such that address wrap around is obtained without any additional circuitry, and ni is an odd number such that it is not a factor of N.
  • Figure 6 shows suitable hardware for such an embodiment, comprising a three-input adder with feedback, which produces a sequence of address values for a look-up table containing a set of N data words, each comprising a real and imaginary component.
  • Input image data, I xy is replicated to form two identical signals, which are multiplied by the real and imaginary components of the selected value from the look-up table. This operation thereby produces the real and imaginary components of the phase-modulated input image data, G ⁇ y , respectively.
  • the third input to the adder denoted n
  • n is a value representing the current holographic subframe
  • the third input, n is omitted.
  • FIG. 7 shows an embodiment of hardware which performs a 2-D FFT on incoming phase-modulated image data, G sy , as shown in Figure 2.
  • the hardware required to perform the 2-D FFT operation comprises a 1-D FFT block, a memory element for storing intermediate row or column results, and a feedback path (which may incorporate a scaling factor) from the output of the memory to one input of a multiplexer.
  • the other input of this multiplexer is the phase-modulated input image data, G Xy , and the control signal to the multiplexer is supplied from a controller block as shown in Figure 2.
  • Such an embodiment represents an area-efficient method of performing a 2-D FFT operation.
  • the input image is padded with zeros around the edges to create an enlarged image plane prior to performing a holographic transform, for example, so that the transformed image fits the SLM (for more details see co-pending UK patent application no. 0610784.1 filed 2 June 2006, hereby incorporated by reference in its entirety.
  • the zeros may be omitted to speed up the processing.
  • the holograms were displayed on an SXGA (1280*1024) reflective binary phase modulating spatial light modulator (SLM) made by CRL Opto.
  • SLM spatial light modulator
  • the SLM was driven by CRL Opto's custom interface board, taking either a DVI or a digitised VGA signal.
  • the native signal was a 1280 x 1024 60Hz, 8 bits per colour plane signal, yielding a total of 24 bits. This signal was interpreted as 24 individual binary planes which were displayed sequentially on the SLM at a rate of 1440 frames per second.
  • Figure 8 shows sequential interpretation of the RGB bitplanes.
  • a VGA signal was provided from an FPGA development board.
  • the FPGA development board used to implement the algorithm comprised a Virtex-II (xc2v2000-ff896) Multimedia and Microblaze demonstration board of Xilinx Inc.
  • the Xilinx ISE Foundation software was used to synthesise and implement the design from a Verilog entry.
  • the board was programmed with the Xilinx Parallel Cable FV, and Chipscope Integrated Logic Analyser (ILA) cores were inserted for the process of debugging.
  • Figure 9 shows an outline block diagram of this system.
  • the demonstration board additionally had built in to it a NTSC/PAL video decoder with 10-Bit CCIR656 output (an Analog Devices ADV7185), five separate banks of NfRAM (No Turnaround Random Access Memory; one access per clock cycle reading or writing) (Samsung K7N163601M) and a triple video digital to analog converter (a Fairchild Semiconductor FMS3810) with a SVGA output.
  • the NfRAMs were used for the frame buffers, and the FPGA was used for the two-dimensional FFT and for the thresholding.
  • Figure 1 1 shows a detailed block diagram of this embodiment of the system.
  • the system was designed completely from a Verilog entry.
  • the system incorporates hardware for a two-dimensional Fourier transform.
  • this was implemented by using a single 1024-point, 16-bit precision Fourier transform core.
  • This core was chosen for its streaming capability; i.e. the transform length was only 1024 clock cycles (however the latency is somewhat greater - over 1,800 clock cycles).
  • a two-dimensional Fourier transform can be realized by transforming the rows and the columns: rows
  • a two-dimensional transform may still be achieved by splitting into rows then columns.
  • FFT Fast Fourier Transform
  • ID 1024-point transforms Given that the FFT supports streaming, a complete two dimensional Fourier transform using ID 1024-point transforms therefore takes In 1 clock cycles, plus the latency: i.e. for a clock running at 108Mhz (for reasons described later), a complete 1024x1024 transform takes 19.5ms, or it can be run at a maximum frequency (with this example hardware) of just over 50Hz.
  • a shortcut may be taken when one bears in mind that for any binary hologram, a conjugate image is produced.
  • Figure 10 shows an example of a replay field including such a conjugate image.
  • 1024x1024 hologram only possible 1024x512 target replay field pixels are used. Therefore (in this particular example) only 512 rows need to be transformed as the Fourier transform of 0 is 0. All 1024 columns should, however, be transformed. The number of operations is hence
  • full frame rate video at least 25fps either more FFT cores may be provided in parallel on the FPGA, or the core can be clocked at a higher speed, or a lower value of N can be employed.
  • a median quantisation process for both the real and the imaginary outputs of the Fourier transform helps to ensure the overall DC balancing.
  • Median quantisation generally requires all values to be known before the middle value can be found, so thai all values can be quantised to (1 ,-1) based on which side they are of the median value.
  • Both of these methods can be very easily pipelined: (1) is easily implemented by simply storing the sign-bit of the output of the FFT; and (2) can be pipelined by storing preferably all the last frames FFT output values, and sorting them while the current frame is being calculated.
  • method (1) was chosen for the described example embodiment.
  • the output from the quantiser was collated.
  • the N/RAMs whose data width is 32 bits, have the facility to enable the data to be written by individual bytes.
  • Two dual-memory frame buffers were implemented in the system. Essentially they were composed of two N/RAMs, one being written to while the other read. A single-bit input to the dual-memory frame buffer configured which N/RAM was being written to, hence giving the ability to be able to switch between the two RAMs.
  • the output frame buffer was read continuously by the video DAC for the output SVGA signal, while data was written to it by the collated outputs of the FFT.
  • the input frame buffer had data supplied from the input image FIFO (first-in and first- out) buffer, while data was read in to the phase randomiser.
  • An Analog Devices ADV7185 (NTSC/PAL video decoder) was used to decode a composite video signal.
  • a simple microprocessor was implemented in the FPGA (KCPSM-II (Constant (K) Coded Programmable State Machine 2, written by Chapman, K. of Xilinx Inc.)).
  • the ADV7185 was configured to give 10-bit luminance data interleaved by the two chrominance channels (YUV data) as a 27MHz data stream; (This data stream is a '4:2:2' sampling scheme, where there are only chrominance values for every other luminance value).
  • This data was fed into a line-field decoder in order to find the line timing signals, signals embedded in the data through the use of reserved data words used as timing reference signals (TRS) (see International Telecommunication Union video standards ITU-R BT.656 and ITU-R BT.601).
  • TRS timing reference signals
  • the data stream was then converted from the 4:2:2 scheme to a 4:4:4 scheme by interpolating between the chrominance values, (this is shown in figure 13).
  • this stage is not required; however it is used should the system be extended to full-colour RGB operation (a colour space converted may also be used to change from YUV to RGB data).
  • the next stage was a de-interlacing stage.
  • the method chosen to de-interlace was 'Multiple Field Processing'.
  • the two fields (odd and even) were stored together in memory to form a single frame (sometimes referred to as 'weave'). This was achieved by having an address counter that stored the odd and even frames together.
  • This method of de-interlacing produced the highest resolution output picture, but sometimes had undesirable visual artifacts (double imaging) when the image had significant movement (for example, the image may have changed significantly after the odd field was sent, before the even field is sent).
  • Another alternative is to interpolate between the lines of each frame.
  • the FPGA supplied the triple video D/A converter (the FMS3815) with three channels of 8-bit data (decoded by the CRL Opto board into 24 sequential binary frames).
  • the CRL Opto display device had a native resolution of 1280 * 1024. Standard values for the sync timings and borders were chosen for this resolution, and a clock of 108MHz was used (hence the rest of the system was run at 108MHz for simplicity). As the data had been collated within the FPGA by the Output collater' module, the data had to be 'unpacked' before being sent to the FMS3815.
  • Figure 15a shows a holographic image display system incorporating a hardware accelerator 100 as described above.
  • the hardware accelerator 100 has an input 102 to receive image data, for example from a consumer electronic device defining an image to be displayed.
  • the hardware accelerator 100 drives SLM 24 to project a plurality of phase hologram sub-frames which combine to give the impression of displayed image 14 in the replay field (RPF).
  • RPF replay field
  • a laser diode 20 (for example, at 532nm), provides substantially collimated light 22 to a spatial light modulator 24 such as a pixeliated liquid crystal modulator.
  • the SLM 24 phase modulates light 22 with a hologram and the phase modulated light is provided to a demag ⁇ ifying optical system 26.
  • optical system 26 comprises a pair of lenses 28, 30 with respective focal lengths fj, f 2 , fi ⁇ f 2 , spaced apart at distance fi+f 2 .
  • Optical system 26 (which is not essential) increases the size of the projected holographic image by diverging the light forming the displayed image, as shown.
  • Lenses Ls and L 2 form the beam -expansion pair. This expands the beam from the light source so that it covers the whole surface of the modulator.
  • Lens pair L 3 and L 4 form a demagnification lens pair, in effect a demag ⁇ ifying telescope. This effectively reduces the pixel size of the modulator, thus increasing the diffraction angle. As a result, the image size increases.
  • the increase in image size is equal to the ratio of fj to U, which are the focal lengths of lenses L 3 and L 4 respectively.
  • a filter may also be included to filter out unwanted parts of the displayed image, for example a bright (zero order) undiffracted spot or a repeated first order or conjugate image, which may appear as an upside down version of the displayed image, depending upon how the hologram for displaying the image is generated.
  • one or more lenses may be encoded in the hologram, as described in UEC patent application GB 0606123.8 filed on 28 March 2006, hereby incorporated by reference in its entirety, allowing the size of the optical system to be reduced.
  • Figure 15b shows an example a consumer electronic device 10 incorporating a hardware projection module 12 as described above to project a displayed image 14.
  • holographic image display hardware which is configured to implement a procedure in which a two-dimensional image is generated using a plurality of holographlcally generated temporal subframes, the temporal subframes being displayed sequentially in time such that they are perceived as a single reduced-noise image.
  • OSPR One Step Phase Retrieval
  • OSPR-type procedures in which, strictly speaking, in some implementations it could be considered that more than one step is employed.
  • the holographic image display hardware we have described is also suitable for implementing these procedures, examples of which are described in GB0518912.1 filed 16 Sept 2005 and GB0601481.5 filed on 25 Jan 2006, both hereby incorporated by reference in their entirety.
  • phase-induced errors can be compensated by adjusting the target phase data for pixels of the image to compensate for the errors introduced. Preferably this is performed so that the desirable requirement of a substantially flat spatial spectrum is met.
  • holographic image display hardware include, but are not limited to, the following: mobile phone; PDA; laptop; digital camera; digital video camera; games console; in-car cinema; personal navigation systems (in-car or wristwatch GPS); head-up/helmet-mounted displays for automobiles or aviation; watch; personal media player (e.g. MP3 player, personal video player); dashboard mounted display; laser light show box; personal video projector (a "video iPod (RTM)"); advertising and signage systems; computer (including desktop); and a remote control unit.

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Abstract

La présente invention concerne l'accélération matérielle de système de traitement de signal afin d'afficher une image au moyen de techniques holographiques. Cette invention concerne un accélérateur matériel destiné à un système d'affichage d'image holographique, ce système d'affichage d'image étant agencé de façon à générer une image affichée utilisant une pluralité de sous trames temporelles générées de manière holographique, ces sous trames temporelles étant affichées séquentiellement dans le temps de sorte qu'elles soient perçues comme une image unique à bruit réduit, chaque sous trame étant générée de manière holographique par modulation d'un modulateur spatial de lumière avec des données holographiques de sorte que la relecture d'un hologramme défini par ces données holographiques définisse cette sous trame. Cet accélérateur matériel comprend un tampon d'entrée destiné à stocker des données image définissant l'image affichée, un tampon de sortie destiné à stocker des données holographiques d'une sous trame, au moins un module de traitement de donnée matériel couplé à ce tampon de données d'entrée et à ce tampon de données de sortie de façon à traiter ces données image afin de générer les données holographiques de cette sous trame et, un contrôleur couplé au module de traitement de données matériel de façon à commander ce module de traitement de données et fournir des données holographiques pour une pluralité des sous trames correspondant aux données image d'une seule image affichée au tampon de données sorties.
EP06755786A 2005-06-14 2006-06-13 Systeme de traitement de signal pour synthetiser des hologrammes Withdrawn EP1891485A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GBGB0511962.3A GB0511962D0 (en) 2005-06-14 2005-06-14 Signal processing systems
GB0512905A GB2429355B (en) 2005-06-14 2005-06-27 Signal processing systems
PCT/GB2006/050152 WO2006134398A2 (fr) 2005-06-14 2006-06-13 Systemes de traitement de signal

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EP1891485A2 true EP1891485A2 (fr) 2008-02-27

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WO (1) WO2006134398A2 (fr)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2436676B (en) * 2006-03-28 2008-02-20 Light Blue Optics Ltd Holographic display devices
GB2445958A (en) * 2007-01-24 2008-07-30 Light Blue Optics Ltd Holographic image display systems
GB2446852B (en) * 2007-02-12 2009-12-09 Light Blue Optics Ltd Data communication and processing system
GB0718633D0 (en) * 2007-05-16 2007-11-07 Seereal Technologies Sa Holograms
DE102007023740B4 (de) 2007-05-16 2009-04-09 Seereal Technologies S.A. Verfahren zur Generierung von Videohologrammen für eine holographische Wiedergabeeinrichtung mit wahlfreier Adressierung
ATE540339T1 (de) 2007-09-26 2012-01-15 Bae Systems Plc Verbesserungen in bezug auf das anzeigen eines holografischen bildes
GB2454246B (en) 2007-11-02 2010-03-10 Light Blue Optics Ltd Holographic image display systems
GB2456170B (en) 2008-01-07 2012-11-21 Light Blue Optics Ltd Holographic image display systems
GB2461894B (en) 2008-07-16 2010-06-23 Light Blue Optics Ltd Holographic image display systems
GB2466497B (en) 2008-12-24 2011-09-14 Light Blue Optics Ltd Touch sensitive holographic displays
GB0902468D0 (en) 2009-02-16 2009-04-01 Light Blue Optics Ltd Optical systems
GB2468911A (en) 2009-03-27 2010-09-29 Light Blue Optics Ltd Aberration correction methods using wavefront sensing hologram patches and mapping of phase aberration corrections
GB0907297D0 (en) 2009-04-29 2009-06-10 Light Blue Optics Ltd Dynamic backlighting
US20120224062A1 (en) 2009-08-07 2012-09-06 Light Blue Optics Ltd Head up displays
GB2555332B (en) 2010-11-22 2018-07-11 Dualitas Ltd Holographic systems
GB2485607B (en) 2010-11-22 2017-12-27 Daqri Holographics Ltd Spatial light modulators
US10168668B2 (en) 2016-12-21 2019-01-01 Vladimir Yankov Method of forming a rarefied hologram for video imaging and 3D lithography
GB2587400B (en) * 2019-09-27 2022-02-16 Dualitas Ltd Hologram display using a liquid crystal display device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992021050A1 (fr) * 1991-05-21 1992-11-26 Seiko Epson Corporation Dispositif optique et systeme d'usinage optique l'utilisant

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2006134398A3 *

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WO2006134398A2 (fr) 2006-12-21
WO2006134398A8 (fr) 2008-05-02
WO2006134398A3 (fr) 2007-02-08

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