Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/26—Systems using multi-frequency codes
  • H04L27/2601—Multicarrier modulation systems
  • H04L27/2614—Peak power aspects
  • H04L27/2623—Reduction thereof by clipping
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
  • H03F1/34—Negative-feedback-circuit arrangements with or without positive feedback
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
  • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
  • H03F3/191—Tuned amplifiers
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
  • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
  • H03F3/217—Class D power amplifiers; Switching amplifiers
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
  • H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
  • H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
  • H04B2201/70706—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation with means for reducing the peak-to-average power ratio

Definitions

• This invention relates in general to communication equipment, and more specifically to radio frequency power amplifiers.
• Radio-frequency power amplifiers are essential components of transmitters found in radio communication systems, and are deployed in various applications, such as mobile telephony, broadcast, wireless data networking, radiolocation and other fields. Generally, they function to make copies of their inputs, which are signals generated by other components of communication equipment, such as base transmitters, mobile devices, or the like, where the copies or output signals are powerful enough to propagate for appropriate distances. Two often conflicting requirements that constrain radio frequency power amplifiers are linearity and efficiency.
• the linearity requirement or constraint on a radio frequency power amplifier is that it reproduces the form of its input signal faithfully.
• Small distortions in the form of the output signal relative to the input can cause the radio frequency power amplifier output signal to interfere with other radio services, in violation of regulatory requirements, or make it difficult or impossible to receive/demodulate the signal accurately.
• These distortions may be caused, for example, by the fact that the characteristics of the components of which a radio frequency power amplifier is composed (e.g. transistors) are non-ideal, e.g., vary with the electrical currents that they carry, which necessarily include the signal being reproduced.
• a conventional method (“class A operation") of getting good linearity in this situation is to add a large "bias" current to signal currents so that current variations due to the signal are small in comparison.
• the efficiency requirement or constraint means that the amplifier should not consume excessive power relative to its desired output power: thus, for example, an amplifier required to produce 10 Watts of output power may typically consume 100 Watts. This is often caused by the use of large bias currents, as described above, to improve linearity.
• the power (90 Watts in the example) "wasted" in this way causes many problems. For example, the power dissipated is manifested as heat, which has to be removed - often with large heat sinks and fans - before it causes temperature rises that damage the amplifier or other circuits.
• equipment is battery-operated (e.g. in cell phones or in fixed installations (base transmitters) that are running on backup batteries during a power failure), battery size and hence weight and cost increases directly with power requirements.
• Relatively efficient power amplifier circuits are known, and for radio frequency power amplifiers one of the more efficient is known as type or class "E". These amplifiers attempt to operate their transistors as pure switches, which in principle dissipate (and hence waste) no power. Their operation depends on synchronization between closing the "switch” device and the "ringing" of a resonant load circuit, such that the switch is only driven closed at times when the voltage across it is almost zero.
• class E amplifiers pose problems. For example, since their output power is effectively set by a power supply voltage, they are difficult to amplitude-modulate and attempts to do so have resulted in both poor efficiency and poor linearity.
• class D Another switching power amplifier is known as class "D". This amplifier architecture has been used for audio-frequency applications. Class D amplifiers in theory have low power dissipation (e.g. a switch does not dissipate power). In practice, Class D amplifiers are continually discharging capacitance (e.g., when turned on) and this can amount to significant power dissipation at radio frequencies.
• Sigma delta technology is a known technique that allows feedback to be used to linearize, for example, class "D" switching amplifiers for audio-frequency use, but ordinarily this technology requires that switching events be synchronous to a fixed clock frequency.
• a sigma delta loop samples the output of a loop filter at a fixed rate that is independent of any input signal. This causes problems for class E radio frequency power amplifiers since their inputs need to be synchronized with a high frequency signal. Note that sigma delta and delta sigma are expressions that may be used interchangeably in this document.
• FIG. 1 depicts, in a simplified and representative form, a block diagram of a radio frequency power amplifier according to various exemplary embodiments
• FIG. 2 depicts, in a simplified and representative form, a more detailed block diagram of a radio frequency power amplifier according to one or more exemplary embodiments
• FIG. 5 shows a representative embodiment of a second feedback system suitable for use in one or more radio frequency power amplifiers in accordance with various exemplary embodiments
• FIG. 6 depicts a representative embodiment of an amplitude limiting and power recovery system in accordance with one or more exemplary embodiments
• FIG. 7 depicts a representative block diagram of a generalized second feedback system suitable for use in one or more radio frequency power amplifiers in accordance with various exemplary embodiments
• FIG. 8 through FIG. 19 show various representative waveforms resulting from an experimental simulation of a radio frequency power amplifier in accordance with the embodiment depicted in FIG. 3;
• FIG. 20 depicts, in a simplified and representative form, a block diagram of a loop filter suitable for use in one or more embodiments of a radio frequency power amplifier
• FIG. 21 depicts, in a simplified and representative form, a block diagram of another loop filter suitable for use in one or more embodiments of a radio frequency power amplifier
• FIG. 22 shows an exemplary state machine that represents an illustrative embodiment of a sequencer that may be used, for example, in FIG 1 through FIG. 4;
• FIG. 23 shows a further illustrative embodiment of a sequencer that may be used, for example, in FIG 1 through FIG. 4;
• FIG. 24 depicts a flow chart of a method of providing a radio frequency signal with complex modulation according to one or more embodiments.
• the present disclosure primarily concerns communication equipment including radio frequency transmitters or amplifiers such as used in infrastructure equipment including base stations or in communications units.
• radio frequency amplifiers for example, may be found in cellular, two-way, and the like radio networks or systems in the form of fixed or stationary and mobile equipment.
• the fixed equipment is often referred to as base stations or transmitters and the mobile equipment can be referred to as communication units, devices, handsets, or mobile stations.
• Such systems and equipment are normally used to support and provide services such as voice and data communication services to or for such communication units or users thereof.
• inventive concepts and principles are embodied in systems or constituent elements, communication units, transmitters and methods therein for providing or facilitating radio frequency amplifiers or power amplifiers with significant improvements in efficiency, linearity or signal to noise, and costs.
• costs include costs associated with size and operational issues.
• the improvements are associated, for example, with power supplies and heat management issues as impacted by improved efficiency.
• the improvements also are reflected in lower component or production costs since the concepts and principles allow less expensive components, such as smaller transistors, to be used for higher power levels.
• the radio frequency power amplifiers advantageously use a feedback control system employing in some embodiments a version of a delta sigma modulator as well as an amplitude limiting system and in some instances a second feedback system thereby advantageously yielding a practical and readily producible power amplifier provided such amplifiers are arranged and constructed in accordance with the concepts and principles discussed and disclosed herein.
• the communication systems and communication transmitters that are of particular interest are those that may employ some form of complex modulation and that may provide or facilitate voice communication services or data or messaging including video services over local area networks (LANs) or wide area networks (WANs), such as conventional two way systems and devices, various cellular phone systems including but not limited to, CDMA (code division multiple access) and variants thereof, GSM, GPRS (General Packet Radio System), 2.5G and 3G systems such as UMTS (Universal Mobile Telecommunication Service) systems, 4G OFDM (Orthogonal Frequency Division Multiplexed) systems, WiMax (IEEE 802.16), ETSI HiperMAN and variants or evolutions thereof.
• CDMA code division multiple access
• GSM Global System
• GPRS General Packet Radio System
• 2.5G and 3G systems such as UMTS (Universal Mobile Telecommunication Service) systems, 4G OFDM (Orthogonal Frequency Division Multiplexed) systems, WiMax (IEEE 802.16), ETSI HiperMAN and variants or evolution
• FIG. 1 through FIG. 4 illustrate various embodiments of radio frequency power amplifiers that are arranged and constructed and operate in an inventive manner.
• the inventors refer to this type of power amplifier as a class M power amplifier.
• These power amplifiers provide replication and amplification of an input signal that includes modulation, such as amplitude modulation, phase modulation or complex modulation (amplitude and phase modulation) in a linear and efficient manner.
• radio frequency power amplifiers utilize a novel arrangement of a switching stage driving resonant circuits, an amplitude limiting or clipper system for reducing or limiting peak voltages across the switching stage (and input to a feedback control loop) and a feedback control loop that operates to induce or control timing associated with switching of the switching stage so as to linearly replicate an input signal including complex modulation as applied to a resultant load or amplifier output signal and to encourage the switching at times when on average the voltage across the switching stage is at a minimum.
• a radio frequency switching stage so as to reproduce modulation with both good linearity and large degrees of amplitude modulation or complex modulation.
• the switching stage and some elements of the amplitude limiting or clipper system can be implemented in a high power density gallium arsenide, gallium nitride, silicon based power device, or the like process.
• a known high frequency submicron silicon based process may be advantageous.
• the radio frequency power amplifier 100 will typically operate at frequencies from tens of Mega Hertz (MHz) to multiple Giga Hertz (GHz) and is generally utilized to amplify an input signal to provide a higher power load output signal.
• the resonant load as will be further described herein below is comprised of a combination of inductive and capacitive elements (the resonant circuit) and a load (shown as R L 102).
• R L 102 may include, for example, a harmonic filter, isolators, circulators, antenna, cable, or the like, that is driven by the resultant output or load output signal.
• the radio frequency power amplifier 100 comprises a radio frequency switching stage 103 with an output 105 that is coupled to the resonant circuit 101 and configured to provide an output signal at output 105 with complex modulation, e.g., amplitude modulation (AM) and/or phase modulation (PM), corresponding to modulation of an input signal at input 107 when, for example, powered from a fixed voltage power supply, V DD 109, via, e.g., a feed choke or inductor 111.
• the FIG. 1 embodiment of the radio frequency power amplifier 100 further comprises a feedback control system 113 that is coupled to the input (thus input signal 107) and the output 105 (thus output signal or one or more variants thereof as a feedback signal).
• the feedback control system 113 is configured to provide a sequencer output at output 117 that is used to drive the radio frequency switching stage 103.
• the sequencer output can be provided by, e.g., a sequencer 115 that is included with the feedback control system 113.
• the sequencer output has at least one state, e.g., an OFF state, with a starting time or which begins at a variable time that is determined by the feedback control system 113.
• the feedback system 123 is coupled and responsive to the sequencer output at output 117 (alternatively referred to as sequencer output 117) and provides a second feedback signal at 125 that is coupled to the feedback control system 113 in varying embodiments as further described below.
• the sequencer output 117 will correspond to one or more of the output signal, the input signal, the second feedback signal, a combination of the output, input, and feedback signals, or the like as will be further discussed below.
• the amplitude control system or clipper system 127 is coupled to the output of the radio frequency switching stage or output signal 105 and configured to control or limit an amplitude of the output signal, e.g., to a constrained or maximum amplitude.
• the feedback signal corresponds to the output signal as limited, e.g., with the maximum or constrained amplitude.
• the output signal as limited is applied to the resonant circuit or resonant load.
• the maximum value of the output signal can be significantly decreased (e.g., by a factor of 2-3 is some instances) which helps protect the radio frequency switching stage or allows use of technologies for the switching stage with lower breakdown voltages.
• the required dynamic range of various circuits in the feedback control system 119 can be designed with lower dynamic ranges which often results in using less substrate area in integrated circuit embodiments and therefore lower costs.
• the radio frequency switching stage 103 may be implemented in various forms, however it may be particularly advantageous when the switching stage together with the resonant circuit 101 is arranged as a radio frequency power amplifier similar to a class E configuration or a class F configuration.
• the radio frequency power amplifier 100 of FIG. 1 and specifically the feedback control system 113 in one or more embodiments further comprises a loop filter 119.
• the loop filter 119 is responsive to the input signal and the output signal or first feedback signal via the inter coupling as shown and the loop filter is configured to provide a filtered signal at 121.
• the sequencer 115 is responsive directly or indirectly to the filtered signal at 121.
• a mixer arrangement can be employed to provide a first feedback signal, e.g., input signal to the filter, where the feedback signal corresponds to the output signal as down converted by the mixer arrangement and provide a sequencer input corresponding to the filtered signal, i.e., in some embodiments a combination of the input signal and the feedback signal, as up converted by the mixer arrangement.
• the second feedback signal can be directly combined with the filtered signal, or used as an additional input to the loop filter or may be used to affect or modify or otherwise change the filtered signal and thus impact the sequencer input and therefore sequencer output.
• the second feedback signal is combined with the filtered signal from the loop filter with the resultant signal used as the sequencer input.
• the second feedback signal is coupled to the input to the sequencer.
• the second feedback signal 125 uses the second feedback signal 125 to otherwise affect or modify the filtered signal from the loop filter 119, i.e., the second feedback signal can be one component of the input signal for the filter or can be coupled directly to some portion of the filter and thus affect the filtered signal.
• a radio frequency power amplifier 200 comprises as part of a feedback control system, a loop filter 201 with an input 203 coupled to a signal corresponding to an input signal 205 and a first feedback signal 207.
• the feedback signal 207 and the terminal or node where the feedback signal is found will alternatively be referred to by reference numeral 207.
• a combiner 216 (analog adder) that is coupled to an output terminal 208 and responsive to a filter output or filtered output signal from the loop filter 201 and a second feedback signal at 214 provided by a second feedback system 212, e.g., sequencer feedback.
• a sequencer 209 that is configured to provide a sequencer output at output 211.
• the sequencer output has at least one state, e.g., an OFF state, with a starting time that corresponds to the output signal from the combiner 216, i.e., filter output and second feedback signal as will be further discussed below.
• a radio frequency switching stage 213 that is driven by the sequencer output and configured to provide an output signal at 215.
• the switching stage is supplied DC (direct current) power from a constant voltage source V DD 220 via a feed choke or inductor 217.
• the output signal is coupled to an amplitude limiter or clipper circuit that is configured similarly to FIG. 1 to limit or constrain an amplitude of the output signal.
• the clipper circuit or system in one or more embodiments can comprise a diode array 232 comprising one or more diodes with the anode(s) coupled to the output signal and the cathode(s) coupled to a voltage source 233, e.g., battery or other DC supply that can sink current where the voltage source has or maintains a reference voltage or clip voltage that with this arrangement corresponds to a maximum amplitude of the output signal.
• a voltage source 233 e.g., battery or other DC supply that can sink current where the voltage source has or maintains a reference voltage or clip voltage that with this arrangement corresponds to a maximum amplitude of the output signal.
• the maximum amplitude would equal the reference voltage of the voltage source, however the currents involved and impedance as well as various parasitics of the diode(s) etc. and characteristic voltage drops will result in some difference between the reference voltage and the maximum amplitude of the output signal.
• the voltage source 233 e.g., battery, may be used for or as
• the output signal is coupled via an attenuator 218 back to be combined with the input signal at summer 219.
• the feedback signal 207 corresponds to the output signal 215 as limited or clipped.
• the summer 219 provides the signal at 203 to the loop filter 201, i.e., the signal coupled to the input of the loop filter can be an error signal corresponding to an algebraic combination of the input signal and the feedback signal.
• the radio frequency switching stage in one or more embodiments is a field effect transistor (FET or JFET) but may also be a bipolar transistor or the like.
• the FET or JFET is formed using known GaAs (gallium arsenide), GaN (gallium nitride), LDMOS (Laterally Diffused Metal Oxide Semiconductor) process technology as noted earlier. It can be advantageous for various reasons (parasitics, similar breakdown voltage requirements, etc.) to form the diode array 232 in the same technologies as the switching stage(s). Note that while the switching stage is shown as one transistor a plurality of transistors may be used essentially in parallel to perform the switching function. Note also that appropriate circuitry, such as additional gain stages will be needed, either as part of the sequencer or switching stage in order to insure that the switching stage is properly driven.
• GaAs gallium arsenide
• GaN gallium nitride
• LDMOS Layer Diffused Metal Oxide Semiconductor
• the output signal at 215 is applied to a resonant circuit 221 and via the resonant circuit 221 to a load 223.
• a diode (catch or snub diode) 225 Placed across the switching stage 213 is a diode (catch or snub diode) 225 that is configured and operates to clamp the output signal to a voltage that is non- negative, i.e., essentially at ground potential.
• diode 225 may be a parasitic diode, e.g., source to substrate diode or the like for the switch 213, or the switch itself may turn on or be turned on when the voltage at 215 is at or below ground.
• the resonant circuit 221 includes a series resonant inductor capacitor pair 227 that couples the output signal as filtered by the series resonant pair 227 to the load 223. Across or in parallel with the load is a parallel resonant inductor capacitor pair 229. Further included in the resonant circuit 221 is a capacitor 231 that is coupled in parallel with the switching stage 213. Those of ordinary skill will appreciate that the capacitor 231 will include at least a parasitic capacitance of switching stage 213 and depending on the particular embodiment the capacitor 231 may only include this and other parasitic capacitance.
• switching stage 213 and others in other figures
• the switching stage and the resonant circuit can be arranged in or similar to a class F configuration.
• Alternative embodiments of the switching stage and the resonant circuit can be arranged in a known class E configuration (for example, eliminate the parallel inductor capacitor pair 229).
• Other architectures for class F or class E exist and may also be utilized.
• Class E and F power amplifiers while taking advantage of the open or short circuit zero power dissipation characteristics also recognize that in practice the switching stage takes a finite time period to change between these states and if both voltage and current are non-zero during the time period between states, power will be dissipated.
• Such power amplifier architectures attempt to avoid dissipating energy stored in the parasitic capacitance (at least part of capacitor 231) of the switching device or stage by insuring this energy is provided to or comes from the resonant circuit, e.g., resonant circuit 221, rather than being dissipated in the switching device 213.
• resonant circuit e.g., resonant circuit 221
• these configurations strive to perform switching between states (ON/OFF) during those times when the voltage of the output signal, i.e., signal across the switching device, is ideally zero volts and furthermore if possible when the derivative of this voltage is also zero, i.e. switching currents will also be zero.
• the radio frequency switching stage can be configured to switch ON responsive to the sequencer output so that over a multitude of switch ON events an average voltage, e.g., root mean square of the voltages, imposed on the resonant load and across the switching stage at the switch ON event is less than Vi, typically less than 1/4 and often less than 1/10 of a maximum voltage imposed on the resonant load, e.g., in practice a voltage approaching the specified breakdown voltage associated with the radio frequency switching stage.
• an average voltage e.g., root mean square of the voltages
• the radio frequency power amplifier 300 includes a loop filter 301 (normally nth order band pass filter in this embodiment) with an input 303 coupled to a signal corresponding to an input signal 305 and a feedback signal 307. Further included is a summer or combiner 316 and a sequencer 309 where the combiner is responsive to a second feedback signal at 314 from a feedback system, e.g. sequencer feedback 312, and a filter output, e.g., via output/input 308, from the loop filter 301 or loop filter output signal.
• a feedback system e.g. sequencer feedback 312
• a filter output e.g., via output/input 308, from the loop filter 301 or loop filter output signal.
• the sequencer 309 is configured to provide a sequencer output at output 311, where the sequencer output has an OFF state with a starting time that corresponds to the filter output signal and the second feedback signal (i.e., there is a defined relationship between the filter output signal plus second feedback signal and operation of the sequencer and thus sequencer output). Additionally included is a radio frequency switching stage 313 driven by the sequencer output and configured to provide an output signal at output 315 that is coupled via the attenuator 318 to the summer 319.
• the feedback signal 307 corresponds to the output signal as amplitude limited or clipped.
• the OFF state corresponds specifically to switching stage 313 being opened or in a high impedance state, i.e., OFF state.
• the D flip flop When the capacitor has charged to the Reset threshold of the D flip flop 331 at a time determined by the RC time constant of resistor 341 and capacitor 339, the D flip flop will be reset and the Q bar output will go high, the switch 337 will be closed holding the Reset input at a low potential, and the sequencer will thus provide the sequencer output at 311 in an ON state (switching stage 313 is ON) after a time lapse determined by the Reset signal (in this embodiment the RC time constant) for the D flip flop.
• This sequencer 309 is often referred to as an edge triggered one shot.
• a time lapse on the order of a half cycle of the radio frequency carrier can be an appropriate time duration for the OFF state, e.g., at 1000 MHz, approx 0.5 nanosecond.
• the sequencer 309 will again provide an output in the OFF state.
• the switching stage is an open circuit, i.e., stage is turned OFF, and the resonant circuit 321 may be charging up through the feed inductor 317 or the inductor capacitor pair may be charging up capacitor 331 thus causing a positive going pulse in the output signal at 315.
• the OFF state for the switching device can be approximately -2 volts while the ON state can be between 0 and 0.5 volts.
• the sequencer and various driver stages will need to be fashioned to provide the appropriate drive signal to the switching stage(s).
• an appropriate sequencer operates in an asynchronous manner, i.e. there is no clock as in conventional architectures. Note that for reasonable efficiency when reproducing input signals it is necessary that the sequencer output produce a drive signal for the class E/F amplifier that is compatible with its requirements, e.g., switching at or near zero voltage, etc.
• the sequencer 309 (and 209, 115) should, in embodiments where efficiency is desired, be configured to provide the sequencer output with a second state, e.g., ON state, that has a starting time corresponding to, e.g., at or near to or on average at or near to, a voltage minimum for the output signal as will become more evident with the review of the simulation waveforms below.
• a second state e.g., ON state
• the sequencer can be configured to provide the sequencer output in the OFF state when the filter output as modified by or in accordance with the second feedback signal 314 corresponds to a predetermined state (the clock level for the D flip flop) and to provide the sequencer output in the ON state after a time lapse that is variable and that corresponds to the minimum time duration starting at the last occurrence of the predetermined state.
• the sequencer is configured to provide the sequencer output asynchronously, i.e., the sequencer is clocked by the combiner output, i.e., loop filter output as modified by the second feedback signal or the control loop may be viewed as self clocked. Note that the sequencer may also be viewed as clocked by various signals, e.g. the output signal (drain voltage) as that ultimately determines the filter output signal, for a given input signal.
• an envelope detector monitors the input signal and when an envelope level of around 20% of the peak envelope is detected, the envelope detector or functionality responsive thereto will operate a switch.
• the switch would add an additional capacitor in parallel with capacitor 339. If the additional capacitor had a capacitance that was, e.g., 2 times that of capacitor 339, the time constant would be about 3 times the initial time constant and this would extend the OFF state to approximately 3 times the original. The net result is the duty cycle of the switching stage is reduced when signal levels are low, the current in the feed inductor is reduced, and this ultimately results in reducing power consumption of the switching stage.
• the radio frequency power amplifier 400 includes in addition to the sequencer 409 (similar to, e.g., sequencer 309), switching stage 313, resonant circuit 321, attenuator 318, etc., a mixer arrangement 401 and a feedback network or system 419.
• the sequencer 409, switching stage 313, resonant circuit 321, attenuator 318, etc. operate in accordance with previously discussed principles and concepts although they may be adjusted, etc. to accommodate the particulars associated with the embodiment of FIG. 4.
• the radio frequency power amplifier 400 of FIG. 4 is arranged and constructed to receive an input signal 403 at a base band frequency, such as zero hertz or another intermediate frequency that is typically relatively low compared to the carrier frequency of the signal that is to be transmitted, frequency translate or up convert the input signal to a carrier frequency and amplify the resultant up converted signal to provide an output signal that is filtered and coupled as a resultant signal to the load 323.
• the output signal will be at the carrier frequency and will include modulation corresponding to the input signal.
• the input signal 403 is a complex signal with I (in phase) and Q (quadrature) components where the double lines in FIG. 4 are used to denote complex signals having I and Q components.
• the mixer arrangement 401 includes linear I/Q mixers 405, 407 (e.g., Gilbert cell arrangements) and is configured to provide the feedback signal 409, where the feedback signal corresponds to the output signal at 315 as frequency translated or down converted to the frequency of the input signal by the mixer arrangement or more specifically mixer 405. Note that under appropriate circumstances mixers other than Gilbert cells can be used.
• the feedback signal 409 is combined with the input signal 403 in the summer 411 with the resultant complex signal coupled to a loop filter 413.
• the complex conversion is a multiple mixer complex conversion providing two outputs coupled to two inputs of the filter so as to provide image rejection without undue delay as discussed in Section 9 of a University of Toronto, Department of Electrical Engineering Doctoral Thesis titled Intermediate Function Synthesis, authored by Snelgrove in December 1981, hereby incorporated herein.
• the mixer arrangement further provides a. sequencer input at input 432 that corresponds to the filter output or output signal from the loop filter 413 as frequency translated or up converted by the mixer arrangement 401, specifically mixer 407 to the carrier frequency, and as modified in accordance with the second feedback signal at 420.
• the complex signal components (I or Q) from mixer 407 is needed to drive the sequencer or alternatively a combiner 421.
• the Q or imaginary component or alternatively the I or real component can be utilized; however the sequencer could be driven by a complex signal.
• Use of the complex signal may help in that, e.g., error-signal envelop information is readily available.
• the sequencer input or input signal corresponds to a combination of the input signal and the feedback signal as filtered and up converted.
• the mixer arrangement may be viewed as part of the feedback control system of FIG. 1.
• the loop filter may be advantageously implemented as a low pass filter and when the input signal is centered at another, e.g., intermediate, frequency the loop filter is normally implemented as a band pass filter centered at the intermediate frequency. Since the filter is handling complex signals both the I and Q component will need to be filtered prior to presentation to the mixer 407. In either situation the loop filter is configured to filter the combination of the input signal and the feedback signal.
• Using the mixer arrangement while adding an apparent level of complexity, allows the loop filter to be implemented at a lower frequency and thus may allow for a more exacting or higher precision loop filter to be implemented/provided at lower costs.
• Using frequency translation in the feedback control system allows the input signal to be presented at base band and thus may eliminate the frequency translation at some other place in a typical transmitter lineup.
• the mixer arrangement in addition to the mixers 405, 407 includes a local oscillator 415 that provides a local oscillator signal at a frequency equal to the carrier plus or minus the center frequency of the input signal.
• a local oscillator 415 that provides a local oscillator signal at a frequency equal to the carrier plus or minus the center frequency of the input signal.
• the local oscillator signal is coupled to both mixers, however the signal coupled to mixer 407 is time-shifted or phase delayed by the phase shifter 417.
• the phase shifter 417 in some embodiments delays the oscillator signal to mixer 407 by approximately one-quarter cycle (at the carrier frequency) and forms the conjugate phase (the sign of the gain for the Q channel in the down conversion mixer 405 is opposite to the sign for the Q channel in the up conversion mixer 407) for the oscillator signal applied to the mixer 407 as compared to the signal applied to the mixer 405.
• the time shift can be selected or adjusted to compensate for time delays in the feedback control system or loop or otherwise improve performance results in parameters such as signal to noise, linearity (noise plus distortion), stability, or the like.
• the second feedback signal can also be used in a further embodiment to modify or change the output signal (frequency translated loop filter output signal) from mixer 407 by coupling the second feedback signal 420 to combiner 421 where it is added to the output of the mixer 407 with the combiner then providing an input signal to the sequencer 409.
• the latter approach for affecting the signal at the input to the sequencer is similar to the approaches discussed with reference to, e.g., FIG. 2-3.
• the radio frequency power amplifier of FIG. 4 includes a feedback control system (401, 411, 413, 409) coupled to a signal corresponding to an input signal 403 and a first feedback signal 409 which is configured to provide a sequencer output at 410.
• a feedback control system (401, 411, 413, 409) coupled to a signal corresponding to an input signal 403 and a first feedback signal 409 which is configured to provide a sequencer output at 410.
• Time domain simulations of the radio frequency power amplifier 400 of FIG. 4 have been conducted using PC based circuit design and simulation software.
• the system that was simulated produced a modulated output signal nominally centered at 100 MHz and processed an information signal comprised of 4 sinusoids arbitrarily spaced across a bandwidth of 1.25 MHz.
• the 4 sinusoid information signal is representative of the system processing an arbitrary wideband signal having a 6 dB peak-to-average power ratio.
• the switching stage 313 was a GaAs FET having a 9 mm gate width, and V DD 316 was set to 12 volts.
• signal-to-noise ratio, output load power efficiency and absolute output load power was optimized by changing component values in an iterative manner through the application of electrical engineering principles.
• a signal-to-noise ratio of approximately 5OdB over a 1.25 MHz bandwidth, a power efficiency of 27% and an output load in band signal power of 3.8 Watts was achieved by setting the respective components to the values noted below.
• the element values were; a feed inductor 317 of 100 nH (nano-henrys), a capacitor 331 of 100 pF (pico-farads), a series resonant inductor capacitor pair 321 of 11 nH and 250 pF, respectively, and a load 323 of 3 Ohms.
• the second feedback system 527 as well as the feedback systems 123, 212, 312, 419 of FIG. 1 - FIG. 4 and can be implemented in various manners.
• the second feedback system comprises a feedback network coupled from the sequencer output to the sequencer input via the combiner 545.
• the second feedback system 527 comprises one or more delay stages with outputs coupled to a corresponding one or more gain stages with each of the gain stages having an output, where the second feedback signal corresponds to a combination of the signal at the output of each of the one or more gain stages. More specifically FIG. 5 shows a delay stage 531 that is coupled to and responsive to the sequencer output 511 and operates to present a delayed version of the sequencer output to gain stage 533.
• the output of delay stage 531 in alternative embodiments can be coupled to a further delay stage 535 with the output of that delay stage 535 coupled to a corresponding gain stage 537.
• the basic architecture of delay stages and gain stages can be repeated if desired as indicated by the dotted lines 543.
• the one or more delay stages i.e., delay stage 531, 535, etc., may advantageously be implemented as a tapped delay line with each tap coupled, respectively, to a different one of the one or more gain stages, i.e., gain stage 533, 537, etc.
• the delay stages can be implemented as a series coupled array of logic gates or buffers with each buffer or gate adding a characteristic delay. For example in one embodiment, a series coupled group of sixteen buffers has been used for the delay stage. [070] The output of the gain stages 533, 537, etc. are added together via one or more adders or combiners 539, 541, etc. to provide the second feedback signal at 544.
• the output of gain stage 533 is the second feedback signal and this signal can be coupled directly to combiner 545.
• the feedback system or network 527 and others can take many forms, however normally at least one and often all of the one or more delay stages and at least one and often all of the corresponding one or more gain stages is operating asynchronously or continuously in the time domain rather than in a clocked mode, i.e., the output is a function of the input for any instant in time.
• Other gain stages or delay stages may operate in a discrete time mode (i.e., output is a function of input at discrete times as determined by a clock).
• the delay stages essentially provide a memory function in that a second feedback signal is representative of the sequencer output at some past instant (the amount of the delay) in time.
• FIG. 5 also illustrates another embodiment of a radio frequency power amplifier that can provide appropriate performance results in some situations.
• This embodiment includes a biasing system 547 that is configured to couple an offset signal (VO F F SET ) to the input of the sequencer, resulting in the sequencer output changing states in accordance with the offset signal and the filter output signal.
• the biasing system or V OFFSET can be used in lieu of or in addition to the second feedback system.
• a typical value for V OFFSET that has been simulated with reasonable results in one power amplifier system is 10% of the rms voltage at the filter output 508.
• the delay stages add a delay around one half cycle, e.g., ranging from .25 to .75 cycle at the carrier frequency, e.g., at 1000 MHz - approximately 0.25 to 0.75 nano-second (ns) of delay for each delay stage.
• the gain of the gain stages are typically fractional values that will vary depending, e.g., on the typical output level of the loop filter as well as output level of the delay stages.
• a typical value for the first gain stage 533 can be 0.1 ranging from 0.05 to 0.35, and can be either positive or negative (180 degree phase shift).
• Some embodiments perform well when gain stage 533 is a negative value (180 degree phase shift), e.g., -0.1, and gain stage 537 is a positive value, e.g., 0.1, with alternating stages negative and positive. It can be expected that for any particular implementation, these values will need to be experimentally optimized to account for various factors such as other loop delays within the power amplifier as well as other factors, e.g.
• An alternative embodiment (not specifically shown) of a second feedback system suitable for use in one or more radio frequency power amplifiers in accordance with various exemplary embodiments includes one or more parallel networks where each of the parallel networks is a series coupled delay stage and gain stage. Each of the delay stages is coupled to the sequencer output signal at 511 and thus each of the delay stages couples a delayed version of the sequencer output to a corresponding gain stage. The output from the gain stage, either alone or together with other gain stage outputs, is the second feedback signal at 544. This structure can be repeated as needed with the outputs from all gain stages combined via summers or combiners, etc. to provide the second feedback signal at 544.
• FIG. 6 a representative embodiment of an amplitude limiting or control (clipper) and power recovery system 600 in accordance with one or more exemplary embodiments will be discussed and described.
• the amplitude control or limiting system of FIG. 6 is coupled to the output signal 315, e.g., output of the radio frequency stage, and configured to limit an amplitude of the output signal.
• the amplitude control or clipper system includes one or more diodes 351 coupled from the output signal to a load or a voltage or reference voltage across the capacitor 353 or at an input 601 of power recovery system 355.
• the reference voltage or load establishes or corresponds to a maximum amplitude or upper value for the amplitude of the output signal.
• the diode(s) 351 or diode array and their in circuit disposal or physical placement need to present minimal inductance from the switching device drain to the diode or this inductance must be otherwise tuned out in order to insure protection for the switching device in terms of breakdown voltages across the device.
• the diode should have low self impedance at frequencies of interest, i.e. low inductance and low series resistance in order to provide effective amplitude limiting or control.
• the diode will need reasonably fast, relative to the radio frequency, recovery characteristics when switching from a forward to reverse biased state.
• the diode should have low parasitic capacitance and demonstrate limited change in that capacitance when switching from a forward to reverse bias conditions, although again some of this capacitance or change in capacitance can be tuned out or otherwise compensated for with the resonant load characteristics.
• the capacitor 353 needs to have good high frequency characteristics (low impedance).
• the capacitor 353 is normally in parallel with a much larger capacitor at the input of the DC to DC converter 603 and thus energy stored on capacitor 353 by pulses at the radio frequency will flow to this larger capacitance.
• the power recovery system 355 includes in various embodiments, DC to DC converter 603 which is configured to provide output power, e.g., a portion of the DC power for the radio frequency switching stage or power amplifier at V DD 356 or Vs 358.
• the DC to DC converter 603 can be a known Buck regulator arranged for down conversion of the input voltage at 605 or in some embodiments a synchronized version (typical Buck regulator diode replaced with a switch and corresponding control logic to synchronize this switch with the conventional switch), with the output section of this regulator replaced with a current source 607 in one or more generally known configurations.
• the DC to DC converter 603 supplies an output current at 609, when enabled via enable signal at 611 as provided by enabling circuitry 610.
• the enabling circuitry is configured to enable the DC to DC converter when a comparison of the voltage at 601 and a reference voltage at 615 satisfies a known condition, e.g., the voltage at 601 exceeds the reference voltage at 615, as determined by comparator 613.
• a known condition e.g., the voltage at 601 exceeds the reference voltage at 615, as determined by comparator 613.
• the reference voltage at 615 can be provided via a resistor divider coupled to V DD or any other convenient DC voltage and the voltage at the positive input of the comparator can be provided by a resistor divider coupled to 601 where the various resistors are selected to set the reference voltage and the voltage at the positive input of the comparator and thus the corresponding voltage at 601 (i.e. upper value of amplitude or maximum amplitude for the output signal).
• One further aspect of the power recovery system 355 or one or more embodiments of the DC to DC converter is the electronic switch 617.
• the electronic switch allows the power recovery system to be isolated from the voltages V DD or Vs (which ever is coupled to the output) when the power recovery system is not supplying any power, i.e., when not enabled or if enabled until the DC to DC converter has ramped up sufficiently and current 609 is available.
• the electronic switch 617 basically compares the voltage at the output of the DC to DC converter to the voltage V DD or Vs and when the voltage at the output of the converter exceeds the destination supply voltage (VD D or Vs) the switch is closed and the current flows to the destination.
• the loop filter is coupled to a signal corresponding to the input signal and the first feedback signal, e.g., sum of these signals from summer 519, and the feedback signal corresponds to the output signal 515 as reduced by attenuator 518.
• the output signal 515 is provided by a switching stage 513 and this signal is coupled to the load 521.
• the sequencer drives the switching stage.
• a second feedback system that provides one or more second feedback signals with one provided by feedback network 703 which is coupled to combiner 545 and thus to the sequencer input and another provided by feedback network 707 which is coupled at 709 to summer 519 and thus the input to the loop filter 701 or at 711 to the loop filter 701.
• the second feedback system 727 specifically one or more of feedback networks 703, 707 includes one or more of a discrete time portion, a continuous time portion, and a memory portion (portion where present output is affected at least in part by a previous input). Note that only one of the feedback networks needs to be present in some embodiments, e.g., feedback network 703 in various of the above discussed embodiments where the feedback system is coupled to the sequencer input.
• the input signal is similar to that found for example, in code division multiple access (CDMA) systems, such as wideband CDMA systems.
• FIG. 9 shows the same input signal over the first 200 nano seconds (200 nsec) where again the AM modulation is clearly evident.
• FIG. 10 shows a 20 nsec portion of the input signal where the carrier signal (approximately 875 MHz) is evident, as well as AM or PM modulation.
• FIG. 11 - FIG. 18 show the waveforms observed at various points in the radio frequency amplifier for the same 20 ns time period. [084]
• FIG. 11 shows the feedback signal 207 over the 20 ns time period. This feedback signal corresponds to the output signal at 215 with a delay equal to one cycle at the radio frequency carrier, i.e.
• Each of the pulses arises or occurs when the sequencer 209 enters the OFF state and the switching stage 213 becomes an open circuit.
• the feed inductor 217, capacitor 231 (some or all of which may be parasitic capacitance of switching stage 213 or parasitic capacitance of diode array 232) and resonant circuit 221 as well as the charge states (conditions when time OFF state starts) for each of the elements determine the particular form of the respective pulses.
• the pulses end when the sequencer enters the ON state and the switching device becomes a short circuit.
• the input signal and the feedback signal are combined in the summer 219 and yield the waveform of FIG. 12. Note that the waveform of FIG. 12 is essentially the difference between the input and the feedback signals. This is the waveform that is input to the loop filter at input 203.
• the loop filter is typically a bandpass filter in the FIG. 2 power amplifier embodiment as earlier noted and as will be further described below.
• the output of the loop filter is shown in FIG. 13.
• the waveform of FIG. 13 is coupled to the combiner 216 at input 208 along with the second feedback signal, shown in FIG. 14, from the second feedback system 212.
• the second feedback system used in these simulations included a single delay stage with slightly less than T/2 delay (at 875 MHz approx. 0.57 ns where the delay used was approx. 0.5 ns) and a single gain stage with an approximate gain setting of -0.1. These signals are added together to provide the combiner output signal, i.e., input signal for the sequencer 209 shown in FIG. 15.
• the discontinuities observed in the FIG. 15 waveform is the result of adding the second feedback signal (essentially a two state signal ignoring nonzero switching times) to the filter output signal.
• the sequencer output signal at 211 is shown in FIG. 16.
• the sequencer output signal is a quantized signal that in this embodiment, ignoring small non-zero switching times, includes an OFF state (sequencer output signal is low at -1 volts and switching stage 213 is essentially an open circuit or OFF) and additionally an ON state (sequencer output signal is high at 1 volts and switching stage is essentially a short circuit or ON), with each state occurring multiple times.
• rising edges (zero crossings) 1501 in FIG 15 result in the sequencer entering the OFF state 1601 (three occurrences specifically labeled 1601).
• the OFF state in the particular sequencer embodiment see 309 in FIG. 3) with the output signal shown in FIG.
• sequencer output includes an OFF state that begins at a variable time that corresponds to the combiner output in FIG. 15 (filter output as modified in accordance with the second feedback signal) or corresponds to the output signal (see FIG. 17 as further described below).
• rising edges e.g., 1503, 1505, etc.
• the sequencer retrigger the sequencer and result in extending the duration of the OFF state.
• the OFF state can be extended by the length of time between the two or more (in one instance 3, i.e., 1501, 1502, 1503) successive rising edges. Similar circumstances in the sequencer input result in the extended OFF state 1607.
• the frequency of occurrence of the OFF state varies from one time period or frame to another as readily observed from FIG. 16 and also varies from the frequency of the input signal (see FIG. 10).
• the second feedback system and signal is provided and deployed to cause the OFF state to begin earlier with the second feedback signal than without the second feedback signal in some instances. Furthermore, the second feedback system and signal is provided and deployed to cause the OFF state to begin later with the second feedback signal than without the second feedback signal in various instances.
• the second feedback system and signal are deployed and operate to over steer the sequencer output in the sense that long (using a T/2 reference length) duration ON states are longer due to the second feedback signal and correspondingly the variable time associated with the beginning of an OFF state is delayed due to the second feedback signal than either would have been without the second feedback signal.
• the second feedback system and signal further operates to over steer the sequencer output in the sense that short (using the T/2 reference length) duration ON states are shorter and correspondingly the variable time associated with the beginning of an OFF state is advanced due to the second feedback signal than either would have been without the second feedback signal.
• FIG. 17 shows the output signal at 215, i.e., at the drain of the switching stage 213, that results given the sequencer output signal of FIG. 16, etc.
• pulses e.g., 1701
• the amplitudes of some of the pulses are limited to approximately 30 volts (i.e., 2.5 - 3 times a VD D ) and this is due to the clipper or amplitude limiting or control system as described and discussed above.
• pulses reaching amplitudes of 5 to 7 times V DD - Pulses end or are terminated whenever the sequencer starts or initiates an ON state, e.g., 1703 (see 1609), and the switching stage becomes a short circuit, although some end long before that (see pulse at 7 ns).
• the ON state is normally initiated at a starting time that corresponds to a voltage minimum in the output signal. For example, pulses 1705 are terminated near a voltage minimum and for these pulses as readily observed near or shortly before/after the voltage minimum.
• pulses 1706 and others are terminated near a voltage minimum and for these pulses near zero volts across the switching stage.
• pulses are abruptly terminated, e.g., 1707, however the majority of the pulses are terminated at or near a voltage minimum and on average near 0 volts across the switching stage.
• the output signal can include multiple pulses 1709 (indicating ringing in the resonant load).
• a comparison of the feedback signal in FIG. 11 with the output signal in FIG. 17 shows a factor of 10 attenuation in the amplitude of the feedback signal as well as a delay of approximately one cycle at the carrier frequency.
• FIG. 18 shows a waveform of the voltage across the load 223 that results from the output waveform of FIG. 17 with peak amplitudes approaching 6 or so volts.
• This waveform includes significant amounts of essentially switching or quantization noise as well as 2 nd and higher order harmonics that may be readily removed with an appropriate harmonic filter, e.g. a band pass radio frequency filter, before applying the resultant signal to an antenna or cable or the like.
• an appropriate harmonic filter e.g. a band pass radio frequency filter
• class F or class E power amplifiers will note that normally these stages are designed to and typically will switch at near zero volts (pulses 1701) across the switching stage, thereby minimizing power dissipation in the switching stage.
• class F or class E in order to consistently switch near zero volts have to provide near a maximum output power given the voltage supply, VD D , for the switching stage and other design values, i.e. class E and class F are not normally capable of AM modulation or PM modulation of more than very small deviations without degrading either efficiency or linearity and typically both.
• the class E amplifier is driven to replicate AM and PM modulation on the input signal, e.g.
• the switching stage when driven by the sequencer in the feedback control system may turn the switching device ON at a point that is not close to a voltage minimum for a particular pulse in order to provide near optimum turn on times for many successive pulses.
• efficiency will be near an optimum value given that AM and PM modulation is being imposed on a carrier signal by a class E or class F or the like power amplifier.
• FIG. 19 shows a close in frequency spectrum of the waveform of FIG. 18 which results when a second feedback system (one delay and one gain stage) and the amplitude limiting or clipping systems as discussed and described above is used with the resultant spectra 1903 depicted as a darker line.
• This spectrum is centered at a frequency near 875 MHz and shows desired sidebands 1905 clearly indicative of AM and PM modulation components as well as the undesirable quantization noise, etc. Note that in band, the quantization noise, etc is down by more than 60 dB in the 10 MHz bandwidth centered at the carrier frequency.
• This spectra is compared to another spectra of a corresponding waveform where the amplitude limiting system is not utilized with this comparison spectra 1901 depicted with a lighter line.
• significant improvement in in-band (near carrier) noise or undesirable energy components 1909 for spectra 1901 as compared to 1907 for spectra 1903 have been realized with the use of the amplitude control or limiting system.
• Quantitative measurements with the amplitude limiting or control system showed a total signal to noise level over the 10 MHz band to be approximately 52 dB whereas without the amplitude limiting the total signal to noise was 45 dB.
• Efficiency with the amplitude limiting system was approximately 23% and approximately 24% without the amplitude limiting system with an output signal power of approximately 6 watts.
• sequencer will depend on a multitude of factors including the switching stage, feed inductor, resonant circuit(s) amplitude control or clipping system, feedback path(s) and loop filter gain and phase parameters.
• the sequencer should be implemented such that given all of the other parameters the sequencer output is provided in the proper state and at the proper time and for the proper time duration to cause the switching stage to turn ON or OFF so as to generate an output signal that when fed back and combined with the input signal will drive the output of the loop filter toward zero. This may be referred to as generating a counter phase or opposing phase loop filter output.
• the particular implementation of the second feedback system will depend on other factors and elements in the radio frequency power amplifier and feedback control system and specifically various delays therein.
• the second feedback system will have less inherent loop delay than the feedback control system in combination with the switching stage. This fact or observation can be used to "predict" what will occur with the switching stage and the like and compensate for undesirable aspects thereof. For example, in the simulations discussed above the second feedback signal resulting from a given sequencer output arrives at or begins to affect the input to the sequencer at least T/2 seconds before the output signal and resultant feedback signal begins to have an impact on the sequencer input.
• FIG. 20 a block diagram of a loop filter suitable for use in one or more embodiments of a radio frequency power amplifier will be discussed and described. The loop filter of FIG.
• the filter 20 is a known transconductance capacitor (gm-C) filter that is shown in a generalized form, i.e., the filter can be a low pass or band pass filter depending on the selection for gains Al, A2 2001, 2003. For example, if Al is set to unity (1) and A2 to zero (0) a band pass filter results. As shown the filter has two inputs, namely the feedback signal 2005 and input signal 2007 (analogous, e.g., to output signal at 105, 215, 315 and input signal 107, 205, 305, etc). Note that the filter of FIG. 20 is also acting as the summer in FIG. 2 - FIG. 5, etc.
• Gm-C transconductance capacitor
• the roll off characteristic on either side of the center frequency is 20 dB per decade.
• this filter may be frequency scaled to any value of interest (carrier frequency or intermediate frequency) according to known techniques, e.g. increasing the capacitor values will lower the center frequency.
• the values of Al and A2 can be selected/adjusted to tune and optimize the system performance of the radio frequency power amplifier and thus account for circuit parasitics and various other non-idealities.
• a fourth order filter may be used in embodiments of a radio frequency power amplifier with a non-DC centered input signal, where the filter has a transfer function of the form:
• this filter has a resonant or center frequency of 0.5 Hz but may be frequency scaled in accordance with known techniques. While this filter is known to work appropriately, there are various other appropriate filter transfer functions.
• a low pass filter will normally be used. This may be comprised of single integrator stages, one for a real (I) path and one for an imaginary (Q) path. Higher order filters may also be used, such as the filter depicted in FIG. 21. Recalling the discussion of FIG. 4, the loop filter needs to filter a complex signal and thus includes a real path 2101 and an imaginary path 2103.
• "Init” 2201 is the start state. From that state, the output switch or switching stage is immediately turned “On” 2203. The machine starts in the "On” state so the choke feed inductor that is supplying the output transistor can charge up. The machine stays in the "On” state in some embodiments for at least some minimum time “onMin” in order to avoid small glitches and thus avoid possible issues with the life expectancy of the switching stage and various drivers. In this embodiment the machine stays in the "On” state until a threshold level of current, e.g. "iTrigger", is flowing through the switch.
• a threshold level of current e.g. "iTrigger
• the state machine waits for the loop filter plus second feedback signal or system to say go, i.e., waits for an initiating signal from the loop filter, etc., ⁇ "filtwt" 2205 (filter wait). If the loop filter with second feedback system says “go” (i.e. makes a transition to a positive value) while we're still seeing positive switch current (meaning that the pulse will go positive if the switching stage is opened), then open the switching stage, i.e., go to state "Off” 2207. Note that once the switching stage is turned off actual output power starts to be generated, i.e. applied to the resonant circuit and thus load.
• FIG. 23 an alternative embodiment of a sequencer 2300 that provides a sequencer output at 2301 asynchronously when synchronously clocked, e.g., from a fixed clock 2303.
• the clock 2303 is shown as toggling for example, at 8 times the carrier frequency for an output signal from the corresponding radio frequency power amplifier.
• the sequencer 2300 may be arranged to generate a plurality of output signals or sequencer outputs with each one having a different and corresponding time profile (e.g., starting and ending time for an OFF state).
• the sequencer output is used to drive a switching stage 2305, such as the switching stage in one of FIG. 1 through FIG. 4 or the like.
• the cross-coupled NOR gates 2315 functionally operate as an RS flip-flop.
• a "1" out of the zero crossing detector (inverter 2311) forces its upper output, i.e. sequencer output at 2301 to "0", i.e. the OFF state, which results in a) turning OFF the RF switching stage 2305 and thus causing a pulse to start and b) starts the one-shot counting.
• the one-shot 2317 is a binary down counter that can be preloaded, e.g. with 011 (JO, Jl). When the RF switch is "ON”, this counter is preloaded to "011 ", i.e. 3 counts plus one delay at a rate of 8x carrier, hence one half-cycle of the carrier.
• the feedback control system 113 of FIG. 1 may be implemented in the discrete time domain using digital signal processing techniques and appropriate continuous to digital and digital to continuous conversion processes at the relevant interfaces.
• sequencer can select from a plurality of sequencer outputs using interpolation. For example by noting the filter output and possible earlier or intermediate results from the filter (e.g., prior to last integrator) at a clock time or at sequential clock times (the clock having a frequency similar to the carrier frequency), an estimate of the filter output in the recent past and near future can be made and thus one of the plurality of pulses can be selected, e.g. from a look up table, to provide the OFF state or ON state with an appropriate time profile, i.e. a starting time and ending time.
• the plurality of pulses would be selected such that each varied from the other by a few degrees and thus the appropriate resolution over a carrier period required to control the switching stage would be provided.
• the method 2400 is a method of providing a radio frequency signal with complex modulation (AM, PM, or AM & PM), e.g.
• an amplified version of an input signal with the same modulation begins at 2401 with providing an input signal including complex modulation (AM/PM modulation) at base band (BB), an intermediate frequency (IF) or radio frequency (RF).
• BB base band
• IF intermediate frequency
• RF radio frequency
• the method includes filtering the combination of the input signal and the feedback signal 2405 to provide a filtered signal, where the filtering is done with a low pass filter if the combination signal is a base band signal and ordinarily with a bandpass filter if the signal is centered at an IF or RF (carrier) frequency.
• the optional process 2407 can be used to up convert or frequency translate the filtered signal when that signal is at BB or IF.
• 2425 shows adding a second feedback signal discussed below to the filtered signal.
• 2409 shows generating, responsive to the filtered signal plus second feedback signal, a quantized signal having an OFF state, ON state, etc. where the OFF state begins at a variable time, e.g., that corresponds to the filtered signal plus second feedback signal.
• the generating the quantized signal can be directly responsive to the second feedback signal.
• 2423 shows providing, responsive to the quantized signal, a second feedback signal having, e.g. appropriate gains and delays, and deployed to affect the generating the quantized signal.
• the second feedback signal can as depicted be added to the filtered signal at 2425 and thus affect or modify the filtered signal with the resultant signal used to trigger the generating the quantized signal.
• the second feedback signal can be coupled at 2427 to the up conversion process and used, e.g., to vary a phase shift of a local oscillator, and thus a phase of the filtered signal as up converted or frequency translated with the resultant signal used to trigger generating the quantized signal.
• the providing the second feedback signal in some embodiments comprises forming one or more delayed and weighted versions of the quantized signal and combining the one or more delayed and weighted versions of the quantized signal to provide the second feedback signal.
• the forming and the combining in some embodiments comprises forming and combining continuously and asynchronously at least a portion of the one or more delayed and weighted versions of the quantized signal.
• the providing the second feedback signal can include providing one or more second feedback signals using one or more of a discrete time process, a continuous time process, and a process with memory.
• the second feedback signal is deployed to cause the OFF state to begin either earlier or later with the second feedback signal than without the second feedback signal.
• the output signal as amplitude limited or clipped is level adjusted 2413 and optionally down converted in a base band system 2415 and used to provide the first feedback signal at BB, IF, or RF 2417 to the combining process at 2403.
• the output signal comprises an amplified version of the input signal with the complex modulation, i.e., the radio frequency signal with the complex modulation.
• the first feedback signal corresponds to the output signal as clipped or amplitude limited as level adjusted and in some instances frequency converted.
• the output signal is filtered 2419 with typically a band pass filter and then output 2421 to a load (antenna, cable, etc.) as a radio frequency signal with modulation.
• Generating the quantized signal can include generating a quantized signal having a second state, where the second state starts at a time near a voltage minimum for the output signal.
• the quantized signal can further comprise an OFF state having a minimum time duration and an ON state having a variable time duration.
• the limiting an amplitude of the output signal 2412 can include coupling the output signal to a voltage source through one or more diodes, where the voltage source establishes an upper value for the amplitude of the output signal.
• the recovering power 2414 corresponds to the limiting the amplitude of the output signal, in that the power recovered is the power included in the higher level pulses.
• the recovering power further can include regulating a voltage using a DC to DC converter having an input coupled to the voltage and an output configured to provide a portion of DC power for the radio frequency switching stage, where the voltage that is regulated corresponds to an upper value for the amplitude of the output signal (see discussion referring to FIG. 6).
• the recovering power can further include enabling the DC to DC converter when the voltage compared to a reference voltage satisfies a known condition, e.g., voltage exceeds the reference voltage. Note that the power recovering can be disabled or isolated from the destination for the recovered power whenever no power is being recovered.
• One of the principles used is to control switching times given the switching stage, accompanying resonant load, and specifics of a radio frequency signal with complex modulation, such that on average the switching occurs at or near a voltage minimum across the switching stage.
• Using the amplitude limiting or clipping techniques as above described is beneficial in protecting switching stages, lowers dynamic range requirements for some elements, increases output power for a given level of breakdown voltage in the switching devices and with the power recovery techniques maintains or improves efficiency, and improves signal to noise (linearity).
• the use of the second feedback system and signal as variously noted above allows for longer loop delays in the radio frequency power amplifier while improving or at least maintaining satisfactory signal to noise (linearity) and efficiency and additionally has provided a surprising improvement in signal to noise and efficiency even without loop delay.

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