EP1872634B1 - Electronic reactive current oscillation-reducing ballast - Google Patents

Description

Technical area

The present invention relates to an electronic ballast having an input capacitance with a step-up converter for operating a discharge lamp, for example a low-pressure discharge lamp on a phase-gating dimmer having a built-in or parasitic inductance.

State of the art

Electronic ballasts for the operation of discharge lamps are known in many designs. I.d.R. They include a rectifier circuit for rectifying an AC power supply and charging a capacitor often referred to as a DC link capacitor. The voltage applied to this capacitor DC voltage is used to supply an inverter or inverter (hereinafter inverter), which operates the discharge lamp. Basically, an inverter from a rectified AC power supply or a DC power supply generates a supply voltage for the lamp to be operated with high-frequency current. Similar devices are also known for other lamp types, for example in the form of electronic transformers for halogen lamps.

Step-up converter circuits can be used for power line harmonic reduction of discharge lamps. Step-up converters have a storage inductor, a switching element, a diode and an intermediate circuit capacitor. The DC link capacitor supplies, for example, a low-pressure discharge lamp via an inverter circuit.

Such a boost converter operates as follows: The AC line voltage is converted in a rectifier into a pulsating DC voltage. Between the supply potential of this pulsating DC voltage and the DC link capacitor, the storage inductor and the diode is connected. When switched on, the switching element ensures an increasing current flow in the storage choke up to an adjustable value, the switch-off current threshold. After switching off the switching element, the diode conducts the current impressed in the storage inductor into the intermediate circuit capacitor.

The use of a boost converter in a ballast for a discharge lamp is in the EP 1 465 330 A2 described.

Phase control dimmers for power control are also known. Phase gating dimmers provide a periodic mains supply to the load. In each half-cycle, the mains supply is delivered to the load only after a settable time.

Frequently, phase gating dimmers, as a switching element controlling the current flow from a supply network to a load, include a triac. With such a switching element, it is possible to allow a current flow from the network to the load from an adjustable time within a network half-wave. At the output of the phase gating dimmer is a voltage available, which is zero in a first time interval, namely in the phase gating, and in a second time interval substantially equal to the input voltage of the dimmer.

To avoid radio interference, many phase gating dimmers include an inductor connected in series with the switching element. In addition, even if no corresponding component is installed in the dimmer, a parasitic inductance can occur between the phase gating dimmer and the capacitive load, for example caused by line inductances. Any Reference to an "inductance in the phase gating dimmer" is to be understood in the following text in this sense.

Presentation of the invention

The invention is based on the technical problem of providing an improved electronic ballast for dimmable discharge lamps with regard to the operating behavior.

The invention relates to an electronic ballast with a switching element and an input capacitance having boost converter for operation on a supply serially acting inductor having phase control dimmer, characterized in that within a power half wave the operating parameters of the boost converter during the demagnetization of the inductance in the phase gating dimmer, in time Completion of the phase angle, be adjusted so that, compared with the operation of the boost converter after the demagnetization of the inductance of the dimmer, a temporarily increased current flows through the boost converter.

Preferred embodiments of the invention are specified in the dependent claims and are explained in more detail below. The disclosure always refers to both the process category and the device category of the invention.

Electronic ballasts for operating discharge lamps often have an effective input capacitance. The invention is based on the consideration that the effective input capacitance of the electronic ballast together with the serially acting inductance of the phase gating dimmer to form a resonant circuit and an overshoot of the voltage across the input capacitance can occur. Such voltage oscillations may affect the performance of electronic ballasts for discharge lamps when operating on a phase gating dimmer.

Specifically, following the phase gating, the switching element is brought into a conductive state in the phase gating dimmer; then the input capacitance of the ballast is charged to the instantaneous value of the supply voltage. This charging of the input capacitance via the inductance of the phase gating dimmer, which determines the increase of the current. The voltage across the input capacitance initially reaches the instantaneous value of the supply voltage, but then goes beyond that. This is done because the inductance in the phase gating dimmer now demagnetizes and maintains a current flow in the original current direction. If the inductance in the phase gating dimmer is demagnetized and the voltage across the input capacitance is greater than the applied supply voltage, then no mains current flows through the ballast until the overvoltage at the input capacitor has been dissipated by discharging.

The triacs often used as switching elements in phase gated dimmers require a certain holding current, i. if they are brought into a conductive state, a minimum current is needed to maintain the conductivity. If this is missing, the triac locks again. If there is no current flowing through the phase gating dimmer for a short time, the triac may transition from the conducting to the blocking state. The reactive current oscillations described above can cause such mains power interruptions.

The interruption of the mains current can be prevented. For this purpose, during the demagnetization of the inductance in the phase gating dimmer, a temporarily increased current is passed through the step-up converter, ie within a time interval defined by the demagnetization. The word "while" is to be understood throughout this text in this sense. This current discharges the input capacitance and the voltage across it again drops to the level of the instantaneous value of the supply voltage. This input capacitance discharging current must be large enough be to reduce the voltage over the input capacitance before the inductance in the phase gating dimmer is completely demagnetized.

A step-up converter can be operated in various operating modes, with a distinction in particular between the discontinuous operation and the continuous operation. Often boost converters are operated continuously in discontinuous mode. This means that the switching element in the boost converter is only turned on when the storage inductor of the boost converter is completely demagnetized and no current flows through them. Switching losses are minimal in this mode of operation.

If the switch-on element in the boost converter is not maintained until the storage choke is completely demagnetized, then this is called continuous operation. The switching element is therefore turned on when falling below a threshold for the current through the storage inductor - the inrush current threshold. This inrush current threshold can be of different magnitude and take on a different value in each cycle of the boost converter.

In a preferred embodiment of the invention, the step-up converter is operated during the demagnetization of the inductance in the phase gating dimmer with temporarily increased inrush current thresholds, compared to the operation of the step-up converter following the demagnetization of the inductance in the phase gating dimmer. As a result, the current flow through the boost converter during this period can be significantly increased. Although the switching losses in the boost converter temporarily increase as a result of this measure, these losses are not high, averaged over the network half-wave.

In the simplest case, this may mean that during the demagnetization of the inductance in the phase gating dimmer, the boost converter in the continuous Operation and after this period, immediately or delayed, goes into discontinuous operation.

However, the above embodiment of the invention also includes, in particular, the case that following the demagnetization of the inductance in the phase gating dimmer, it is not switched to the discontinuous operation of the boost converter, but remains in the boost converter in a continuous operation with lower inrush current thresholds of the switching element.

In a further preferred embodiment of the invention, in particular in combination with the above measures, the Abschaltstromschwelle the switching element of the boost converter during the demagnetization of the inductance of the phase gating dimmer increases. Even with this measure, as an alternative or in addition to continuous operation, the current flow through the boost converter can be significantly increased.

Preferably, during the magnetization of the inductance in the phase gating dimmer, the current flowing through the step-up converter is reduced or even prevented. Thus, no or only a small current discharging the input capacitance can flow. As a result, the magnetization of the inductance in the phase gating dimmer and thus the energy stored in it can be reduced to a minimum. The less energy stored in the inductance of the phase gating dimmer, the lower the voltage overshoot is over the input capacitance.

In another preferred embodiment of the above aspect of the invention, the current flowing through the boost converter during magnetization of the inductance in the phase gating dimmer is reduced by setting the turn-off current threshold of the boost converter small compared to operation of the boost converter following the magnetization of the inductor in the dimmer , As a result, the boost converter takes a smaller amplitude stream; The average current flowing through the inductance of the phase gating dimmer can thus be set very small, or even negligible.

In a further preferred embodiment, however, the turn-off current threshold, starting from no or a small current through the switching element during the magnetization of the inductance in the phase gating dimmer then increases, so that the current absorbed by the step-up converter increases from switching cycle to switching cycle of the boost converter. For example, the switch-off threshold of the boost converter at the end of the magnetization of the inductance in the phase gating dimmer can reach the increased switch-off threshold for the time following the magnetization of the inductance. By gradually increasing the turn-off current threshold, load current oscillations can be reduced.

In an alternative, likewise preferred embodiment, the switching element of the boost converter is permanently disabled during the magnetization of the inductance. Thus no current discharging the input capacitance can flow.

A preferred embodiment of the invention has a circuit arrangement for metrological detection of the completion of the phase gating, the beginning of the demagnetization of the inductance in the phase gating dimmer and the completion of the demagnetization of the same inductance. These three times determine the two relevant time intervals within which embodiments of the invention work to reduce the voltage overshoot across the input capacitance. Between the completion of the phase control and the time at which the voltage across the input capacitance reaches the instantaneous value of the supply voltage, the inductance in the phase gating dimmer is magnetized; From this point on it will be demagnetized.

The circuit arrangement preferably consists of a series connection of two differentiators, which may for example be connected in parallel to the input capacitance. The output voltage of the second differentiator corresponds to the second derivative of the voltage across the input capacitance and has the property that it has a different sign during the magnetization of the inductance in the phase gating dimmer than during the demagnetization of the same inductance. Thus, the two relevant time intervals are determined and the output signal of the second differentiator can be used to set the operating parameters of the boost converter. The output voltage of the second differentiator can be converted via two threshold elements into signals corresponding to the logic states zero and one. If the output voltage of the second differentiator has the first sign, then the output signal of the first threshold element is logically one, the same applies to the second threshold element and the time in which a voltage of the other sign is present at the output of the second differentiator. Preferably, these threshold elements are Schmitt triggers.

Typically, the voltage across the input capacitance is superimposed by the boost converter function, a high-frequency, relatively low AC voltage. These high-frequency vibrations are decoupled from the first differentiator, a second differentiation may not provide a meaningful result. A preferred embodiment of the invention therefore provides a peak detection circuit. By means of peak detection, the first derivative of the voltage across the input capacitance is smoothed. The quality of a subsequent differentiation increases with it.

The circuit arrangements just described for determining the relevant time intervals in principle perform a metrological detection of the waveform of the voltage across the input capacitance. Therefore, you can These circuits reliably determine the relevant time intervals under different circumstances. These circuits can be used for various combinations of input capacitance and inductance of the phase gating dimmer, as they measure the course of the voltage across the input capacitance and therefore no assumptions about the input capacitance, the inductance of the phase gating dimmer or the course of the voltage across the input capacitance following the phase gating include.

The inventors have found that the values of the inductances of the dimmers available on the market are in a comparatively small range. Furthermore, the voltage overshoot across the input capacitance can also be limited by supplementary measures (see below and claims 14 ff.). If the voltage overshoot above the input capacitance is not so pronounced, the relevant time intervals after the phase gating also do not vary so much.

In these cases, a metrological detection of the waveform of the voltage across the input capacitance is not necessarily required.

In a preferred embodiment of the invention, the electronic ballast on a threshold value for detecting the completion of the phase gating and a first timer, which provides a first fixed time and is set by the threshold value element following the phase gating.

For this purpose, the threshold element about the rectified AC power supply, optionally via a voltage divider, are supplied. During the phase control, the output signal of the threshold element can correspond to logic zero, while it jumps to logic one directly after the phase control. Through this jump, the first timer can be set, which is for a constant predetermined time, the holding time, remains set. After that it can reset itself independently. The predetermined hold time of the timer can be determined by averaging over one of the relevant time intervals, which takes into account as many dimmers available on the market as possible. The input capacitance of the electronic ballast containing this circuit is known to the manufacturer and can be considered accordingly in the hold time of the first timer.

The first timer can predetermine a time corresponding at most to the duration of the magnetization of the inductance in the phase gating dimmer following the phase gating. This corresponds to the time when the supply voltage is greater than the voltage across the input capacitance. If this time has expired, according to the invention, a temporarily increased current can be passed through the step-up converter. In addition, the operating parameters of the boost converter can of course also be set so that during the magnetization of the inductance in the phase gating dimmer very little current is passed through the boost converter.

Preferably, the electronic ballast on two timers. Both timers can be set by the same threshold element following the phase gating, but have different hold times. In this way, for example, by means of an AND operation three relevant for the operation of the electronic ballast time intervals can be specified.

Preferably, the first fixed time interval of the first timer begins with the end of the phase gating and lasts at most until the end of the magnetization of the inductance in the phase gating dimmer. The second fixed time interval of the second timer also begins with the end of the phase gating and lasts at least until complete reduction of the voltage overshoot across the input capacitance.

By ANDing the first and second fixed time intervals, a time interval which begins with the end of the first time interval and ends with the end of the second time interval can be defined. Ideally, this interval begins with the end of the magnetization of the inductance in the phase gating dimmer and ends after complete removal of the overvoltage across the input capacitance.

Preferably, the threshold elements are Schmitt triggers.

Preferably, when using an operating mode of the boost converter with increased inrush current of the switching element in Hochsetzsteiler - during the demagnetization of the inductance in the phase gating dimmer - the transition to subsequent operation with lower inrush current thresholds carried out slowly. This means that the inrush current thresholds of the switching element distributed in the boost converter become smaller over some current consumption cycles of the boost converter. As a result, further load current oscillations can be reduced.

Up to this point is described how reactive current oscillations can be reduced by means of an adjustment of the time profile of the current through the boost converter. As an additional measure according to the invention, reactive current oscillations can be reduced by suitably charging or discharging the input capacitance before the end of the phase gating, and thus additionally the current charging the inductance in the phase gating dimmer can be reduced quantitatively. A ballast, which realizes both possibilities of reactive current reduction, attenuates reactive current oscillations more effectively.

The voltage overshoots are particularly pronounced when the voltage across the input capacitance following the phase gating is significantly less than the instantaneous value of the supply voltage. Here and in the following text is the "instantaneous value of the supply voltage following the phase control ", it should be understood that the supply voltage across the ballast or above the phase gating dimmer has already fully built up.

If the voltage across the input capacitance at this time is greater than the instantaneous value of the supply voltage, no current flows through the dimmer until the input capacitance is discharged by a current through the load so that its voltage corresponds to the instantaneous value of the supply voltage. During this time, however, the switching element in the phase gating dimmer can turn off.

In operation, therefore, both cases should be avoided.

The greater the difference between the supply voltage of the ballast and the voltage across the input capacitance of the ballast at the end of the phase control, the more voltage drops across the inductance of the dimmer. The current flowing during the magnetization of the inductance of the dimmer increases as long as the voltage across the input capacitance is less than the supply voltage at the load.

A reduction of this difference at the beginning of the inductance magnetization in the dimmer reduces the initial voltage across it. Thus, respective reactive currents which magnetize the inductance and cause voltage overshoot across the input capacitance are further reduced.

For this purpose, the input capacitance is charged to a value which corresponds at most to the instantaneous value of the supply voltage at the end of the phase control by a charging process (charging or discharging) before the end of the phase control of a mains half-wave. However, the voltage across the input capacitance should not be the value of the supply voltage at this time exceed, otherwise no continuous mains current can be guaranteed.

The instantaneous value of the supply voltage at the end of the phase control within a system half-cycle is not known in advance. Preferably, therefore, the invention in this embodiment has a memory device for storing a prognosis value for the supply voltage at the time of the end of the phase gating, which was obtained from one or more preceding network half-waves. Below, preferred implementations of such a storage device are presented. The prediction value of the instantaneous value of the supply voltage at the end of the phase control can then be used in a following system half-cycle to actively charge or discharge the input capacitance such that the voltage above the input capacitance at most assumes the stored value.

Preferably, the invention has a device for storing an instantaneous value of the supply voltage at the end of the phase control of one or more preceding network half-waves. However, the instantaneous value of the supply voltage at the end of the phase gating of a preceding mains half-wave does not have to be identical to the instantaneous value of the supply voltage at the end of the phase gating of a following mains half-wave - it is rather a forecast for the supply voltage value, as explained in the previous paragraph.

If the network half-wave in which a value has been stored does not yet have too many network half-waves, it can be assumed that the stored value for the current network half-wave is very similar. This is the case because changes in the phase angle between successive line half-waves usually take place slowly. Reactive current oscillations are reduced most effectively when the input capacitance is charged exactly to the value of the supply voltage at the end of the phase gating. However, to be sure that the voltage across the input capacitance is not greater than the supply voltage at the end of the phase gating, the input capacitance is charged to a value slightly less than the stored predictive value.

In practice, it has proven useful to set the voltage across the input capacitance to about 90-95% of the supply voltage at the end of the phase control. But even with values from 50% can already be worked.

In a preferred embodiment of the invention, the prognosis value of the supply voltage following the phase gating is newly stored in each network half-wave and used in the respectively following network half-wave.

The memory device preferably stores the instantaneous value of the supply voltage within a time window after the completion of the phase control. In a preferred embodiment of the invention, a peak detection circuit is used for this purpose. The time window can be used for charging a capacitor, for example, but is very short compared to the sinusoidal supply voltage.

The time window is preferably set to open and close within a time interval beginning with the gating of the phase gating dimmer and ending with the voltage across the input capacitance reaching the value of the instantaneous supply voltage. This excludes in particular the case that a value is stored which is greater than the supply voltage when switching on the dimmer.

When applying the supply voltage to the dimmer and the lamp for the first time, a reactive current oscillation can not be ruled out, as no prognosis value has yet been stored. After a few half waves, however, a stable state is reached.

In a preferred embodiment of the invention, the length of the time window is determined by a monoflop. This is set by a signal from a control circuit of the electronic ballast and resets after a given time back. For example, the incipient current flow through the storage choke of the boost converter can trigger the setting of the monoflop. The monoflop defines the time window for the storage of the instantaneous value of the supply voltage at the end of the phase control, for example by means of a switch controlled by the monoflop.

The time window is specified in a further preferred embodiment by means of a differentiator of a capacitor and a resistor. The differentiator is addressed by an edge of a signal from a control circuit of the ballast. As a result of the flank occurs across the resistance of the differentiator on a voltage jump followed by an exponential decay. The time constant of the exponential decay is determined by the size of the resistor and the capacitor in the differentiator. The exponential decay defines the time window for the storage of the instantaneous value of the supply voltage.

A further preferred embodiment for determining a time window and for storing a prognosis value of the supply voltage at the end of the phase gating is based on the following relationship: At the time of the end of the magnetization of the inductance in the dimmer, the instantaneous value of the voltage across the input capacitance corresponds to the instantaneous value of the supply voltage. Since the end of the phase control, the supply voltage has barely changed, then corresponds to the voltage across the input capacitance about the instantaneous value of the supply voltage at the end of the phase control. The time of the end of the magnetization of the inductance in the dimmer corresponds to the zero crossing of the second derivative of the voltage across the input capacitance of the ballast and is easy to determine, if necessary, to estimate (as in the embodiments following FIG. 12 described). In this case, one can store as a prediction value, the voltage across the input capacitance of the ballast at this time.

Preferably, an embodiment comprises a comparison device. This compares the value from the memory device with the current value of the voltage across the input capacitance. Before the end of the phase control, the comparison device controls the control circuit of the boost converter, which then discharges the input capacitance accordingly. For example, if the voltage across the input capacitance is greater than the stored value, the input capacitance is discharged. In the exemplary embodiment, it is described more concretely how the output signal of the comparison device can contribute to the control of the charging process of the input capacitance.

Preferably, the input capacitance is discharged via activation of the boost converter prior to completion of the phase gating.

Preferably, the input capacitance is charged by the DC link capacitor. For this purpose, a diode connected between the supply potential-side terminals of the intermediate circuit capacitor and the input capacitance can be bridged with a resistor. There are types of boost converters that have multiple switched between the supply potential side terminals of the link capacitor and the input capacitance Having diodes; here one or more diodes can be bridged.

To load the input capacitance to the value stored in the memory device, control is required. If such is not to be added specifically, then first the input capacitance of the link capacitor can be charged so much that the voltage across the input capacitance is in any case too high. The boost converter can then be activated in order to discharge the input capacitance to the desired value (at most the forecast value).

The above and the following description of the individual features relate to the electronic ballast and to a discharge lamp with an integrated electronic ballast according to the invention. Further, it relates to the individual features on a method according to the invention for operating an electronic ballast. This also applies without being explicitly mentioned in detail.

The invention thus also relates, in principle, to a method for operating an electronic ballast having a step-up converter having a switching element and an input capacitance on a phase-leading dimmer which has a serially acting inductance, characterized in that the operating parameters of the step-up converter during demagnetization are within one half-wave Inductance in the phase gating dimmer, temporally after the completion of the phase gating, be adjusted so that, compared with the operation of the boost converter after the demagnetization of the inductance, a temporarily increased current flows through the boost converter.

Brief description of the drawings

Figur 1

zeigt schematisch einen Hochsetzsteller als Teil eines elektronischen Vorschaltgerätes mit einem vorgeschalte- ten Phasenanschnittdimmer.

Figur 2

zeigt schematisch für ein elektronisches Vorschaltgerät nach dem Stand der Technik die Versorgungsspannung UIN, die Spannung über einer Eingangskapazität einer Last UC, den Netzstrom IN und den mittleren durch den Hochsetzsteller fließenden Strom ILH. Es sind drei rele- vante Zeitintervalle T1, T2, T3 eingetragen.

Figur 3

zeigt schematisch für ein elektronisches Vorschaltgerät mit einer ersten Vorrichtung zur Blindstromschwingungs- reduzierung die Versorgungsspannung UIN, die Span- nung über der Eingangskapazität der Last UC, den Netz- strom IN und den mittleren durch den Hochsetzsteller fließenden Strom ILH. Es sind zwei relevante Zeitinter- valle T1, T2 eingetragen.

Figur 4

zeigt eine erste Schaltungsanordnung zu einer Figur 3 entsprechenden Blindstromschwingungsreduzierung.

Figur 5

zeigt relevante Spannungsverläufe der Schaltungsan- ordnung aus Figur 4.

Figur 6

zeigt eine zweite Schaltungsanordnung zu einer Figur 3 entsprechenden Blindstromschwingungsreduzierung.

Figur 7

zeigt eine dritte Schaltungsanordnung zu einer Figur 3 entsprechenden Blindstromreduzierung.

Figur 8

zeigt relevante Signalverläufe der Schaltungsanordnung aus Figur 7.

Figur 9

zeigt schematisch für ein elektronisches Vorschaltgerät nach dem Stand der Technik die Versorgungsspannung UIN, die Spannung UC über einer Eingangskapazität C der Last, die Spannung UL über einer Induktivität des Dimmers und den Netzstrom IN. Es sind drei relevante Zeitintervalle T1, T2, T3 eingetragen.

Figuren 10 a, b

zeigen schematisch einen Verlauf der Spannung UC ü- ber der Eingangskapazität C beim Entladen bzw. Laden der Eingangskapazität C und die Versorgungsspannung UIN.

Figur 11

zeigt schematisch für ein elektronisches Vorschaltgerät mit einer zweiten Vorrichtung zur Blindstromschwin- gungsreduzierung die Versorgungsspannung UIN, die Spannung UC über der Eingangskapazität C der Last, die Spannung UL über der Induktivität des Dimmers und den Netzstrom IN. Wieder sind drei relevante Zeitinter- valle T1, T2, T3 eingetragen.

Figur 12 a

zeigt eine Schaltungsanordnung zur Speicherung von Prognosewerten und zum Vergleich eines Prognosewer- tes mit der Spannung UC über der Eingangskapazität C.

Figur 12 b

zeigt eine Variation der Schaltungsanordnung aus Figur 12 a.

Figur 13

zeigt eine Variation der Schaltungsanordnung aus Figur 1.

In the following, the invention will be explained in more detail with reference to exemplary embodiments. The individual features disclosed may also be essential to the invention in other combinations. The above and following description refers to the device category and the method category of the invention, although not explicitly mentioned in detail.

FIG. 1

schematically shows a step-up converter as part of an electronic ballast with an upstream Phasenanschnittimmer dimmer.

FIG. 2

shows schematically for a electronic ballast according to the prior art, the supply voltage UIN, the voltage across an input capacitance of a load UC, the mains current IN and the average flowing through the boost converter current ILH. There are three relevant time intervals T1, T2, T3 entered.

FIG. 3

schematically shows for an electronic ballast with a first device for reactive current oscillation reduction, the supply voltage UIN, the voltage across the input capacitance of the load UC, the mains current IN and the average flowing through the boost converter current ILH. Two relevant time intervals T1, T2 are entered.

FIG. 4

shows a first circuit arrangement to a FIG. 3 corresponding reactive current oscillation reduction.

FIG. 5

shows relevant voltage curves of the circuit arrangement FIG. 4 ,

FIG. 6

shows a second circuit arrangement to a FIG. 3 corresponding reactive current oscillation reduction.

FIG. 7

shows a third circuit arrangement to a FIG. 3 corresponding reactive current reduction.

FIG. 8

shows relevant waveforms of the circuit arrangement FIG. 7 ,

FIG. 9

shows schematically for a electronic ballast according to the prior art, the supply voltage UIN, the voltage UC across an input capacitance C of the load, the voltage UL across an inductance of the dimmer and the mains current IN. There are three relevant time intervals T1, T2, T3 entered.

FIGS. 10 a, b

schematically show a profile of the voltage UC over the input capacitance C when discharging or charging the input capacitance C and the supply voltage UIN.

FIG. 11

schematically shows for an electronic ballast with a second device for reactive current oscillation reduction, the supply voltage UIN, the voltage UC across the input capacitance C of the load, the voltage UL across the inductance of the dimmer and the mains current IN. Again, three relevant time intervals T1, T2, T3 are entered.

Figure 12 a

shows a circuit arrangement for storing prognosis values and for comparing a prognosis value with the voltage UC over the input capacitance C.

FIG. 12b

shows a variation of the circuit arrangement FIG. 12 a.

FIG. 13

shows a variation of the circuit arrangement FIG. 1 ,

Preferred embodiment of the invention

FIG. 1 schematically shows a Hochsetzstetter as part of an electronic ballast of a compact fluorescent lamp CFL.

The electronic ballast upstream of a phase gating dimmer DIM. This has a series circuit of a triac TR and an inductance LP. This series circuit is connected in series in an AC supply line of the electronic ballast. Another AC supply line is passed through the phase gating dimmer DIM. If the triac TR is switched through, then a supply voltage UIN is present between a node between the triac TR and the inductance LP and the other AC voltage supply line. The outputs of the phase gating dimmer DIM are connected to the inputs of a rectifier GL of the electronic ballast.

The boost converter is formed by a capacitor C, a DC link capacitor CH, a diode DH, a storage inductor LH and a switching element SH, here a MOSFET.

Usually, boost converters also include a control circuit not shown here for driving the switching element SH. For example, a control circuit as in the EP 1 465 330 A2 can be used described.

The DC link capacitor CH is charged via the rectifier GL via the storage inductor LH and the diode DH. The DC link capacitor supplies, for example, a compact fluorescent lamp CFL via an inverter circuit INV.

The circuit operates as follows: The AC line voltage is converted in the rectifier GL in a pulsating DC voltage. Parallel to the rectifier GL, the capacitor C is connected on the DC side for radio interference suppression. In the positive supply line a storage inductor LH is connected. The switching element SH ensures in the on state for a rising to an adjustable value current flow in the storage inductor LH. After switching off the switching element SH, the diode DH conducts the current impressed in the storage inductor LH into the intermediate circuit capacitor CH.

First, it will be described how reactive current oscillations can be reduced by means of an adjustment of the time profile of a current ILH by the boost converter.

In FIG. 2 For example, for a prior art electronic ballast, the supply voltage UIN, the voltage across the input capacitance of the load UC, the mains current IN, and the average current ILH flowing through the boost converter are shown. There are three relevant intervals T1, T2, T3 entered.

The end of the phase gating defines the beginning of the first interval T1. A current flow IN from the supply network through the dimmer begins. The increase of the current IN is determined by the inductance of the dimmer. The voltage UC across the input capacitance C increases. The interval T1 ends as soon as the voltage UC across the input capacitance C corresponds to the instantaneous value of the supply voltage UIN.

In the second interval T2, the input capacitance C is further charged by the serial inductance L of the phase gating dimmer. The complete demagnetization of the inductance L defines the end of the interval T2. Although in the time interval T2, the voltage across the input capacitance C is higher is as the supply voltage UIN, a mains current continues to flow IN, because the inductance demagnetizes in the phase gating dimmer and maintains the flow of IN in the same direction.

In a third interval T3, first a small current IN flows from the input capacitance C back to the supply since the rectifier diodes commutate in the reverse direction. As a result of the current ILH flowing through the boost converter, the voltage across the input capacitance C decreases and then reaches the instantaneous value of the supply voltage. This time corresponds to the end of the interval T3.

In the scenario described above, in the interval T3, no mains current IN flows. The consequence is that the phase angle dimmer, when using a triac as a switching element, turns off. Triacs need a certain holding current to stay on.

In FIG. 3 For a electronic ballast according to the invention, the supply voltage UIN, the voltage across the input capacitance of the load UC, the mains current IN and the average current ILH flowing through the boost converter are shown. Two relevant intervals T1, T2 are entered.

Unlike the scenario in FIG. 2 flows in the inventive electronic ballast in FIG. 3 during the interval T1 no current ILH through the boost converter, because the switching element SH of the boost converter off FIG. 1 permanently locks. As a result, the magnetization of the series inductance L of the phase gating dimmer can be minimized.

In the interval T2, during which the inductance in the phase gating dimmer L is demagnetized and the energy stored in it is transferred to the capacitive load, a current ILH flows through the step-up converter. This current ILH must be so large that the temporary voltage over the input capacitance C is not as pronounced as in FIG. 2 , To Within the interval T2, the energy transmitted by ILH must be greater than the energy stored in the serial inductance of the phase gating dimmer L at the beginning of the interval T2.

An increased current flow within the interval T2 can be achieved by operating the boost converter temporarily in continuous operation mode, in contrast to the otherwise used discontinuous operating mode.

When comparing FIG. 2 and FIG. 3 it can be seen that the current ILH is greatly reduced by the boost converter in the invention in the interval T1 and is greatly increased in the interval T2. Following T2, the current flow from the supply IN is not interrupted in the invention. The interval T3 is omitted. The phase control dimmer does not switch off.

In addition, the above result can also be achieved by increasing the Abschaltstromschwelle. If the boost converter operates with an increased turn-off current threshold, a larger average current flows through the storage inductor during the power consumption cycles. So that the storage throttle does not saturate, it may need to be re-dimensioned.

FIG. 4 shows a circuit arrangement according to the invention for detecting the limits of the intervals T1 and T2.

Parallel to the input capacitance C of the load, a series circuit of a capacitor C2 and a resistor R1 is connected. Parallel to the resistor R1, a series circuit of a capacitor C3 and a resistor R2 is connected. Threshold components, specifically two Schmitt triggers ST1 and ST2, whose outputs mark the intervals T1 and T2, are connected to the connection node between R2 and C3.

FIG. 5 shows relevant voltage curves of the circuit arrangement FIG. 4 ,

To describe the voltage curves in FIG. 5 a jump function is assumed as the supply voltage UIN. This assumption about the supply voltage UIN is a good approximation for the actual time course of the phase-cut supply voltage on the time scale of interest. Further, in the following consideration, the current ILH is neglected by the boost converter. This is for the consideration of the vibration processes when switching through the phase gating dimmer only of minor importance.

FIG. 5 shows in the top diagram the course of the supply voltage UIN and the voltage UC across the capacitive input load. Deviating from the Figures 2 . 3 . 9 and 11 the voltage UC is not shown schematically as a linear function, but drawn somewhat more realistic.

The voltage UR1 across R1 is proportional to the current loading the input capacitance C. R1 and C2 are dimensioned so that UR1 corresponds to the first derivative of the time course of UC. In the second differentiating series circuit of R2 and C3, these are dimensioned so that a voltage drops across the resistor R2, which corresponds to the second derivative of the time course of the voltage UC.

Alternatively, in order to determine the first derivative, it is also possible to connect the resistor R1 in series with the input capacitance C and to dispense with the capacitor C2.

The voltage drop across R2, which corresponds to the second derivative of the voltage UC applied to the input capacitance C, is supplied to two Schmitt triggers. A first Schmitt trigger ST1 generates an output voltage USTA1, which assumes a positive value in the interval T1. During the interval T1, the second derivative of UC is positive. Outside of T1, USTA1 corresponds to the reference potential. A second Schmitt trigger ST2 generates an output voltage USTA2, which assumes a positive value in the interval T2. During the interval T2 is the second derivative of UC negative. Outside T2, USTA2 is equal to the reference potential.

The voltage UC across the input capacitance may be superimposed by high-frequency alternating voltages. The differentiation by the series connection of the capacitor C2 and the resistor R1, in particular, decouples the high-frequency AC voltage components. The voltage UR1 may then no longer be meaningfully evaluable for the following differentiator.

FIG. 6 shows a correspondingly improved circuit arrangement according to the invention. The capacitor C3 of the second differentiator is no longer connected directly to the connection node of R1 and C2, but via a parallel connection of a diode D1 and a resistor R3. The diode is poled so that a current from C2 to C3 can flow through it, but no current from C3 to C2. In addition, another capacitor C4 is used, which is parallel to the series circuit of C3 and R2. With this peak detection circuit, the first derivative of the voltage across the input capacitance UC is smoothed. In the capacitor C4, the peak value of the voltage is stored via R1 via the diode D1. R3 allows slow unloading of C4.

FIG. 7 shows a circuit arrangement according to the invention for specifying an estimate of the intervals T1 and T2.

Between the DC voltage outputs of the rectifier GL, a voltage divider of a resistor R4 and a resistor R5 is connected. Above this voltage divider R4, R5 drops a boost converter input voltage UINL. Parallel to the voltage divider R4, R5, a series circuit of a diode DC and the input capacitance C is connected. The diode DC blocks if there is a voltage UC across the input capacitance which is greater than the boost converter input voltage UINL. The center tap of the voltage divider is connected to an input of a threshold value element ST3. Threshold element ST3 here is a Schmitt trigger and generates an output signal ST3A, which may be logically one or zero. The circuit arrangement has two timers TIM1 and TIM2, to which the output signal ST3A of the threshold value element ST3 is supplied. The timers TIM1 and TIM2 each provide an output signal TIM1A and TIM2A, which may also be logically one or zero.

FIG. 8 shows the relevant waveforms of the circuit FIG. 7 together with the supply voltage UIN and the voltage UC across the input capacitance C following the phase gating.

Following the phase control, the boost converter input voltage UINL increases. The threshold value element ST3 is set via the voltage divider R4, R5. The output signal ST3A of the threshold element jumps from logic zero to logic one. It thus simultaneously sets the two timers TIM1 and TIM2. The timer TIM1 is designed so that its output signal TIM1A jumps back to zero at the latest following the magnetization of the inductance in the phase gating dimmer. The timer TIM2 is designed such that its output signal TIM2A returns to logical zero at the earliest after the complete reduction of the voltage overshoot above the input capacitance. The time in which the output signal TIM1A of the timer TIM1 is logically one therefore corresponds to the time interval T1. The output signal TIM2A of the timer TIM2 is logic one during the time intervals T1 and T2. By ANDing the two output signals TIM1A and TIM2A, it is also possible to generate a signal which is only logic one during the time interval T2.

The hold times of the timers TIM1, TIM2 are already specified here by the manufacturer. The two variables which essentially determine the time intervals T1 and T2 are the inductance of the phase gating dimmer and the input capacitance C. The input capacitance C is known to the manufacturer and can easily be taken into account by the latter. The inductance of the The phase-angle dimmer that is actually used can not be considered in advance; instead, an average over the time intervals T1, T2 of the dimmers available on the market is established for determining the holding times of the timers TIM1, TIM2.

The difference between permanently set time intervals T1 and T2 and the actual intervals dependent on the inductance in the dimmer is greater the greater the voltage overshoot across the input capacitance C following the phase gating. If further measures are taken to reduce the voltage overshoot across the input capacitance C, the inductance-related deviations of the actual intervals from the predefined time intervals T1 and T2 have less of an effect on the reduction of the voltage overshoot than without such further measures. One of these further measures will be explained with reference to FIGS. 9 et seq.

The in the FIGS. 4 . 6 and 7 described circuit arrangements according to the invention can with the electronic ballast from the EP 1 465 330 A2 can be advantageously used by being there parallel to the input capacitance C (C1 in the EP 1 465 330 A2 ). The circuit arrangements control the boost converter so that in the interval T1 the current through LH and thus the current discharging the input capacitance is minimal. This can be achieved in that the switch SH permanently locks, by a control of the switch SH via the control device of the boost converter from the EP 1 465 330 A2 by the voltage signal STA1 from one of the circuit arrangements according to the invention.

In contrast, according to the invention, a temporarily increased average current ILH is to flow through the boost converter in the interval T2. For this purpose, the operation of the boost converter via the control device from the EP 1 465 330 A2 be varied (in the EP 1 465 330 A2 the control circuit is labeled BCC).

Normally, the boost converter is operated in the so-called discontinuous mode. The switch SH is always turned on only when in the storage inductor of the boost converter no current flows, so if the storage inductor LH is just completely demagnetized. Switching losses are minimal in this mode of operation.

In this embodiment, however, the boost converter is operated in the interval T2 in the continuous mode. The continuous mode is characterized by the fact that it is not necessary to wait as long as the switching element SH is switched on, as in the discontinuous case, so that a current flows continuously through the storage inductor LH. As a result, the average current flow is increased by the boost converter in the interval T2 compared to normal operation. Since the interval T2 is short compared to an entire half-wave, the increased switching losses caused are averaged out to a small, negligible amount.

It has been found that a smooth transition from the continuous mode to the discontinuous mode is advantageous because it allows further current oscillations to be reduced. "Flowing transition" here means that the inrush current thresholds decrease. As soon as the switch-off time of the switch SH is so long that the storage choke LH can completely demagnetise itself, a discontinuous mode is present. The switch-off time can be extended further if desired.

Based on Figures 9 In the following, it will be explained how additional reactive current oscillations can be reduced by suitably charging or discharging the input capacitance during phase control.

Because the three previous embodiments (according to the FIGS. 4 . 6 and 7 ) to realize both possibilities of reactive power reduction, they dampen reactive current vibrations more effectively. If the input capacitance C is charged or discharged to a suitable value before the end of the phase control, the voltage overshoot UC after the end of the Magnetization of the inductance in the dimmer is not as pronounced as without this intervention. Less reactive current flows and the remaining reactive current oscillation can be damped more easily by suitable control of the current through the boost converter.

In FIG. 9 is like in FIG. 2 First, to understand an electronic ballast according to the prior art, the supply voltage UIN, the voltage UC across the input capacitance C of the load and the line current IN shown. In addition, the voltage UL across the inductance in the phase gating dimmer is shown. These are the three equal intervals T1, T2, T3 as in FIG. 2 entered.

The course of the supply voltage UIN, the voltage across the input capacitance UC and the course of the mains current in the time intervals T1, T2 and T3 is identical to that of FIG. 2 ,

The increase of the current IN is determined by the inductance of the dimmer, the size of the input capacitance C and the voltage UL across the inductance of the dimmer. Note the large peak values of the voltage UL across the inductance in the phase gating dimmer, the voltage UC across the input capacitance C and the mains current IN.

The reactive current superimposed on the active current required to supply the discharge lamp should be reduced. This reactive current is caused by the magnetization and demagnetization of the inductance in the phase gating dimmer, continues to charge the input capacitance C during demagnetization T2 of the inductance in the dimmer and causes the voltage overshoot.

The current IN through the inductance of the phase gating dimmer increases as long as the voltage UC across the input capacitance C is lower than the supply voltage UIN. This is the case in interval T1. Before the end of the phase gating (before the interval T1), the input capacitance C is charged so that the voltage UC across the input capacitance C is the instantaneous value the supply voltage UIN at the end of the phase gating comes close. Since approximately UL = UIN - UC applies, the voltage UL is above the inductance of the dimmer then at the beginning of the magnetization of this inductance smaller than without proper charging of the input capacitance C. Thus, the peak current IN through the inductance of the dimmer is comparatively small. Ideally, the voltage UC at the end of the phase control corresponds to the instantaneous value of the supply voltage UIN. It will be shown below that it is technically sensible to choose the value of the voltage UC slightly smaller.

In this example, the instantaneous value of the supply voltage is stored in each line half-wave of the supply network at the end of the phase control; at a cleverly selected time of storage, the stored value corresponds to the instantaneous value of the supply voltage UIN at the end of the phase control. A corresponding circuit will be described below. The input capacitance C is then charged to just before switching on the switching element in the dimmer in the next half-wave (90%) of the value stored in the previous half-wave. It can be assumed that the change made by an operator to the phase angle of the dimmer in successive mains half-waves is only slight.

The Figures 10 a and b show schematically the profile of the voltage UC when discharging or charging the input capacitance C to the value of the supply voltage UIN stored in the previous half-cycle. At the times when the input capacitance C is charged or discharged, the course of the voltage UC is shown in dashed lines, because the exact course is not relevant.

FIG. 10 a shows the case that the input capacitance C is discharged before the end of the phase gating, and FIG. 10b shows the case that the input capacitance C is charged before turning on the switching element in the dimmer. How this happens is described below.

In both cases, the difference between the voltage UC across the input capacitance C and the instantaneous value of the supply voltage UIN at the end of the phase control becomes small or almost disappears.

When applying the supply voltage UIN for the first time via the dimmer and to the load, a reactive current oscillation may not be avoided, because no prognosis value for the supply voltage UIN has yet been stored. However, after a few half-waves, the system has reached a stable state.

FIG. 11 shows for the further features of the embodiments, the supply voltage UIN, the voltage UC across the input capacitance C, the mains current IN and the voltage UL across the inductance of the dimmer. For ease of understanding, only the effect of a suitable charge on the input capacitance before the end of the phase gating will be shown. Measures based on the FIGS. 3 to 8 were explained missing.

The voltage UC across the input capacitance C is slightly smaller than the value of the instantaneous voltage UIN at the end of the phase control. It can be seen that the peak value of the mains current IN compared to FIG. 9 is significantly smaller. The peak value of the voltage UL applied across the inductance is also smaller. The mains current IN oscillates significantly less. After the demagnetization T3 of the inductor flows in the dimmer, unlike in FIG. 9 shown a continuous line current IN. The invention prevents the holding current of the switching element is fallen below in the dimmer.

FIG. 11 shows that the voltage UC is set above the input capacitance C to a value at the end of the phase control, which is below the corresponding instantaneous value of the supply voltage. This can ensure that in each case a current can flow to the load following the phase control.

Another way of predicting the instantaneous value of the supply voltage UIN is as follows: A further component, for example an inductance, can be connected in series with the input of the electronic ballast. At this component, at the end of the phase gating, there is approximately a voltage proportional to the difference UIN-UC, which can then be used in a subsequent half-wave to adjust the voltage across the input capacitance.

FIG. 12 a describes a less expensive and more reliable circuit arrangement. The task of the circuit is to measure the instantaneous value of the voltage UIN following the phase control. Furthermore, the circuit should address a control device of the boost converter for the described charge of the input capacitance C.

The circuit includes a monoflop MF, which is activated via a signal input A at the end of the phase control. At one output B of the monoflop MF is one of two states. One of them indicates that the monoflop MF is set, the other state takes the monoflop MF in the remaining time.

The output B of the monoflop MF is applied to a control input C of a switch AS. The switch AS forwards a signal AVIN from a second input D to an output E when it is activated via the control input C. The signal AVIN is proportional to the supply voltage UIN of the load.

To the output E of the switch AS, a diode DS and a capacitor CS for peak detection is connected. Parallel to the capacitor CS while a resistor RS is connected. Over this, the capacitor CS can be discharged slowly as the peak values to be detected become smaller. The discharge time of the capacitor CS is determined only by the size of the capacitance CS and the resistance RS. The corresponding Time scale is chosen so that it is appropriate to the change of the phase control by an operator.

The voltage across the capacitor CS is supplied to a first input COM2 of a comparator COM. A second input COM1 of the comparator COM is supplied with a signal UC proportional to the voltage UC. An output COMA of the comparator assumes a first state when the signal AVC at input COM1 is smaller than the signal at the other input COM2, and a second state when the signal at COM1 is greater than the signal at COM2. The output COMA of the comparator COM can be connected to the control device of the boost converter, for example.

The length of the time window in which the monoflop MF is set is very small compared to the period of the supply voltage UIN. In the longest case, the monoflop MF remains set during the entire magnetization of the inductance in the dimmer (in the interval T1).

FIG. 12b shows how the length of the time window can also be specified by means of differentiator of a capacitor CT and a resistor RT. Like the monoflop MF, the differentiator is addressed via a signal input at the end of the phase control. Thus, a voltage jump occurs across the resistor RT, which decays exponentially. The time constant of the exponential decay is the product of the size of the resistor RT and the capacitance CT. The duration of the decay of the voltage jump across the resistor RT specifies the time window in which the switch AS remains switched on.

Alternatively, a suitable time window for the storage of a prognosis value for the supply voltage UIN can also be determined by means of one of the circuit arrangements from the FIGS. 4 . 6 or 7 be recorded or specified. The detected time of the end of the magnetization T1 of the inductance in the dimmer corresponds to the zero crossing of the second derivative of Voltage UC over the input capacitance C. This time is indicated by the signal outputs STA1 and STA2 or TIM1A and TIM2A and determines the end of the time window. In this case, as a forecast value, the peak voltage UC over the input capacitance C can be stored up to this time. Since the supply voltage has scarcely changed since the end of the phase control, the voltage UC across the input capacitance C corresponds at this time to the instantaneous value of the supply voltage UIN at the end of the phase control.

The circuit arrangements of the Figures 12 a and 12 b can be, as the circuits from the FIGS. 4 . 6 and 7 , good in the in the EP 1 465 330 A2 Install the boost converter described above. This has a control circuit BCC, which among other things of the circuit arrangement FIG. 12 a and b can be controlled. Further measures for charging or discharging the input capacitance C can be concretely described for this boost converter.

The time of switching on the switching element in the dimmer can in the boost converter from the EP 1 465 330 A2 by the incipient current flow through, for example, the storage inductor LH (L1 in the EP 1 465 330 A2 ) of the boost converter. This incipient current flow triggers the monoflop MF via the input A. The monoflop MF switches on at the end of the phase control to the end of a predetermined time interval (the time window) via the input C, the switch AS. While the switch AS is turned on, the capacitance CS via the diode DS detects the voltage applied to the input AVIN peak voltage.

With the signal COMA, the boost converter from the EP 1 465 330 A2 be activated as long as the voltage UC across the input capacitance C is greater than the stored value. Characterized the input capacitance C is discharged to a value which is slightly below the value of the supply voltage UIN at the end of the phase control. Specifically, the signal line COMA with an element of the control circuit BCC of the boost converter connected. In the EP 1 465 330 A2 in theirs FIG. 5 a is a flip-flop FF2 described, which can be set by means of the output COMA of the comparator COM, so that the boost converter is activated.

Alternatively, the input capacitance C can also be discharged by a switching element connected in parallel, for example a series connection of a transistor and a resistor. This is controlled via the signal line COMA so that it turns on and the input capacitance C discharges.

FIG. 13 shows a variation of the boost converter circuit FIG. 1 ; There is an additional resistor RH connected in parallel to the diode DH.

Namely, is a charging of the input capacitance C desired, as in FIG. 10b shown, the diode DH can be bridged with a resistor RH. As a result, the input capacitance C can be charged via the intermediate circuit capacitor before the end of the phase control. To load the input capacitance to the value stored in the memory device, control is required. If you do not want to add such a special, so the input capacitance C can be charged by the DC link capacitor so strong that the voltage UC on the input capacitance C is too high. Thereafter, the boost converter can be activated to discharge the input capacitance C to the desired value.

There are types of boost converters which have a plurality of diodes connected between the supply potential of the intermediate circuit capacitor CH and the supply potential of the input capacitance C; here one or more diodes can be bridged.

Claims (18)

1. Electronic ballast with a step-up converter (LH, SH, DH, CH), which has a switching element (SH) and an input capacitance (C), for operation using a phase gating dimmer, which has an inductance acting in series with the supply, characterized in that, within a system half-cycle, the operational parameters of the step-up converter (LH, SH, DH, CH) are set during the demagnetization (T2) of the inductance in the phase gating dimmer, which takes place after the phase gating, in such a way that, in comparison with the operation of the step-up converter (LH, SH, DH, CH) after the demagnetization (T2) of the inductance, a temporarily increased current (ILH) flows through the step-up converter.
2. Electronic ballast according to Claim 1, in which the step-up converter (LH, SH, DH, CH) has various operating modes, which differ in terms of their switch-on current thresholds of the switching element (SH), and, during the demagnetization (T2) of the inductance, temporally after the termination of the phase gating, functions in an operating mode with temporarily increased switch-on current thresholds of the switching element (SH), so that a temporarily increased current (ILH) flows through the step-up converter.
3. Electronic ballast according to Claim 2, in which the step-up converter (LH, SH, DH, CH) has a continuous and a discontinuous operating mode and, during the demagnetization (T2) of the inductance, temporally after the termination of the phase gating, functions in the continuous operating mode for temporarily increasing the current (ILH) through the step-up converter (LH, SH, DH, CH), but then functions in the discontinuous mode after the demagnetization (T2) for the rest of the system half-cycle.
4. Electronic ballast according to one of the preceding claims, in which, during the demagnetization (T2) of the inductance, the switch-off current threshold of the switching element (SH) of the step-up converter (LH, SH, DH, CH) is increased.
5. Electronic ballast according to one of the preceding claims, in which, during the magnetization (T1) of the inductance in the phase gating dimmer, temporally after the termination of the phase gating, the switch-off current threshold is set to be very low in comparison with the operation of the step-up converter (LH, SH, DH, CH) after termination of the magnetization (T1).
6. Electronic ballast according to one of the preceding claims, in which, during the magnetization (T1) of the inductance in the phase gating dimmer, temporally after the termination of the phase gating, the switch-off current threshold is initially very low in comparison with the operation of the step-up converter (LH, SH, DH, CH) after termination of the magnetization (T1) and increases over the duration of the magnetization (T1).
7. Electronic ballast according to one of Claims 1 to 4, in which, during the magnetization (T1) of the inductance in the phase gating dimmer, temporally after the termination of the phase gating, the switching element (SH) in the step-up converter (LH, SH, DH, CH) is turned off.
8. Electronic ballast according to one of the preceding claims, which has a series circuit comprising two differentiators (C2, R1, C3, R2) for detecting the termination of the phase gating, the beginning of the demagnetization (T2) of the inductance in the phase gating dimmer and the termination of the demagnetization (T2) of the same inductance.
9. Electronic ballast according to Claim 8 with a peak value detection circuit (D1, R3, C4), which is connected upstream of the differentiator.
10. Electronic ballast according to one of Claims 1 to 7 with a threshold value element (ST3) for detecting the termination of the phase gating and a first timing element (TIM1, TIM2), which predetermines a first fixed time interval and is set by the threshold value element (ST3) after the phase gating.
11. Electronic ballast according to Claim 10 with a second timing element (TIM1, TIM2), which predetermines a second fixed time interval and is set by the threshold value element (ST3) after the phase gating.
12. Electronic ballast according to Claim 11, in which the first time interval lasts at most up to the end of the magnetization (T1), and in which the second time interval lasts at least until the complete decay of the excessively high voltage across the input capacitance (C).
13. Electronic ballast according to Claim 2, also in combination with a further one of the preceding claims, which is designed to continuously carry out the transition from an operating mode with a high switch-on current threshold during the demagnetization (T2) of the inductance in the phase gating dimmer to an operating mode used after the demagnetization (T2) of the inductance with a lower switch-on current threshold.
14. Electronic ballast according to one of the preceding claims with a device (DS, CS) for storing a prognosis value of the supply voltage (UIN) of the electronic ballast, in which, during a system half-cycle of the supply, the prognosis value of the supply voltage (UIN) after termination of the phase gating is stored in order to set the input capacitance (C), prior to the end of the phase gating, at most to a voltage which corresponds to the value stored in the device (DS, CS), by means of a charging operation in a subsequent system half-cycle.
15. Electronic ballast according to Claim 14, in which the storage device (DS, CS) is designed to store an instantaneous value of the supply voltage (UIN) during a system half-cycle after termination of the phase gating, the stored value corresponding to the prognosis value.
16. Electronic ballast according to Claim 14 or 15, in which the storage device (DS, CS) is designed to store the prognosis value of the supply voltage (UIN) after termination of the phase gating in each system half-cycle, and the ballast is designed to set the input capacitance (C), prior to the end of the phase gating, at most to a voltage which corresponds to the value stored in the device (DS, CS), in each respectively following system half-cycle.
17. Electronic ballast according to one of Claims 14 to 16 which is designed to store the prognosis value to be stored of the supply voltage (UIN) within a time window after termination of the phase gating via a peak value detection (DS, CS).
18. Discharge lamp with an integrated electronic ballast according to one of the preceding claims.

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