EP1861873A1 - Method of producing a hetero-structure comprising at least one thick layer of semiconductor material - Google Patents

Method of producing a hetero-structure comprising at least one thick layer of semiconductor material

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Publication number
EP1861873A1
EP1861873A1 EP06725289A EP06725289A EP1861873A1 EP 1861873 A1 EP1861873 A1 EP 1861873A1 EP 06725289 A EP06725289 A EP 06725289A EP 06725289 A EP06725289 A EP 06725289A EP 1861873 A1 EP1861873 A1 EP 1861873A1
Authority
EP
European Patent Office
Prior art keywords
thin layer
layer
thickness
support
transferred
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06725289A
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German (de)
French (fr)
Inventor
Fabrice Letertre
Bruno Ghyselen
Ian Cayrefourcq
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
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Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Publication of EP1861873A1 publication Critical patent/EP1861873A1/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques

Definitions

  • the present invention relates generally to the manufacture of materials and more particularly hetero-substrates for microelectronics, optoelectronics, optics or photonics.
  • the invention relates to a new process for producing a hetero-substrate composed of at least one support and one or more thin layer (s), where the materials used and their thermal properties can be different.
  • the known processes of the Besoi®, Eltran® or Smart-Cut® type use a gluing step.
  • these methods comprise at least the following steps: a) bonding by contacting two generally massive substrates into generally dissimilar materials, with a layer useful which is based on a support substrate, the whole forming a hetero-structure, b) a strengthening of the bonding interface of the two substrates by implementing a heat treatment at high temperature to reduce the fragility of said interface. Problems of delamination and alteration of the mechanical and / or electrical quality of said useful layer are thus avoided, at least limited, and c) a reduction of the thickness of the useful layer resting on the support substrate to constitute a thin layer.
  • steps b) and c can be implemented with different possibilities, such as, for example, sacrificial oxidation in step c), or with a different order, with in particular a reversal between steps b) and c).
  • step b a stabilizing heat treatment of the bonding interface
  • step c a thinning step
  • the heat treatments undergone during the manufacture of the composite substrate typically induce significant mechanical stresses. Such stresses can lead to embrittlement, followed in some cases by cracking or even fracture, of one or both treated substrates.
  • temperatures at which these problems appear typically depend: on the mechanical energy stored by the composite structure during the heat treatment implemented, on the difference between the coefficients of thermal expansion of the materials composing the composite structure, and the thickness of the substrates used.
  • an interface strengthening heat treatment at about 1050-1000 ° C. will be difficult to implement in the case of a hetero-structure having a useful layer of 500 ⁇ thickness.
  • the temperature levels generally practiced in this type of treatment being too high with regard to the problems mentioned above. Solutions are also known which make it possible to improve the reinforcement of the bonding interface of a hetero-substrate without additional thermal input.
  • a first proposal known as "plasma bonding" consists in applying certain treatments to the surfaces to be bonded, in order to increase the bonding energy for a given reinforcement heat treatment.
  • a second known solution is to perform a eutectic bonding: a metal layer (Au 2 Si 3 ) is interposed between the two substrates to seal to facilitate their bonding by heat treatment, so that the temperature levels can remain relatively low.
  • This solution therefore also offers the advantage of being able to relax the thermal stresses in a treatment for reinforcing the interface of a hetero-substrate.
  • An object of the invention is to overcome the above problems.
  • a method of manufacturing a structure comprising at least one semiconductor material for applications in microelectronics, optoelectronics, optics, etc., the method comprising the transfer on a support made of a first material of a monocrystalline thin layer of a second material different from the first, and a predetermined heat treatment providing at least one reinforcement of a bonding interface between the thin layer and the support, characterized in that the thickness of the thin layer is chosen according to the difference between the thermal expansion coefficients of the first and second materials and as a function of the parameters of said predetermined heat treatment, so that the stresses exerted by said heat treatment on the assembly of the support and the thin layer transferred. leaves said assembly intact, and in that it comprises an additional deposition step, on the thin wafer, of an additional thickness of the second material in the monocrystalline state.
  • the thickness of the transferred thin layer is between about 100 and 300 ⁇ , and preferably between 150 and 250 ⁇ . * The thickness of the deposit produced on the thin transferred layer is between about 1000 and 5000 ⁇ .
  • the thin film step of transferring the second material comprises the sub-steps of creating a donor wafer by implantation of species, a zone of weakness which delimits the thin layer to be transferred, contacting the donor wafer with the support, and to apply constraints apt to lead to the detachment of the thin layer relative to the remainder of the donor wafer after contacting.
  • the method comprises an additional step of preparing the free surface of the thin film after detachment, to achieve deposition.
  • the first material is an insulator
  • the first material is quartz, while the second material is silicon. * the first material is a semiconductor.
  • the first material is silicon, while the second material is germanium.
  • Said heat treatment is apt to generate in the thin transferred layer an acceptable level of defects associated with the difference between the thermal expansion coefficients of the first and second materials.
  • the support 10 and the wafer 20 are assembled and glued together by molecular adhesion, a bonding interface layer (Not shown), such as an oxide or nitride, being optionally formed on the support and / or on the wafer.
  • the bonding interface is designated by the reference 12.
  • the assembly then undergoes a heat treatment, in one or more steps, so as firstly to perform on the one hand a detachment between the zone 22 and the rest of the wafer 20 at the weakening zone, and on the other hand a strengthening of the bonding interface between the support 10 and the thin layer now formed by the zone 22 detached as indicated above.
  • the structure thus formed is illustrated in FIG. 1C.
  • the above steps generally correspond to the Smart-process.
  • the present invention aims at situations in which the material of the support 10 and the material of the thin layer 22 have sufficiently different coefficients of thermal expansion from one another so that the aforementioned heat treatments can not be implemented without attending a form of deterioration of the composite structure of the support 10 and the thin layer 22, with any bonding interface layers.
  • a low value is chosen for the thickness e1 of the transferred layer 22, such that the aforementioned heat treatments leave the structure substantially unaffected; in other words, the thickness of the layer 22 is chosen sufficiently low not to cause rupture phenomena, or undesirable phenomena of plastic deformation, linked for example to dislocations, atomic plane shifts, cracks, etc. . in the layer 22.
  • the free surface of the layer 22 is then prepared to receive a deposit of the same material. This preparation may comprise a chemical mechanical polishing, a sacrificial oxidation, a rapid thermal annealing (RTA for "Rapid Thermal Annealing" in English terminology) or an oven annealing, etc., the objective here being to achieve at a sufficiently low surface roughness.
  • RTA Rapid Thermal Annealing
  • the next step of the process consists in using the layer 22 thus prepared as a seed layer for depositing the same material over a thickness e2, by epitaxy, and effecting an increase in the thickness of the overall layer 220 (useful layer) of the material constituting the layers 22 and 22 'up to the desired value.
  • Epitaxy makes it possible to obtain a very good crystalline quality.
  • the choice of the thickness e1 of the transferred layer 22 may be such that there is a certain density level of dislocations or sliding planes in the intermediate hetero-structure represented in FIG. 1C and in particular In fact, these defects, after the epitaxy of the layer 22 ', are buried deep in the useful layer 220 and are not through.
  • phase of thickening by epitaxial deposition of the layer 22 makes it possible to postpone in the end much greater thicknesses than is possible with a technique of the Smart-Cut® type, limited in a manner inherent by the possible depth of implantation
  • a structure composed of a quartz support for example of a thickness of 1.2 mm, on which a monocrystalline silicon layer with a thickness of up to 500 to 2000 ⁇ applications in microelectronics, or even more for other applications such as charge coupled devices (CCD) in English terminology.
  • a quartz support for example of a thickness of 1.2 mm, on which a monocrystalline silicon layer with a thickness of up to 500 to 2000 ⁇ applications in microelectronics, or even more for other applications such as charge coupled devices (CCD) in English terminology.
  • CCD charge coupled devices
  • the experiment demonstrates that the critical temperature from which excessive plastic deformations (dislocations, sliding planes, etc.) occur in a structure composed of a thin layer of Si transferred according to the Smart-Cut process on a support in quartz depends on the thickness of the layer transferred as follows: Thickness layer 22 Temp. Critical
  • a layer of monocrystalline silicon 22 having a thickness of 200 ⁇ is transferred onto the quartz support 10, this transfer involving reinforcement of the bonding interface by heat treatment at 1050 ° C. for a period of time. about two hours. Due to the limited thickness of the layer 22, this heat treatment does not cause any detrimental deterioration (cracking or breaking) of the structure.
  • the free surface of the thin layer 22 is then prepared for epitaxial deposition of the silicon complement making it possible to produce the monocrystalline useful layer of the desired thickness.
  • This epitaxy to form the layer 22 'also monocrystalline silicon is made to a thickness that can vary widely depending on the application.
  • the thickness of the deposit is for example about 800 to 1800 ⁇ , resulting in a useful layer thickness of about 1000 to 2000 ⁇ .
  • the overall thickness sought is typically 5 to 10 ⁇ m.
  • a semiconductor-on-insulator structure comprising a silicon support (monocrystalline or polycrystalline) and a thick monocrystalline germanium thick layer, for example for photovoltaic component applications.
  • these treatments include a detachment phase at a temperature of about 300 to 400 ° C for a period of about a few minutes to two hours, and then a step of reinforcing the bonding interface at a temperature of about 500 at 800 ° C for a period of about one hour.
  • a thickness of the thin layer 22 which is not greater than about 200 ⁇ makes it possible to apply these heat treatments to the structure without said thin layer deteriorating.
  • a monocrystalline germanium deposit 22 ' is formed which is formed in the continuity of the layer 22 in terms of crystalline structure, and therefore achieve a thickening thereof.
  • this deposition is carried out at a temperature of about 700 ° C., and at a thickness of 4800 ⁇ , to form a total useful layer of monocrystalline germanium having a thickness of 5000 ⁇ or more (up to at 3 ⁇ m).
  • the present invention is not limited to the embodiments described, and the skilled person will be able to make many variations.
  • heterostructure comprising at least one semiconductor material and in which an added layer must have a thickness greater than that authorized by the essential starting data which are the heat treatments to be undergone and the difference between the coefficients of thermal expansion of the two materials.
  • essential starting data which are the heat treatments to be undergone and the difference between the coefficients of thermal expansion of the two materials.
  • structures of InP on Si and GaAs on Si will be mentioned.
  • the transferred thin film may be constrained, in tension or in compression, by the additional thickness of deposited material preserving this stress.
  • This allows thick stress layers, the stresses being ensured on thicknesses of several tens of nanometers, or even up to a few hundred nanometers depending on the level of stress that one wishes to preserve.

Abstract

The invention relates to a method of producing a structure comprising at least one semiconductor material for use in microelectronics, optoelectronics, optics, etc. The inventive method comprises the following steps consisting in: equipping a support (10) which is made from a first material with a thin monocrystalline layer (22) of a second material which is different from the first, said layer being transferred to the support; and performing a pre-determined heat treatment such as at least to reinforce the bonding interface (12) between the thin layer and the support. The method is characterised in that the thickness (e1) of the thin layer is selected as a function of the difference between the thermal expansion coefficients of the first and second materials and as a function of the parameters of said pre-determined heat treatment, such that the stresses exerted by said treatment on the support/transferred thin layer assembly leave same intact. The invention is also characterised in that it comprises an additional step in which an additional thickness (22') of the second material in the monocrystalline state is deposited on the thin layer. The invention is suitable for the production of hetero-substrates comprising a thick useful layer.

Description

Procédé de fabrication d'une hétéro-structure comportant au moins une couche épaisse de matériau semi-conducteurMethod for producing a hetero-structure comprising at least one thick layer of semiconductor material
La présente invention concerne d'une façon générale la fabrication de matériaux et plus particulièrement d'hétéro-substrats pour la microélectronique, l'optoélectronique, l'optique ou la photonique.The present invention relates generally to the manufacture of materials and more particularly hetero-substrates for microelectronics, optoelectronics, optics or photonics.
Plus précisément, l'invention concerne un nouveau procédé de réalisation d'un hétéro-substrat composé au moins d'un support et d'une ou de plusieurs couche(s) mince(s), où les matériaux utilisés ainsi que leurs propriétés thermiques peuvent être différents.More specifically, the invention relates to a new process for producing a hetero-substrate composed of at least one support and one or more thin layer (s), where the materials used and their thermal properties can be different.
On connaît déjà des procédés de ce type.Methods of this type are already known.
Il est ainsi connu de réaliser des hétéro-substrats en mettant en œuvre des techniques de collage en particulier par adhésion moléculaire.It is thus known to produce hetero-substrates by implementing bonding techniques, in particular by molecular adhesion.
A titre d'exemple et de manière non limitative, les procédés connus de type Besoi®, Eltran® ou Smart-Cut® utilisent une étape de collage.By way of example and in a nonlimiting manner, the known processes of the Besoi®, Eltran® or Smart-Cut® type use a gluing step.
On rappellera à cet égard que dans le cadre d'une fabrication d'hétéro-substrats, ces procédés comprennent au moins les étapes suivantes : a) un collage par mise en contact de deux substrats généralement massifs en matériaux en général dissemblables, avec une couche utile qui repose sur un substrat support, le tout formant une hétéro-structure, b) un renforcement de l'interface de collage des deux substrats en mettant en œuvre un traitement thermique à haute température en vue de réduire la fragilité de ladite interface. Les problèmes de délaminage et d'altération de la qualité mécanique et/ou électrique de ladite couche utile sont ainsi évités, tout au moins limités, et c) une réduction de l'épaisseur de la couche utile reposant sur le substrat support afin de constituer une couche mince.It will be recalled in this regard that in the context of a hetero-substrate manufacturing, these methods comprise at least the following steps: a) bonding by contacting two generally massive substrates into generally dissimilar materials, with a layer useful which is based on a support substrate, the whole forming a hetero-structure, b) a strengthening of the bonding interface of the two substrates by implementing a heat treatment at high temperature to reduce the fragility of said interface. Problems of delamination and alteration of the mechanical and / or electrical quality of said useful layer are thus avoided, at least limited, and c) a reduction of the thickness of the useful layer resting on the support substrate to constitute a thin layer.
De telles étapes peuvent être mises en œuvre avec différentes possibilités, telles que par exemple une oxydation sacrificielle à l'étape c), ou avec un ordre différent, avec en particulier une inversion entre les étapes b) et c).Such steps can be implemented with different possibilities, such as, for example, sacrificial oxidation in step c), or with a different order, with in particular a reversal between steps b) and c).
Par ailleurs, certaines de ces étapes elles peuvent être combinées en vue d'optimiser le procédé globalement (durée cumulée des traitements, durée cumulée liée aux manipulations, etc.).Moreover, some of these steps can be combined to optimize the process globally (cumulative duration of treatment, cumulative duration related to manipulations, etc.).
On profite par exemple d'un traitement thermique de stabilisation de l'interface de collage (étape b)), pour le combiner avec une étape d'amincissement (étape c)) (cf. brevet US6403450).For example, a stabilizing heat treatment of the bonding interface (step b) is used, to combine it with a thinning step (step c)) (see patent US Pat. No. 6,4034,50).
Toutefois, dans le cadre de la réalisation d'hétéro-substrats avec des matériaux ayant des propriétés différentes, par exemple des coefficients de dilatation thermique différents, les traitements thermiques subis lors de la fabrication du substrat composite (renforcement de l'interface, amincissement, ...) induisent typiquement des contraintes mécaniques importantes. De telles contraintes peuvent conduire à une fragilisation, suivie dans certains cas d'une fissuration voire d'une fracture, d'un ou des deux substrats traités.However, in the context of the production of hetero-substrates with materials having different properties, for example different thermal expansion coefficients, the heat treatments undergone during the manufacture of the composite substrate (interface reinforcement, thinning, ...) typically induce significant mechanical stresses. Such stresses can lead to embrittlement, followed in some cases by cracking or even fracture, of one or both treated substrates.
Ces contraintes peuvent aussi conduire à une déformation plastique irrémédiable du ou des substrats traités. En particulier, des dislocations et/ou des glissements de plan et/ou d'autres défauts cristallins peuvent apparaître.These stresses can also lead to irreversible plastic deformation of the treated substrate (s). In particular, dislocations and / or plane slips and / or other crystalline defects may occur.
Il est aussi connu que les températures auxquelles apparaissent ces problèmes dépendent typiquement : de l'énergie mécanique emmagasinée par la structure composite lors du traitement thermique mis en œuvre, de la différence entre les coefficients de dilatation thermique des matériaux composant la structure composite, et de l'épaisseur des substrats utilisés.It is also known that the temperatures at which these problems appear typically depend: on the mechanical energy stored by the composite structure during the heat treatment implemented, on the difference between the coefficients of thermal expansion of the materials composing the composite structure, and the thickness of the substrates used.
Ainsi, dans le cadre de la fabrication d'hétéro-substrats par procédé de type Smart Cut®, de tels problèmes peuvent constituer de réelles limitations. Plus particulièrement, les niveaux maximaux possibles en termes de température diminuent, de sorte que des traitements thermiques deviennent difficilement utilisables par manque d'efficacité.Thus, in the context of the production of hetero-substrates by Smart Cut® type process, such problems can constitute real limitations. More particularly, the maximum levels possible in terms of temperature decrease, so that heat treatments become difficult to use for lack of efficiency.
Par exemple et de manière non exhaustive, un traitement thermique de renforcement d'une interface vers 1050-1000°C va se trouver délicat à mettre en œuvre dans le cas d'une hétéro-structure comportant une couche utile de 500 Â d'épaisseur, les niveaux de température généralement pratiqués dans ce type de traitement étant trop élevés au regard des problèmes évoqués précédemment. On connaît par ailleurs des solutions qui permettent d'améliorer le renforcement de l'interface de collage d'un hétéro-substrat sans surcroît d'apport thermique.For example and in a non-exhaustive manner, an interface strengthening heat treatment at about 1050-1000 ° C. will be difficult to implement in the case of a hetero-structure having a useful layer of 500 Å thickness. , the temperature levels generally practiced in this type of treatment being too high with regard to the problems mentioned above. Solutions are also known which make it possible to improve the reinforcement of the bonding interface of a hetero-substrate without additional thermal input.
Une première proposition, connue sous le terme de « collage plasma », consiste à appliquer certains traitements sur les surfaces à coller, en vue d'augmenter l'énergie de collage pour un traitement thermique de renforcement donné.A first proposal, known as "plasma bonding", consists in applying certain treatments to the surfaces to be bonded, in order to increase the bonding energy for a given reinforcement heat treatment.
En procédant de la sorte on relâche les contraintes thermiques que subissent les substrats tout en maintenant un renforcement et un scellement adéquat de l'interface dans la structure composite. Mais cette proposition requiert des équipements spécifiques, limitant ainsi sont attrait sur le plan économique.By proceeding in this way, the thermal stresses that the substrates undergo are maintained while maintaining adequate reinforcement and sealing of the interface in the composite structure. But this proposal requires specific equipment, thus limiting its attractiveness economically.
Une deuxième solution connue consiste à réaliser un collage eutectique : une couche métallique (Au2Si3) est intercalée entre les deux substrats à sceller pour faciliter leur collage par traitement thermique, de sorte que les niveaux de température peuvent rester relativement bas .A second known solution is to perform a eutectic bonding: a metal layer (Au 2 Si 3 ) is interposed between the two substrates to seal to facilitate their bonding by heat treatment, so that the temperature levels can remain relatively low.
Cette solution offre donc, elle aussi, l'avantage de pouvoir relâcher les contraintes thermiques dans un traitement de renforcement de l'interface d'un hétéro-substrat.This solution therefore also offers the advantage of being able to relax the thermal stresses in a treatment for reinforcing the interface of a hetero-substrate.
Toutefois la présence de ladite couche métallique au niveau de l'interface limite les températures maximales permises lors d'étapes ultérieures du procédé de fabrication, des niveaux de températures trop élevés pouvant en effet conduire à une fusion de cette couche. En outre, elle nécessite une étape supplémentaire d'interposition de cette couche métallique.However, the presence of said metal layer at the interface limits the maximum temperatures allowed during subsequent steps of the manufacturing process, too high temperature levels. high levels can indeed lead to a melting of this layer. In addition, it requires an additional step of interposition of this metal layer.
Un but de l'invention est de permettre de s'affranchir des problèmes ci-dessus.An object of the invention is to overcome the above problems.
Elle propose à cet effet un procédé de fabrication d'une structure comprenant au moins un matériau semiconducteur pour des applications en micro-électronique, opto-électronique, optique, etc., le procédé comprenant le transfert sur un support en un premier matériau d'une couche mince monocristalline en un second matériau différent du premier, ainsi qu'un traitement thermique prédéterminé réalisant au moins un renforcement d'une interface de collage entre la couche mince et le support, caractérisé en ce que l'épaisseur de la couche mince est choisie en fonction de la différence entre les coefficients de dilatation thermique des premier et second matériaux et en fonction des paramètres dudit traitement thermique prédéterminé, de telle sorte que les contraintes exercées par ledit traitement thermique sur l'assemblage du support et de la couche mince transférée laisse ledit assemblage intact, et en ce qu'il comprend une étape supplémentaire de dépôt, sur la couche mince, d'une épaisseur supplémentaire du second matériau à l'état monocristallin.To this end, it proposes a method of manufacturing a structure comprising at least one semiconductor material for applications in microelectronics, optoelectronics, optics, etc., the method comprising the transfer on a support made of a first material of a monocrystalline thin layer of a second material different from the first, and a predetermined heat treatment providing at least one reinforcement of a bonding interface between the thin layer and the support, characterized in that the thickness of the thin layer is chosen according to the difference between the thermal expansion coefficients of the first and second materials and as a function of the parameters of said predetermined heat treatment, so that the stresses exerted by said heat treatment on the assembly of the support and the thin layer transferred. leaves said assembly intact, and in that it comprises an additional deposition step, on the thin wafer, of an additional thickness of the second material in the monocrystalline state.
Certains aspects préférés, mais non limitatifs, du procédé selon l'invention sont les suivants :Some preferred, but not limiting, aspects of the process according to the invention are the following:
* l'épaisseur de la couche mince transférée est comprise entre environ 100 et 300 Â, et de préférence entre 150 et 250 Â. * l'épaisseur du dépôt réalisé sur la couche mince transférée est compris entre environ 1000 et 5000 Â. * The thickness of the transferred thin layer is between about 100 and 300 Å, and preferably between 150 and 250 Å. * The thickness of the deposit produced on the thin transferred layer is between about 1000 and 5000 Å.
* l'étape de transfert de la couche mince du second matériau comprend les sous-étapes consistant à créer dans une plaquette donneuse, par implantation d'espèces, une zone de fragilisation délimitant la couche mince à transférer, à mettre en contact la plaquette donneuse avec le support, et à appliquer des contraintes aptes à mener au détachement de la couche mince par rapport au reste de la plaquette donneuse après la mise an contact. * The thin film step of transferring the second material comprises the sub-steps of creating a donor wafer by implantation of species, a zone of weakness which delimits the thin layer to be transferred, contacting the donor wafer with the support, and to apply constraints apt to lead to the detachment of the thin layer relative to the remainder of the donor wafer after contacting.
* le procédé comprend une étape supplémentaire de préparation de la surface libre de la couche mince, après détachement, pour réaliser le dépôt. The method comprises an additional step of preparing the free surface of the thin film after detachment, to achieve deposition.
* l'étape de dépôt est réalisée par épitaxie. * The step of depositing is carried out by epitaxy.
* le premier matériau est un isolant. * the first material is an insulator.
* le premier matériau est du quartz, tandis que le second matériau est du silicium. * le premier matériau est un semi-conducteur. * The first material is quartz, while the second material is silicon. * the first material is a semiconductor.
* le premier matériau est du silicium, tandis que le second matériau est du germanium. * The first material is silicon, while the second material is germanium.
* ledit traitement thermique est apte à engendrer dans la couche mince transférée un niveau acceptable de défauts liés à la différence entre les coefficients de dilatation thermique des premier et second matériaux. * Said heat treatment is apt to generate in the thin transferred layer an acceptable level of defects associated with the difference between the thermal expansion coefficients of the first and second materials.
D'autres aspects, buts et avantages de la présente invention apparaîtront mieux à la lecture de la description détaillée suivante de formes de réalisation préférées de celle-ci, donnée à titre d'exemple non limitatif et faite en référence aux dessins annexés, sur lesquels les figures 1A à 1 D illustrent schématiquement les étapes principales d'un procédé préféré de l'invention.Other aspects, objects and advantages of the present invention will appear better on reading the following detailed description of preferred embodiments thereof, given by way of nonlimiting example and with reference to the appended drawings, in which: Figures 1A-1D schematically illustrate the main steps of a preferred method of the invention.
On notera ici que les dimensions, en particulier épaisseurs relatives, montrées sur les figures ont été choisies par souci de clarté et ne sont pas censées illustrer la réalité des choses. En référence tout d'abord à la figure "IA, on a représenté un supportIt will be noted here that the dimensions, in particular relative thicknesses, shown in the figures have been chosen for the sake of clarity and are not meant to illustrate the reality of things. Referring firstly to Figure "IA, there is shown a support
10 et une plaquette donneuse 20 dans laquelle, par exemple par implantation ionique à travers une face 20a de la plaquette, on a réalisé une zone de fragilisation 21 délimitant une zone 22 de la plaquette 20 à transférer sur le support 10. A l'étape 1 B, le support 10 et la plaquette 20 sont assemblés et collés ensemble par adhésion moléculaire, une couche d'interface de collage (non représentée), telle qu'un oxyde ou un nitrure, étant éventuellement formée sur le support et/ou sur la plaquette. L'interface de collage est désignée par la référence 12.10 and a donor wafer 20 in which, for example by ion implantation through a face 20a of the wafer, an embrittlement zone 21 defining an area 22 of the wafer 20 to be transferred on the support 10 has been made. 1 B, the support 10 and the wafer 20 are assembled and glued together by molecular adhesion, a bonding interface layer (Not shown), such as an oxide or nitride, being optionally formed on the support and / or on the wafer. The bonding interface is designated by the reference 12.
L'ensemble subit alors un traitement thermique, en une ou plusieurs étapes, de manière d'une part à réaliser d'une part un détachement entre la zone 22 et le reste de la plaquette 20 au niveau de la zone de fragilisation, et d'autre part un renforcement de l'interface de collage entre le support 10 et la couche mince maintenant formée par la zone 22 détachée comme indiqué ci- dessus. La structure ainsi formée est illustrée sur la figure 1 C. Les étapes ci-dessus correspondent globalement au procédé Smart-The assembly then undergoes a heat treatment, in one or more steps, so as firstly to perform on the one hand a detachment between the zone 22 and the rest of the wafer 20 at the weakening zone, and on the other hand a strengthening of the bonding interface between the support 10 and the thin layer now formed by the zone 22 detached as indicated above. The structure thus formed is illustrated in FIG. 1C. The above steps generally correspond to the Smart-process.
Cut (B) exploité par la Demanderesse.Cut ( B ) operated by the Applicant.
La présente invention vise les situations où le matériau du support 10 et le matériau de la couche mince 22 présentent des coefficients de dilatation thermique suffisamment différents l'un de l'autre pour que les traitements thermiques précités ne puissent pas être mis en œuvre sans assister à une forme de détérioration de la structure composée du support 10 et de la couche mince 22, avec les éventuelles couches d'interface de collage.The present invention aims at situations in which the material of the support 10 and the material of the thin layer 22 have sufficiently different coefficients of thermal expansion from one another so that the aforementioned heat treatments can not be implemented without attending a form of deterioration of the composite structure of the support 10 and the thin layer 22, with any bonding interface layers.
Selon l'invention, on choisit pour l'épaisseur e1 de la couche transférée 22 une valeur faible, telle que les traitements thermiques précités laissent la structure sensiblement non affectée ; en d'autres termes, l'épaisseur de la couche 22 est choisie suffisamment faible pour ne pas provoquer de phénomènes de rupture, ou encore de phénomènes indésirables de déformation plastique, liée par exemple à des dislocations, glissements de plans atomiques, fissurations, etc. dans la couche 22. La surface libre de la couche 22 est ensuite préparée pour recevoir un dépôt du même matériau. Cette préparation peut comprendre un polissage mécano-chimique, une oxydation sacrificielle, une recuit thermique rapide (RTA pour « Rapid Thermal Annealing » en terminologie anglo- saxonne) ou encore un recuit au four, etc., l'objectif étant ici d'aboutir à une rugosité de la surface suffisamment faible. L'étape suivante du procédé, illustrée sur la figure 1 D, consiste à utiliser la couche 22 ainsi préparée comme couche germe pour procéder à un dépôt 22' du même matériau sur une épaisseur e2, par épitaxie, et réaliser un accroissement de l'épaisseur de la couche globale 220 (couche utile) du matériau constituant les couches 22 et 22' jusqu'à la valeur recherchée. L'épitaxie permet d'obtenir une très bonne qualité cristalline.According to the invention, a low value is chosen for the thickness e1 of the transferred layer 22, such that the aforementioned heat treatments leave the structure substantially unaffected; in other words, the thickness of the layer 22 is chosen sufficiently low not to cause rupture phenomena, or undesirable phenomena of plastic deformation, linked for example to dislocations, atomic plane shifts, cracks, etc. . in the layer 22. The free surface of the layer 22 is then prepared to receive a deposit of the same material. This preparation may comprise a chemical mechanical polishing, a sacrificial oxidation, a rapid thermal annealing (RTA for "Rapid Thermal Annealing" in English terminology) or an oven annealing, etc., the objective here being to achieve at a sufficiently low surface roughness. The next step of the process, illustrated in FIG. 1D, consists in using the layer 22 thus prepared as a seed layer for depositing the same material over a thickness e2, by epitaxy, and effecting an increase in the thickness of the overall layer 220 (useful layer) of the material constituting the layers 22 and 22 'up to the desired value. Epitaxy makes it possible to obtain a very good crystalline quality.
On observera ici que le choix de l'épaisseur e1 de la couche transférée 22 peut être tel qu'il existe un certain niveau densité de dislocations ou de plans de glissement dans l'hétéro-structure intermédiaire représentée à la figure 1 C et en particulier dans la couche transférée 22. En effet, ces défauts, après l'épitaxie de la couche 22', sont enterrés en profondeur dans la couche utile 220 et ne sont pas traversants.It will be observed here that the choice of the thickness e1 of the transferred layer 22 may be such that there is a certain density level of dislocations or sliding planes in the intermediate hetero-structure represented in FIG. 1C and in particular In fact, these defects, after the epitaxy of the layer 22 ', are buried deep in the useful layer 220 and are not through.
On observera en outre que la phase d'épaississement par dépôt épitaxial de la couche 22' permet de reporter au final des épaisseurs bien plus importantes que ce qu'il est possible de faire avec une technique de type Smart-Cut®, limitée de façon inhérente par la profondeur d'implantation possibleIt will further be observed that the phase of thickening by epitaxial deposition of the layer 22 'makes it possible to postpone in the end much greater thicknesses than is possible with a technique of the Smart-Cut® type, limited in a manner inherent by the possible depth of implantation
Exemple 1Example 1
Dans ce premier exemple, on cherche à réaliser une structure composée d'un support en quartz, par exemple d'une épaisseur de 1 ,2 mm, sur lequel repose une couche de silicium monocristallin d'une épaisseur pouvant atteindre 500 à 2000 Â pour des applications en micro-électronique, voire bien davantage pour d'autres applications tels que des dispositifs à couplage de charges (CCD pour « Charge Coupled Device » en terminologie anglo-saxonne).In this first example, it is sought to produce a structure composed of a quartz support, for example of a thickness of 1.2 mm, on which a monocrystalline silicon layer with a thickness of up to 500 to 2000 Å applications in microelectronics, or even more for other applications such as charge coupled devices (CCD) in English terminology.
L'expérimentation démontre que la température critique à partir de laquelle se manifestent des déformations plastiques excessives (dislocations, plans de glissement, etc.) dans une structure composée d'une couche mince de Si transférée selon le procédé Smart-Cut sur un support en quartz dépend de l'épaisseur de la couche transférée de la façon suivante : Epaisseur couche 22 Temp. CritiqueThe experiment demonstrates that the critical temperature from which excessive plastic deformations (dislocations, sliding planes, etc.) occur in a structure composed of a thin layer of Si transferred according to the Smart-Cut process on a support in quartz depends on the thickness of the layer transferred as follows: Thickness layer 22 Temp. Critical
2000 Â 750 °C2000 at 750 ° C
500 Â 950 °C 200 Â 1100 °C500 Å 950 ° C 200 Å 1100 ° C
Selon le présent exemple, on transfère sur le support 10 en quartz une couche de silicium monocristallin 22 d'une épaisseur de 200 Â, ce transfert mettant en jeu un renforcement de l'interface de collage par traitement thermique à 1050 °C pendant une durée d'environ deux heures. Grâce à l'épaisseur limitée de la couche 22, ce traitement thermique n'engendre aucune détérioration préjudiciable (fissuration ou rupture) de la structure. La surface libre de la couche mince 22 est ensuite préparée pour le dépôt par épitaxie du complément de silicium permettant de réaliser la couche utile monocristalline de l'épaisseur voulue. Cette épitaxie pour former la couche 22' également en silicium monocristallin est réalisée sur une épaisseur qui peut varier largement en fonction de l'application.According to the present example, a layer of monocrystalline silicon 22 having a thickness of 200 Å is transferred onto the quartz support 10, this transfer involving reinforcement of the bonding interface by heat treatment at 1050 ° C. for a period of time. about two hours. Due to the limited thickness of the layer 22, this heat treatment does not cause any detrimental deterioration (cracking or breaking) of the structure. The free surface of the thin layer 22 is then prepared for epitaxial deposition of the silicon complement making it possible to produce the monocrystalline useful layer of the desired thickness. This epitaxy to form the layer 22 'also monocrystalline silicon is made to a thickness that can vary widely depending on the application.
Ainsi, pour des applications en micro-électronique, l'épaisseur du dépôt est par exemple d'environ 800 à 1800 Â, pour aboutir à une épaisseur de couche utile d'environ 1000 à 2000 Â.Thus, for applications in microelectronics, the thickness of the deposit is for example about 800 to 1800 Å, resulting in a useful layer thickness of about 1000 to 2000 Å.
Pour des applications CCD, l'épaisseur globale recherchée est typiquement de 5 à 10 μm.For CCD applications, the overall thickness sought is typically 5 to 10 μm.
Exemple 2Example 2
On cherche à réaliser une structure de semiconducteur sur isolant comprenant un support en silicium (monocristallin ou polycristallin) et une couche utile épaisse en germanium monocristallin, par exemple pour des applications de composants photovoltaïques. On détermine les traitements thermiques nécessaires au détachement de la couche mince 22 de germanium par rapport à sa plaquette donneuse et au renforcement de l'interface de collage avec le support 10 en silicium.It is sought to provide a semiconductor-on-insulator structure comprising a silicon support (monocrystalline or polycrystalline) and a thick monocrystalline germanium thick layer, for example for photovoltaic component applications. The thermal treatments necessary for the detachment of the thin layer 22 of germanium with respect to its donor wafer and reinforcement of the bonding interface with the support 10 of silicon.
Typiquement, ces traitements comprennent une phase de détachement à une température d'environ 300 à 400 °C pendant une durée d'environ quelques minutes à deux heures, puis une phase de renforcement de l'interface de collage à une température d'environ 500 à 800 °C pendant une durée d'environ une heure.Typically, these treatments include a detachment phase at a temperature of about 300 to 400 ° C for a period of about a few minutes to two hours, and then a step of reinforcing the bonding interface at a temperature of about 500 at 800 ° C for a period of about one hour.
On détermine ensuite, expérimentalement, qu'une épaisseur de la couche mince 22 qui n'est pas supérieure à environ 200 Â permet d'appliquer ces traitements thermiques à la structure sans que ladite couche mince ne se détériore.It is then determined, experimentally, that a thickness of the thin layer 22 which is not greater than about 200 Å makes it possible to apply these heat treatments to the structure without said thin layer deteriorating.
On réalise ensuite sur la couche mince 22, après un traitement préparatoire à l'épitaxie tel qu'un polissage mécano-chimique, un dépôt de germanium monocristallin 22' venant se former dans la continuité de la couche 22 en termes de structure cristalline, et donc réaliser un épaississement de celle-ci. Dans le présent exemple, ce dépôt s'effectue sous une température d'environ 700 °C, et sur une épaisseur de 4800 Â, pour former au total une couche utile de germanium monocristallin d'une épaisseur de 5000 Â, voire davantage (jusqu'à 3 μm). Bien entendu, la présente invention n'est nullement limitée aux formes de réalisation décrites, et l'homme du métier saura y apporter de nombreuses variantes. Elle trouve application dès que l'on souhaite réaliser une hétérostructure comprenant au moins un matériau semi-conducteur et dans laquelle une couche rapportée doit présenter une épaisseur supérieure à celle autorisée par les données essentielles de départ que sont les traitements thermiques à subir et la différence entre les coefficients de dilatation thermique des deux matériaux. On citera notamment des structures d'InP sur Si et de GaAs sur Si.Then, on the thin layer 22, after a treatment preparatory to epitaxy, such as a chemical-mechanical polishing, a monocrystalline germanium deposit 22 'is formed which is formed in the continuity of the layer 22 in terms of crystalline structure, and therefore achieve a thickening thereof. In the present example, this deposition is carried out at a temperature of about 700 ° C., and at a thickness of 4800 Å, to form a total useful layer of monocrystalline germanium having a thickness of 5000 Å or more (up to at 3 μm). Of course, the present invention is not limited to the embodiments described, and the skilled person will be able to make many variations. It finds application as soon as it is desired to produce a heterostructure comprising at least one semiconductor material and in which an added layer must have a thickness greater than that authorized by the essential starting data which are the heat treatments to be undergone and the difference between the coefficients of thermal expansion of the two materials. In particular, structures of InP on Si and GaAs on Si will be mentioned.
On notera également que la couche mince transférée peut être contrainte, en tension ou en compression, l'épaisseur supplémentaire de matériau apportée par dépôt préservant cette contrainte. Ceci permet des couches contraintes épaisses, les contraintes étant assurées sur des épaisseurs de plusieurs dizaines de nanomètres, voire jusqu'à quelques centaines de nanomètres selon le niveau de contrainte que l'on souhaite préserver. It will also be noted that the transferred thin film may be constrained, in tension or in compression, by the additional thickness of deposited material preserving this stress. This allows thick stress layers, the stresses being ensured on thicknesses of several tens of nanometers, or even up to a few hundred nanometers depending on the level of stress that one wishes to preserve.

Claims

REVENDICATIONS
1. Procédé de fabrication d'une structure comprenant au moins un matériau semiconducteur pour des applications en micro-électronique, opto- électronique, optique, etc., le procédé comprenant le transfert sur un support (10) en un premier matériau d'une couche mince monocristalline (22) en un second matériau différent du premier, ainsi qu'un traitement thermique prédéterminé réalisant au moins un renforcement d'une interface de collage (12) entre la couche mince et le support, caractérisé en ce que l'épaisseur (e1 ) de la couche mince est choisie en fonction de la différence entre les coefficients de dilatation thermique des premier et second matériaux et en fonction des paramètres dudit traitement thermique prédéterminé, de telle sorte que les contraintes exercées par ledit traitement thermique sur l'assemblage du support et de la couche mince transférée laisse ledit assemblage intact, et en ce qu'il comprend une étape supplémentaire de dépôt, sur la couche mince, d'une épaisseur supplémentaire (22') du second matériau à l'état monocristallin.A method of manufacturing a structure comprising at least one semiconductor material for microelectronic, optoelectronic, optical, etc. applications, the method comprising transferring on a carrier (10) a first material of a monocrystalline thin layer (22) in a second material different from the first, and a predetermined heat treatment providing at least one reinforcement of a bonding interface (12) between the thin layer and the support, characterized in that the thickness (e1) of the thin layer is chosen according to the difference between the thermal expansion coefficients of the first and second materials and according to the parameters of said predetermined heat treatment, so that the stresses exerted by said heat treatment on the assembly of the support and of the transferred thin film leaves said assembly intact, and in that it comprises an additional step of depositing, on the couch e thin, of an additional thickness (22 ') of the second material in the monocrystalline state.
2. Procédé selon la revendication 1 , caractérisé en ce que l'épaisseur (e1 ) de la couche mince transférée est comprise entre environ2. Method according to claim 1, characterized in that the thickness (e1) of the transferred thin film is between about
100 et 300 Â, et de préférence entre 150 et 250 Â.100 and 300 Å, and preferably between 150 and 250 Å.
3. Procédé selon la revendication 2, caractérisé en ce que l'épaisseur (e2) du dépôt (22') réalisé sur la couche mince transférée (22) est compris entre environ 1000 et 5000 Â.3. Method according to claim 2, characterized in that the thickness (e2) of the deposit (22 ') formed on the transferred thin layer (22) is between about 1000 and 5000 Å.
4. Procédé selon l'une des revendications 1 à 3, caractérisé en ce que l'étape de transfert de la couche mince (22) du second matériau comprend les sous-étapes consistant à créer dans une plaquette donneuse (20), par implantation d'espèces, une zone de fragilisation (21 ) délimitant la couche mince à transférer, à mettre en contact la plaquette donneuse avec le support, et à appliquer des contraintes aptes à mener au détachement de la couche mince par rapport au reste de la plaquette donneuse après la mise an contact.4. Method according to one of claims 1 to 3, characterized in that the step of transferring the thin layer (22) of the second material comprises the substeps of creating in a donor wafer (20), by implantation of species, an embrittlement zone (21) delimiting the thin layer to be transferred, bringing the donor wafer into contact with the support, and to apply stresses capable of leading to detachment of the thin layer relative to the remainder of the donor wafer after contacting.
5. Procédé selon la revendication 4, caractérisé en ce qu'il comprend une étape supplémentaire de préparation de la surface libre de la couche mince (22), après détachement, pour réaliser le dépôt (22').5. Method according to claim 4, characterized in that it comprises an additional step of preparing the free surface of the thin layer (22), after detachment, to perform the deposition (22 ').
6. Procédé selon l'une des revendications 1 à 5, caractérisé en ce que l'étape de dépôt est réalisée par épitaxie.6. Method according to one of claims 1 to 5, characterized in that the deposition step is carried out by epitaxy.
7. Procédé selon l'une des revendications 1 à 6, caractérisé en ce que le premier matériau est un isolant.7. Method according to one of claims 1 to 6, characterized in that the first material is an insulator.
8. Procédé selon la revendication 7, caractérisé en ce que le premier matériau est du quartz.8. Method according to claim 7, characterized in that the first material is quartz.
9. Procédé selon la revendication 8, caractérisé en ce que le second matériau est du silicium.9. The method of claim 8, characterized in that the second material is silicon.
10. Procédé selon l'une des revendications 1 à 6, caractérisé en ce que le premier matériau est un semi-conducteur.10. Method according to one of claims 1 to 6, characterized in that the first material is a semiconductor.
11. Procédé selon la revendication 10, caractérisé en ce que le premier matériau est du silicium.11. The method of claim 10, characterized in that the first material is silicon.
12. Procédé selon la revendication 11 , caractérisé en ce que le second matériau est du germanium.12. The method of claim 11, characterized in that the second material is germanium.
13. Procédé selon l'une des revendications 1 à 12, caractérisé en ce que ledit traitement thermique est apte à engendrer dans la couche mince transférée (22) un niveau acceptable de défauts liés à la différence entre les coefficients de dilatation thermique des premier et second matériaux. 13. Method according to one of claims 1 to 12, characterized in that said heat treatment is capable of generating in the thin layer transferred (22) an acceptable level of defects related to the difference between the coefficients of thermal expansion of the first and second materials.
EP06725289A 2005-03-24 2006-03-23 Method of producing a hetero-structure comprising at least one thick layer of semiconductor material Withdrawn EP1861873A1 (en)

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