EP1820275A4 - Codeur et decodeur ldpc et procedes de codage et de decodage ldpc - Google Patents

Codeur et decodeur ldpc et procedes de codage et de decodage ldpc

Info

Publication number
EP1820275A4
EP1820275A4 EP05821430A EP05821430A EP1820275A4 EP 1820275 A4 EP1820275 A4 EP 1820275A4 EP 05821430 A EP05821430 A EP 05821430A EP 05821430 A EP05821430 A EP 05821430A EP 1820275 A4 EP1820275 A4 EP 1820275A4
Authority
EP
European Patent Office
Prior art keywords
ldpc
decoder
decoding methods
encoder
encoding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP05821430A
Other languages
German (de)
English (en)
Other versions
EP1820275A1 (fr
Inventor
Sang Hyun Lee
Jae Young Ahn
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Electronics and Telecommunications Research Institute ETRI
Original Assignee
Electronics and Telecommunications Research Institute ETRI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020050063905A external-priority patent/KR100641052B1/ko
Application filed by Electronics and Telecommunications Research Institute ETRI filed Critical Electronics and Telecommunications Research Institute ETRI
Publication of EP1820275A1 publication Critical patent/EP1820275A1/fr
Publication of EP1820275A4 publication Critical patent/EP1820275A4/fr
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1168—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices wherein the sub-matrices have column and row weights greater than one, e.g. multi-diagonal sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/615—Use of computational or mathematical techniques
    • H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6356—Error control coding in combination with rate matching by repetition or insertion of dummy data, i.e. rate reduction
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H03M13/6516—Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields
EP05821430A 2004-12-08 2005-12-07 Codeur et decodeur ldpc et procedes de codage et de decodage ldpc Ceased EP1820275A4 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR20040103240 2004-12-08
KR1020050063905A KR100641052B1 (ko) 2004-12-08 2005-07-14 Ｌｄｐｃ 부호기 및 복호기, 및 ｌｄｐｃ 부호화 방법 및복호화 방법
PCT/KR2005/004177 WO2006062351A1 (fr) 2004-12-08 2005-12-07 Codeur et decodeur ldpc et procedes de codage et de decodage ldpc

Publications (2)

Publication Number Publication Date
EP1820275A1 EP1820275A1 (fr) 2007-08-22
EP1820275A4 true EP1820275A4 (fr) 2009-11-25

Family

ID=36578137

Family Applications (1)

Application Number Title Priority Date Filing Date
EP05821430A Ceased EP1820275A4 (fr) 2004-12-08 2005-12-07 Codeur et decodeur ldpc et procedes de codage et de decodage ldpc

Country Status (2)

Country Link
EP (1) EP1820275A4 (fr)
WO (1) WO2006062351A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110087268A (ko) 2008-09-26 2011-08-02 에이전시 포 사이언스, 테크놀로지 앤드 리서치 디코딩 회로 및 인코딩 회로
JP4898858B2 (ja) 2009-03-02 2012-03-21 パナソニック株式会社 符号化器、復号化器及び符号化方法
WO2014117836A1 (fr) * 2013-01-31 2014-08-07 Intracom S.A. Telecom Solutions Conception de codes ldpc et appareil de codage permettant le réglage du débit de codes et de la longueur de code
JP6798004B2 (ja) * 2016-07-20 2020-12-09 ホアウェイ・テクノロジーズ・カンパニー・リミテッド Ｌｄｐｃ符号の符号化および復号化のための方法およびシステム
AU2018294852B2 (en) * 2017-06-25 2021-07-22 Lg Electronics Inc. Method for performing encoding on basis of parity check matrix of LDPC code in wireless communication system and terminal using same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040064776A1 (en) * 2002-09-30 2004-04-01 Yedidia Jonathan S. Transforming generalized parity check matrices for error-correcting codes
EP1480346A1 (fr) * 2002-02-28 2004-11-24 Mitsubishi Denki Kabushiki Kaisha Procede de generation de matrices d'inspection de code ldpc et dispositif de generation de matrices d'inspection
EP1610466A1 (fr) * 2004-06-22 2005-12-28 Infineon Technologies AG Décodeur LPDC pour décoder des codes de controle de parité de faible densité

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2457420C (fr) * 2002-07-03 2016-08-23 Hughes Electronics Corporation Etiquetage de bit de constellation de decalage de phase et d'amplitude utilise pour des codes de controle de parite faible densite
US7702986B2 (en) * 2002-11-18 2010-04-20 Qualcomm Incorporated Rate-compatible LDPC codes
JP4224777B2 (ja) * 2003-05-13 2009-02-18 ソニー株式会社 復号方法および復号装置、並びにプログラム

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1480346A1 (fr) * 2002-02-28 2004-11-24 Mitsubishi Denki Kabushiki Kaisha Procede de generation de matrices d'inspection de code ldpc et dispositif de generation de matrices d'inspection
US20040064776A1 (en) * 2002-09-30 2004-04-01 Yedidia Jonathan S. Transforming generalized parity check matrices for error-correcting codes
EP1610466A1 (fr) * 2004-06-22 2005-12-28 Infineon Technologies AG Décodeur LPDC pour décoder des codes de controle de parité de faible densité

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
ANDREWS K; DOLINAR S; POLLARA F: "LPDC decoding using multiple representations", PROC., IEEE INTERNATIONAL SYMPOSIUM ON INFORMATION THEORY, ISIT 02, LAUSANNE, SWITZERLAND, 30 June 2002 (2002-06-30) - 5 July 2002 (2002-07-05), pages 456 - 456, XP010602167 *
CLASSON B; ET AL: "LDPC coding for OFDMA PHY", INTERNET CITATION, 17 August 2004 (2004-08-17), XP002371218, Retrieved from the Internet <URL:http://ieee802.org/16> *
KOU Y.; LIN S. ; FOSSORIER M.P.C.: "Low-Density Parity-Check Codes Based on Finite Geometries: A Rediscovery and New Results", IEEE TRANSACTIONS ON INFORMATION THEORY, IEEE, US, no. 7, 1 November 2001 (2001-11-01), XP011028087, ISSN: 0018-9448 *
See also references of WO2006062351A1 *
SHASHA E; LITSYN S; SHARON E: "Multi-Rate LDPC code for OFDMA PHY", INTERNET CITATION, 25 June 2004 (2004-06-25), XP002334837, Retrieved from the Internet <URL:http://www.ieee802.org/16/tge/contrib/C80216e-04_185.pdf> *
WILSON S G: "Linear block codes", DIGITAL MODULATION AND CODING, 1 January 1996 (1996-01-01), pages 411 - 425,470, XP002275914 *

Also Published As

Publication number Publication date
WO2006062351A1 (fr) 2006-06-15
EP1820275A1 (fr) 2007-08-22

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