EP1805799A1 - Substrate with electric contacts and method of manufacturing the same - Google Patents
Substrate with electric contacts and method of manufacturing the sameInfo
- Publication number
- EP1805799A1 EP1805799A1 EP05794401A EP05794401A EP1805799A1 EP 1805799 A1 EP1805799 A1 EP 1805799A1 EP 05794401 A EP05794401 A EP 05794401A EP 05794401 A EP05794401 A EP 05794401A EP 1805799 A1 EP1805799 A1 EP 1805799A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- contact pads
- substrate
- contact
- solder
- metallic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/019—Manufacture or treatment of bond pads
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09436—Pads or lands on permanent coating which covers the other conductors
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09745—Recess in conductor, e.g. in pad or in metallic substrate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07231—Techniques
- H10W72/07236—Soldering or alloying
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/241—Dispositions, e.g. layouts
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/241—Dispositions, e.g. layouts
- H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/241—Dispositions, e.g. layouts
- H10W72/247—Dispositions of multiple bumps
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/251—Materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/251—Materials
- H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/29—Bond pads specially adapted therefor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/951—Materials of bond pads
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
- H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- the invention relates to a substrate with a first surface comprising first metallic contact pads separated by insulating areas inbetween them, which first contact pads and second contact pads on a second surface of a second substrate are to be soldered together, wherein said first contact pads on said substrate and corresponding second contact pads on the second substrate face each other.
- the invention furthermore relates to an electronic device comprising a substrate with a first surface comprising first metallic contact pads, and a second substrate with a second surface comprising second metallic contact pads, wherein first contact pads and second contact pads are soldered together, and wherein first contact pads on the first substrate and corresponding second contact pads on the second substrate face each other.
- the invention relates to a method of manufacturing such a substrate.
- a die carrying an electronic circuit comprises also contact pads to connect the die to a "support” substrate with the well-known "Flip Chip Technology”.
- Flip Chip refers to an electronic component or semiconductor device that can be mounted directly onto a substrate, board, or carrier in a 'face-down' manner. Electrical connection is achieved through conductive bumps built on the surface of the chips, which is why the mounting process is by nature 'face-down'. During mounting, the chip is flipped on the substrate, board, or carrier, (hence the name 'flip-chip'), with the bumps being precisely positioned on their target locations. Because flip chips do not require wirebonds, they occupy less space on the substrate than their conventional wirebonded counterparts. The flip chip is structurally different from traditional semiconductor packages, and therefore requires an assembly process that also differs from conventional semiconductor assembly.
- Flip chip assembly consists of three major steps: 1) bumping of the chips; 2) 'face ⁇ down' attachment of the bumped chips to the substrate or board; and 3) underfilling, which is the process of filling the open spaces between the chip and the substrate or board with a non- conductive, mechanically protective material.
- underfilling is the process of filling the open spaces between the chip and the substrate or board with a non- conductive, mechanically protective material.
- UBM underbump metallization
- the UBM preferably consists of electroless NiAu, which has a good solder wettability, but also other material combinations are applicable.
- electroless NiPdAu One alternative, which is used for rather high temperatures, is electroless NiPdAu.
- the UBM process removes the passivating oxide layer on the bond pad and defines the solder- wetted area. Solder may then be deposited over the UBM by a suitable method, e.g. evaporation, electroplating, screen-printing, or dispensing.
- solder paste For low-cost wafer bumping, stencil printing of solder paste has been implemented and has gained much interest for flip chip soldering. Besides cost efficiency, different solder pastes including lead- free alloys are available. However, due to available solder pastes and stencil geometries, at present this process is limited in pitch down to 200 ⁇ m for high volumes and 150 ⁇ m for tests.
- ISB Industrial Solder Bumping
- pads which normally have a size of 100 ⁇ m down to very fine pitches of 40 ⁇ m.
- the wafer is immersed in liquid solder, the UBM is wetted, and a small solder cap is formed on top of the UBM.
- the solder cap height depends strongly on pad size.
- An organic liquid above the liquid solder surface prevents oxidation of solder and improves wettability. After soldering, residues can be easily removed.
- the process in itself has no restrictions with respect to wafer size. It is even possible to treat single dies. The process has also been modified to suit the demands of lead- free solders. Different solder materials are available such as PbSn63, SnBi42, SnAg3.5, SnCuO.7.
- thermode bonder i.e., a pick and placement tool
- the placement head of the thermode bonder can be used to supply the flip chip device with energy with the aim of providing sufficient heat to complete the refiow process.
- Immersion solder bumping of low-melting soft solder in combination with rapid thermode bonding could be an alternative to the smart tag adhesive technology.
- a flip chip device is underfilled.
- substrate as used herein not only covers the meaning that it has in the Flip Chip Technology but also covers a die comprising an electronic circuit. The differentiation between “substrate” and “die” with respect to chip production is not applicable for the invention. Everytime the term “substrate” is needed in its chip-related sense, the term “support substrate” is used instead.
- underbump metallization when using the corresponding process, is referenced as "metallic contact pad” here for reasons of a general language. This general language is used since the invention is neither limited to the Flip Chip Technology nor to an UBM- or an ISB-process.
- Figure Ia shows a cross section of a prior art substrate 40
- Figure Ib shows a corresponding top view.
- Substrate 40 could be a part of a larger electronic circuit, thus
- Figure Ia and Ib only show a cut-out of such an electronic circuit, which normally comprises a number of those parts.
- Said substrate 40 comprises a first metallic bond pad 41 on a first surface.
- a first insulating layer 42 is arranged, which also covers the border area of the first metallic bond pad 41, thus forming a cylindrical groove on the upper side of the first bond pad 41.
- a first contact pad 43 On the first metallic bond pad 41 there is arranged a first contact pad 43, which itself juts out from said first insulating layer 42. Because of the cylindrical groove, first contact pad 43 has a raised edge.
- a solder bump 44 is provided on the first contact pad 43.
- the height Hpr of the solder bump 44 depends on the diameter Dpr of the first contact pad 43 and is typically about 0.3 times said diameter Dpr.
- the arrangement shown in Figures Ia and Ib normally is an intermediate product. For this example it is assumed that said arrangement is part of a die comprising an electronic circuit.
- FIG. 2 shows an arrangement where the part of Figure Ia and an identical mirror-inverted part are soldered together.
- Said mirrored part comprises a second substrate 50 with a second metallic bond pad 51 on a second surface.
- a second insulating layer 52 is arranged, which also covers the border area of the second metallic bond pad 51, thus forming a cylindrical groove on the lower side of the second bond pad 51.
- a second contact pad 53 Under the second metallic bond pad 51 there is arranged a second contact pad 53, which itself juts out from said second insulating layer 52. Because of the cylindrical groove, the second contact pad 53 has a raised edge.
- a separate solder bump 44 is omitted, since there is solder already on the first contact pad 43.
- first and second contact pad 43 and 53 are sucked together through the surface tension of the solder.
- Figure 2 shows that the connection of the two parts results in a so-called stand off Xpr, i.e., a distance between contact pads 43 and 53.
- This stand off Xpr also depends on the diameter Dpr of first contact pad 43 and is typically about 0.15 times said diameter Dpr. In this example, identical diameters for the first and the second contact pad 43 and 53 are assumed. Different diameters of course would lead to a different result.
- the concrete value of the "zero stand off does not only depend on the size of the contact pads but also on their surface. Hence, a fine structured surface leads to a smaller value than a rough surface.
- the process of soldering can furthermore be performed with a small or without any force effect, which also influences said value.
- contact pads should have a certain size at least so that they are easy to manufacture. Said range runs from 5 ⁇ m to 20 ⁇ m which is advantageous in particular for the UBM and ISB processes. • Electroless NiAu for instance has already been performed on pads with dimensions down to 7 • ⁇ m, which is of course not to be interpreted as a "physical" lower limit. It might be possible to produce smaller NiAu contact pads in the near future. However, these small dimensions put new demands on the bath that is being used for this process. Hence a "practical" lower value for the pad diameter is considered to be 5 ⁇ m.
- first contact pads have a raised edge.
- intermetallics are formed where the solder contacts the metal of the contact pad. These intermetallics hinder the zero stand off, since the tendency of "sucking together" the parts involved is not as strong as necessary.
- said intermetallics are mainly formed in the center, i.e., the groove of the contact pads. Therefore they do not essentially hamper the close approximation of two contact pads.
- the substrate comprises solder bumps on first contact pads, because the first substrate is then prepared to be soldered to a second substrate also comprising second metallic contact pads.
- the solder bumps are preferably manufactured using an ISB process but are not limited thereto.
- An alternative to the aforesaid ISB is wave soldering, which can also be used for the concerns of the invention. Further applicable technologies are stencil printing as well as plating, which both are relatively expensive compared to ISB. It should also be noted here that soldering does not depend on the use of an underbump metallization. Soldering can rather be accomplished with any contact pad.
- solder bump consists of a low melting solder.
- a substrate can consist of a temperature-sensitive material such as paper or plastic.
- solders which melt below 100°C.
- US 6,740,544, "Solder compositions for attaching a die to a substrate", dated May 25, 2004 is referenced, in particular table 1, column 6.
- the document discloses a possibility to raise the melting point of a solder through so-called ,,solder agents”. Said document is herewith incorporated by reference. The aforesaid method is especially advantageous when a device is operated under a higher environmental temperature condition.
- first metallic contact pads form an electric contact.
- One single contact pad which preferably has a size between 5 ⁇ m and 20 ⁇ m, is only able to drive a certain current. If the necessary current resulting from a certain design of an electronic circuit exceeds said limit, it is possible to form an electric contact comprising more adjacent first metallic contact pads. In this way an electric contact can drive any wanted current without increasing the stand-off. It should be mentioned at this point that " the contact pads do not necessarily have to be in the vicinity of each other. It is also imaginable that there are metallic contact pads of another electric contact inbetween them.
- the object of the invention is furthermore achieved by an electronic device comprising a substrate with a first surface having first metallic contact pads, and a second substrate with a second surface having second metallic contact pads, wherein first contact pads and second contact pads are soldered together, wherein first contact pads on the first substrate and corresponding second contact pads on the second substrate face each other, and wherein the greatest planar extension of said first and second contact pads with respect to said first and second surface does not exceed 20 ⁇ m.
- the object of the invention is also achieved by a method of manufacturing a substrate with a first surface comprising first metallic contact pads through an underbump metallization process, short UBM, wherein the greatest planar extension of said first contact pads with respect to said first surface does not exceed 20 ⁇ m.
- Figure Ia is a cross sectional view of a prior art substrate
- Figure Ib is a top view of the substrate of Figure Ia;
- Figure 2 is a cross sectional view of a prior art electronic device
- Figure 3a is a cross sectional view of an inventive substrate
- Figure 3b is a top view of the substrate of Figure 3a
- Figure 4 is a cross sectional view of an inventive electronic device
- Figure 5 shows the relation between pad diameter and bump height as well as between pad diameter and stand off;
- Figure 6 shows a contact pad in the form of a pentagon.
- FIG. 3 a shows the cross section of an inventive substrate 10
- Figure 3b shows the corresponding top view.
- Substrate 10 could be a part of a larger electronic circuit, thus Figure Ia and Ib only show a cutout of such an electronic circuit, which normally comprises a number of those parts.
- Said substrate 10 comprises a first metallic bond pad 11 (e.g. made of Cu, Ni, Co, Nb, etc.) on a first surface.
- a first insulating layer 12 is arranged, which also covers the border area of the first metallic bond pad 11.
- Insulating layer 12 forms four cylindrical grooves on the upper side of the first bond pad 11.
- first contact pads 13a..13d are arranged on the first metallic bond pad 11 and in the grooves there are arranged four first contact pads 13a..13d, which jut out from said first insulating layer 12. Because of the cylindrical groove, first contact pads 13a..13d have raised edges.
- solder bumps 14a..14d are provided on first contact pads 13a..13d.
- the height Hin of the solder bumps 14a..14d depends on the diameter Din of the first contact pads 13a..13d and is about 0.3 times said diameter Din.
- the arrangement shown in Figures Ia and Ib normally is an intermediate product. For this example it is assumed that said arrangement is part of a die comprising an electronic circuit.
- this die is flip chip mounted on a support substrate.
- a part of this support substrate is shown in Figure 4.
- Figure 4 shows an arrangement where the part of Figure 3a and an identical mirror-inverted part are soldered together.
- Said mirrored part comprises a second substrate 20 with a second metallic bond pad 21 on a second surface.
- a second insulating layer 22 is arranged, which also covers the border area of the second metallic bond pads 21.
- cylindrical grooves are formed in the lower side of the second bond pad 21.
- second contact pads 23a..23d 23c and 23d not shown due to the cross sectional view
- second contact pads 23a..23d have raised edges. Separate solder bumps 24a..24d are omitted since there already is solder on the first contact pads 13a..13d.
- first and second contact pads 13a..13d and 23a..23d are sucked together through the surface tension of the solder bumps 14a..14d.
- Figure 4 shows that the connection of the two parts results in a stand off Xin, i.e., the distance between contact pads 13a..13d and 23a..23d.
- Figure 4 shows that the stand off Xin surprisingly is zero or almost zero although the diameter between contact pads 13a..13d and 23a..23d is greater than zero.
- the height of a solder bump 14a..14d; 44 does not only depend on the pad diameter Din but also on the shape of a contact pad 13a..13d; 14a..14d; 43; 44.
- Figure 6 shows an example of a first contact pad 73, which is polygon shaped, more precisely pentagon shaped. It should be noted here that the first contact pad 73 only serves as an example. Hence, a multitude of forms is imaginable for the first contact pad 73, for instance a triangle, a rectangle (especially a quadratic one), a hexagon as well as an octagon. Furthermore, elliptic, oval and kidney-shaped forms are possible, for example. Figure 6 now shows that such a first contact pad 73 has a greatest planar extension Din and a smallest planar extension din, which preferably are in the range from 20 ⁇ m to 5 ⁇ m.
- first contact pads 13a..13d form a single electric contact. In fact the invention is also applicable to cases where one single first contact pad 13a..13d forms an electric contact. Furthermore, it is not mandatory that first contact pads 13a..13d are manufactured through a UBM process or are shaped like a UBM. A first contact pad 13a..13d could rather be a flat object on a first surface of first substrate 10 or even be embedded in it. It should further be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be capable of designing many alternative embodiments without departing from the scope of the invention as defined by the appended claims.
- any reference signs placed in parentheses shall not be construed as limiting the claims.
- the word “comprising” and “comprise(s)”, and the like, does not exclude the presence of elements or steps other than those listed in any claim or the specification as a whole.
- the singular reference of an element does not exclude the plural reference of such elements and vice- versa.
- a device claim enumerating several means several of these means may be embodied by one and the same item of hardware.
- the mere . fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
A substrate (10) with first metallic contact pads (13a..13d) is disclosed, which first contact pads (13a..13d) and second contact pads (23a..23d) on a second substrate (20) are to be soldered together. According to the invention, the greatest planar extension (Din) of said first contact pads (13a..13d) with respect to said first surface does not exceed 20 µm. Thus, a stand off Xin of zero or almost zero can be achieved when the first substrate (10) and the second substrate (20) are soldered together. This method for instance is applicable to the flip chip technology, wherein preferably 'underbump metallization', UBM for short, and 'Immersion solder bumping', ISB for short, are used for manufacturing said substrate (10).
Description
Substrate with electric contacts and method of manufacturing the same
FIELD OF THE INVENTION
The invention relates to a substrate with a first surface comprising first metallic contact pads separated by insulating areas inbetween them, which first contact pads and second contact pads on a second surface of a second substrate are to be soldered together, wherein said first contact pads on said substrate and corresponding second contact pads on the second substrate face each other.
The invention furthermore relates to an electronic device comprising a substrate with a first surface comprising first metallic contact pads, and a second substrate with a second surface comprising second metallic contact pads, wherein first contact pads and second contact pads are soldered together, and wherein first contact pads on the first substrate and corresponding second contact pads on the second substrate face each other.
Finally, the invention relates to a method of manufacturing such a substrate.
BACKGROUND OF THE INVENTION Said substrates are widely used in the state of the art. For instance, a die carrying an electronic circuit comprises also contact pads to connect the die to a "support" substrate with the well-known "Flip Chip Technology".
The term "Flip Chip" refers to an electronic component or semiconductor device that can be mounted directly onto a substrate, board, or carrier in a 'face-down' manner. Electrical connection is achieved through conductive bumps built on the surface of the chips, which is why the mounting process is by nature 'face-down'. During mounting, the chip is flipped on the substrate, board, or carrier, (hence the name 'flip-chip'), with the bumps being precisely positioned on their target locations. Because flip chips do not require wirebonds, they occupy less space on the substrate than their conventional wirebonded counterparts. The flip chip is structurally different from traditional semiconductor packages, and therefore requires an assembly process that also differs from conventional semiconductor assembly. Flip chip assembly consists of three major steps: 1) bumping of the chips; 2) 'face¬ down' attachment of the bumped chips to the substrate or board; and 3) underfilling, which is the process of filling the open spaces between the chip and the substrate or board with a non-
conductive, mechanically protective material. Given the many different materials and technologies used in the bumping, attachment, and underfilling steps, the flip chip exists in a vast array of variants.
One of the many known processes for flip-chip bumping comprises placing a so- called "underbump metallization", UBM for short, over the bond pad by means of sputtering, plating, printing, or a similar process. Of course, combinations thereof are possible as well. The UBM preferably consists of electroless NiAu, which has a good solder wettability, but also other material combinations are applicable. One alternative, which is used for rather high temperatures, is electroless NiPdAu. The UBM process removes the passivating oxide layer on the bond pad and defines the solder- wetted area. Solder may then be deposited over the UBM by a suitable method, e.g. evaporation, electroplating, screen-printing, or dispensing.
For low-cost wafer bumping, stencil printing of solder paste has been implemented and has gained much interest for flip chip soldering. Besides cost efficiency, different solder pastes including lead- free alloys are available. However, due to available solder pastes and stencil geometries, at present this process is limited in pitch down to 200 μm for high volumes and 150 μm for tests.
One further method is the so-called "Immersion Solder Bumping", ISB for short, which can be used as a low-cost alternative to electroplating. ISB can be used for pads, which normally have a size of 100 μm down to very fine pitches of 40 μm. With ISB the wafer is immersed in liquid solder, the UBM is wetted, and a small solder cap is formed on top of the UBM. The solder cap height depends strongly on pad size. An organic liquid above the liquid solder surface prevents oxidation of solder and improves wettability. After soldering, residues can be easily removed. The process in itself has no restrictions with respect to wafer size. It is even possible to treat single dies. The process has also been modified to suit the demands of lead- free solders. Different solder materials are available such as PbSn63, SnBi42, SnAg3.5, SnCuO.7.
This entire process of solder bumping normally is performed at wafer level. Solder-bumped wafers are subsequently sawn into individual flip-chips that get mounted on a board or substrate by subjecting the assembly to a temperature that is high enough to melt the solder, thereby forming the interconnection. For this purpose a thermode bonder, i.e., a pick and placement tool, is used. The placement head of the thermode bonder can be used to supply the flip chip device with energy with the aim of providing sufficient heat to complete the refiow process. Immersion solder bumping of low-melting soft solder in combination with rapid thermode bonding could be an alternative to the smart tag adhesive technology.
Finally, a flip chip device is underfilled. This is often achieved by needle dispensation along the edges of the flip-chip. Capillary action then draws the dispensed underfill inwards, until the open spaces are filled. Thermal curing is then performed to form the permanent bond. It has to be noted that the term "substrate" as used herein not only covers the meaning that it has in the Flip Chip Technology but also covers a die comprising an electronic circuit. The differentiation between "substrate" and "die" with respect to chip production is not applicable for the invention. Everytime the term "substrate" is needed in its chip-related sense, the term "support substrate" is used instead. Furthermore, it should be considered that what normally is called "underbump metallization" when using the corresponding process, is referenced as "metallic contact pad" here for reasons of a general language. This general language is used since the invention is neither limited to the Flip Chip Technology nor to an UBM- or an ISB-process.
Figure Ia shows a cross section of a prior art substrate 40, Figure Ib shows a corresponding top view. Substrate 40 could be a part of a larger electronic circuit, thus
Figure Ia and Ib only show a cut-out of such an electronic circuit, which normally comprises a number of those parts.
Said substrate 40 comprises a first metallic bond pad 41 on a first surface. Above substrate 40 a first insulating layer 42 is arranged, which also covers the border area of the first metallic bond pad 41, thus forming a cylindrical groove on the upper side of the first bond pad 41. On the first metallic bond pad 41 there is arranged a first contact pad 43, which itself juts out from said first insulating layer 42. Because of the cylindrical groove, first contact pad 43 has a raised edge. Finally, a solder bump 44 is provided on the first contact pad 43. The height Hpr of the solder bump 44 depends on the diameter Dpr of the first contact pad 43 and is typically about 0.3 times said diameter Dpr. The arrangement shown in Figures Ia and Ib normally is an intermediate product. For this example it is assumed that said arrangement is part of a die comprising an electronic circuit.
To complete an electronic device 60, this die is flip chip mounted on a support substrate. A part of this prior art support substrate is shown in Figure 2. Figure 2 shows an arrangement where the part of Figure Ia and an identical mirror-inverted part are soldered together. Said mirrored part comprises a second substrate 50 with a second metallic bond pad 51 on a second surface. Below the second substrate 50 a second insulating layer 52 is arranged, which also covers the border area of the second metallic bond pad 51, thus forming a cylindrical groove on the lower side of the second bond pad 51. Under the second metallic
bond pad 51 there is arranged a second contact pad 53, which itself juts out from said second insulating layer 52. Because of the cylindrical groove, the second contact pad 53 has a raised edge. A separate solder bump 44 is omitted, since there is solder already on the first contact pad 43. When both parts are soldered together, first and second contact pad 43 and 53 are sucked together through the surface tension of the solder. Figure 2 shows that the connection of the two parts results in a so-called stand off Xpr, i.e., a distance between contact pads 43 and 53. This stand off Xpr also depends on the diameter Dpr of first contact pad 43 and is typically about 0.15 times said diameter Dpr. In this example, identical diameters for the first and the second contact pad 43 and 53 are assumed. Different diameters of course would lead to a different result.
In line with the common trend of minimizing the size of electronic devices, there are also endeavors to minimize said stand off Xpr. But, since a contact pad has to have a certain size also the stand off has a certain size.
OBJECT AND SUMMARY OF THE INVENTION
It is an object of the invention to find a solution, which provides a stand off of zero, or approximately zero.
This object is achieved by a substrate of the aforesaid kind, wherein the greatest planar extension of said first contact pads with respect to said first surface does not exceed 20 μm. It has surprisingly been found that a zero stand off or a near zero stand off is achievable not only when first contact pads have a zero size (which would be senseless of course), but also when they do not exceed a certain size, namely 20 μm. The diagram of Figure 5 illustrates said effect. The diagram shows the height Hpr of a solder bump (dash-dotted line) as well as the stand off Xpr as a function of the pad diameter D according to former investigations. It can easily be seen that solder bump height Hpr strongly depends on pad diameter D and is about 0.3 times the pad diameter D. Former investigations forecasted a similar (linear) effect also for the stand off Xpr. The stand off Xpr is about 0.15 times the pad diameter D (dashed line). But more recent investigations showed that a zero stand off or a near zero stand off Xin is surprisingly achievable when first contact pads do not exceed 20 μm (solid line). For small pad diameters below 20 μm, the solder picked up through the ISB process is arranged around the periphery of the combined contact pads, thereby not contributing to the increase of the stand-off.
These results advantageously can be used for manufacturing very small electronic devices. In particular, this is interesting for so-called Radio Frequency Identification Tags,
RFID tags for short, which are needed in large amounts nowadays. By virtue of the invention, these tags can be built with a very low assembly height using the comparatively easy and therefore cheap production processes UBM and ISB.
It should be noted that the concrete value of the "zero stand off does not only depend on the size of the contact pads but also on their surface. Hence, a fine structured surface leads to a smaller value than a rough surface. The process of soldering can furthermore be performed with a small or without any force effect, which also influences said value.
Since "stand off in the terminology of this invention refers to the distance between the contacts, there is some distance between first and second substrate in the case of UBMs, which normally jut out from the surfaces of said substrates. Hence, the distance between the substrates is influenced by the thickness of the UBM layers and cannot be smaller than the sum of the thicknesses of the UBM layers of the connecting members, which in practice is in the order of microns. Therefore, electronic devices made by means of inventive substrates are normally underfilled according to known technologies.
It is advantageous if the smallest planar extension of said first contact pads with respect to said first surface does not underrun 5 μm. It has been found that contact pads should have a certain size at least so that they are easy to manufacture. Said range runs from 5 μm to 20 μm which is advantageous in particular for the UBM and ISB processes. • Electroless NiAu for instance has already been performed on pads with dimensions down to 7 • μm, which is of course not to be interpreted as a "physical" lower limit. It might be possible to produce smaller NiAu contact pads in the near future. However, these small dimensions put new demands on the bath that is being used for this process. Hence a "practical" lower value for the pad diameter is considered to be 5 μm. It is further advantageous when first contact pads have a raised edge. When solder is put onto a contact pad, intermetallics are formed where the solder contacts the metal of the contact pad. These intermetallics hinder the zero stand off, since the tendency of "sucking together" the parts involved is not as strong as necessary. In the case of raised edges said intermetallics are mainly formed in the center, i.e., the groove of the contact pads. Therefore they do not essentially hamper the close approximation of two contact pads.
Contact pads and in particular contact pads with raised edges jutting out from the surfaces of the first and second substrate lead to an additional advantage, which emerges especially in the case of a zero stand off. In this case there is only contact of points instead of contact of a whole surface, which obviously assists in achieving the zero stand off of the contact pads.
Yet another preferred solution in accordance with the invention is a substrate, wherein a metallic bond pad is arranged between a first contact pad and said first surface, wherein the metallic bond pad is partly covered by an insulating layer in the border area, and wherein said first contact pad juts out from said insulating layer. This structure is the result of a UBM process for instance, which is relatively easy to handle. Hence, the technical and financial effort required to manufacture the aforesaid substrate is quite low. It should be mentioned here that the invention is not limited to UBM.
Advantageously, the substrate comprises solder bumps on first contact pads, because the first substrate is then prepared to be soldered to a second substrate also comprising second metallic contact pads. The solder bumps are preferably manufactured using an ISB process but are not limited thereto. An alternative to the aforesaid ISB is wave soldering, which can also be used for the concerns of the invention. Further applicable technologies are stencil printing as well as plating, which both are relatively expensive compared to ISB. It should also be noted here that soldering does not depend on the use of an underbump metallization. Soldering can rather be accomplished with any contact pad.
Furthermore, advantageously the solder bump consists of a low melting solder. Hence a substrate can consist of a temperature-sensitive material such as paper or plastic. The prior art hereto discloses solders, which melt below 100°C. With respect to this matter, US 6,740,544, "Solder compositions for attaching a die to a substrate", dated May 25, 2004 is referenced, in particular table 1, column 6. Furthermore the document discloses a possibility to raise the melting point of a solder through so-called ,,solder agents". Said document is herewith incorporated by reference. The aforesaid method is especially advantageous when a device is operated under a higher environmental temperature condition.
It is further advantageous if more adjacent first metallic contact pads form an electric contact. One single contact pad, which preferably has a size between 5 μm and 20 μm, is only able to drive a certain current. If the necessary current resulting from a certain design of an electronic circuit exceeds said limit, it is possible to form an electric contact comprising more adjacent first metallic contact pads. In this way an electric contact can drive any wanted current without increasing the stand-off. It should be mentioned at this point that " the contact pads do not necessarily have to be in the vicinity of each other. It is also imaginable that there are metallic contact pads of another electric contact inbetween them.
The object of the invention is furthermore achieved by an electronic device comprising a substrate with a first surface having first metallic contact pads, and a second substrate with a second surface having second metallic contact pads, wherein first contact
pads and second contact pads are soldered together, wherein first contact pads on the first substrate and corresponding second contact pads on the second substrate face each other, and wherein the greatest planar extension of said first and second contact pads with respect to said first and second surface does not exceed 20 μm. The object of the invention is also achieved by a method of manufacturing a substrate with a first surface comprising first metallic contact pads through an underbump metallization process, short UBM, wherein the greatest planar extension of said first contact pads with respect to said first surface does not exceed 20 μm.
It should be noted here that advantages as well as various embodiments, which were cited when discussing the inventive substrate, are valid also for the inventive device as well as for the inventive method. Hence a special citation of embodiments and their advantages for the inventive device and for the inventive method is omitted.
BRIEF DESCRIPTION OF THE DRAWINGS These and other aspects of the present invention will be apparent from, and elucidated with reference to, the embodiments described herein. Embodiments of the present invention will now be described by way of examples only and with reference to the accompanying drawings, in which:
Figure Ia is a cross sectional view of a prior art substrate; Figure Ib is a top view of the substrate of Figure Ia;
Figure 2 is a cross sectional view of a prior art electronic device; Figure 3a is a cross sectional view of an inventive substrate; Figure 3b is a top view of the substrate of Figure 3a; Figure 4 is a cross sectional view of an inventive electronic device; Figure 5 shows the relation between pad diameter and bump height as well as between pad diameter and stand off;
Figure 6 shows a contact pad in the form of a pentagon.
DESCRIPTION OF EMBODIMENTS Figure 3 a shows the cross section of an inventive substrate 10, Figure 3b shows the corresponding top view. Substrate 10 could be a part of a larger electronic circuit, thus Figure Ia and Ib only show a cutout of such an electronic circuit, which normally comprises a number of those parts.
Said substrate 10 comprises a first metallic bond pad 11 (e.g. made of Cu, Ni, Co,
Nb, etc.) on a first surface. Above substrate 10 a first insulating layer 12 is arranged, which also covers the border area of the first metallic bond pad 11. Insulating layer 12 forms four cylindrical grooves on the upper side of the first bond pad 11. On the first metallic bond pad 11 and in the grooves there are arranged four first contact pads 13a..13d, which jut out from said first insulating layer 12. Because of the cylindrical groove, first contact pads 13a..13d have raised edges. Finally, solder bumps 14a..14d are provided on first contact pads 13a..13d. The height Hin of the solder bumps 14a..14d depends on the diameter Din of the first contact pads 13a..13d and is about 0.3 times said diameter Din. The arrangement shown in Figures Ia and Ib normally is an intermediate product. For this example it is assumed that said arrangement is part of a die comprising an electronic circuit.
To complete an electronic device 30, this die is flip chip mounted on a support substrate. A part of this support substrate is shown in Figure 4. Figure 4 shows an arrangement where the part of Figure 3a and an identical mirror-inverted part are soldered together. Said mirrored part comprises a second substrate 20 with a second metallic bond pad 21 on a second surface. Below the second substrate 20 a second insulating layer 22 is arranged, which also covers the border area of the second metallic bond pads 21. Again, cylindrical grooves are formed in the lower side of the second bond pad 21. Under the second metallic bond pad 21 and in the grooves there are arranged second contact pads 23a..23d (23c and 23d not shown due to the cross sectional view), which jut out from said second insulating layer 22. Because of the cylindrical groove, second contact pads 23a..23d have raised edges. Separate solder bumps 24a..24d are omitted since there already is solder on the first contact pads 13a..13d. When both parts are soldered together, first and second contact pads 13a..13d and 23a..23d are sucked together through the surface tension of the solder bumps 14a..14d. Figure 4 shows that the connection of the two parts results in a stand off Xin, i.e., the distance between contact pads 13a..13d and 23a..23d. Contrary to the former opinion that the stand off Xin strongly linearly depends on the pad diameter Din, Figure 4 (as well as Figure 5) shows that the stand off Xin surprisingly is zero or almost zero although the diameter between contact pads 13a..13d and 23a..23d is greater than zero.
The height of a solder bump 14a..14d; 44 does not only depend on the pad diameter Din but also on the shape of a contact pad 13a..13d; 14a..14d; 43; 44. Thus,
Figure 6 shows an example of a first contact pad 73, which is polygon shaped, more precisely pentagon shaped. It should be noted here that the first contact pad 73 only serves as an example. Hence, a multitude of forms is imaginable for the first contact pad 73, for instance a triangle, a rectangle (especially a quadratic one), a hexagon as well as an octagon.
Furthermore, elliptic, oval and kidney-shaped forms are possible, for example. Figure 6 now shows that such a first contact pad 73 has a greatest planar extension Din and a smallest planar extension din, which preferably are in the range from 20 μm to 5 μm.
It should be noted that it is not mandatory that a plurality of first contact pads 13a..13d form a single electric contact. In fact the invention is also applicable to cases where one single first contact pad 13a..13d forms an electric contact. Furthermore, it is not mandatory that first contact pads 13a..13d are manufactured through a UBM process or are shaped like a UBM. A first contact pad 13a..13d could rather be a flat object on a first surface of first substrate 10 or even be embedded in it. It should further be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be capable of designing many alternative embodiments without departing from the scope of the invention as defined by the appended claims. In the claims, any reference signs placed in parentheses shall not be construed as limiting the claims. The word "comprising" and "comprise(s)", and the like, does not exclude the presence of elements or steps other than those listed in any claim or the specification as a whole. The singular reference of an element does not exclude the plural reference of such elements and vice- versa. In a device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere . fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
Claims
1) Substrate (10) with a first surface comprising first metallic contact pads (13a..13d) separated by insulating areas inbetween them, which first contact pads (13a..13d) and second contact pads (23a..23d) on a second surface of a second substrate (20) are to be soldered together, wherein said first contact pads (13a..13d) on said substrate (10) and corresponding second contact pads (23a..23d) on the second substrate (20) then face each other, and wherein the greatest planar extension (Din) of said first contact pads (13a..13d) with respect to said first surface does not exceed 20 μm.
2) Substrate (10) as claimed in claim 1, wherein the smallest planar extension (din) of said first contact pads (13a..13d) with respect to said first surface does not underrun 5 μm.
3) Substrate (10) as claimed in claim 1, wherein first contact pads (13a..13d) have a raised edge.
4) Substrate (10) as claimed in claim 1, wherein a metallic bond pad (11) is arranged between a first contact pad (13a..13d) and said first surface, wherein the metallic bond pad (11) is partly covered by an insulating layer (12) in the border area, and wherein said first contact pad (13a..13d) juts out from said insulating layer (12).
5) Substrate (10) as claimed in claim 1, comprising solder bumps (14a..14d) on first contact pads (13a..13d).
6) Substrate (10) as claimed in claim 1, wherein the solder bumps (14a..14d) consist of a low melting solder.
7) Substrate (10) as claimed in one of claims 1 to 6, wherein more adjacent first metallic contact pads (13a..13d) form an electric contact.
8) Electronic device (30) comprising a substrate (10) with a first surface having first metallic contact pads (13a..13d), and a second substrate (20) with a second surface having second metallic contact pads (23a..23d), wherein first contact pads (13a..13d) and second contact pads (23a..23d) are soldered together, wherein first contact pads (13a..13d) on first substrate (10) and corresponding second contact pads (23a..23d) on second substrate (20) face each other, and wherein the greatest planar extension (Din) of said first and second contact pads (13a..13d, 23a..23d) with respect to said first and second surface does not exceed 20 μm.
9) Method of manufacturing a substrate (10) with a first surface comprising first metallic contact pads (13a..13d) by means of an underbump metallization process, UBM for short, wherein the greatest planar extension (Din) of said first contact pads (13a..13d) with respect to said first surface does not exceed 20 μm.
10) Method as claimed in claim 9, wherein the smallest planar extension (din) of said first contact pads (13a..13d) with respect to said first surface does not underrun 5 μm.
11) Method as claimed in claim 9, wherein solder bumps (14a..14d) on said first contact pads (13a..13d) are manufactured using an immersion solder bumping process, ISB for short.
12) Method as claimed in claim 9, wherein low melting solder is used for manufacturing the solder bumps (14a..14d).
13) Method as claimed in one of claims 9 to 12, wherein more adjacent first metallic contact pads (13a..13d) form an electric contact.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP05794401A EP1805799A1 (en) | 2004-10-20 | 2005-10-18 | Substrate with electric contacts and method of manufacturing the same |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP04105175 | 2004-10-20 | ||
| PCT/IB2005/053408 WO2006043235A1 (en) | 2004-10-20 | 2005-10-18 | Substrate with electric contacts and method of manufacturing the same |
| EP05794401A EP1805799A1 (en) | 2004-10-20 | 2005-10-18 | Substrate with electric contacts and method of manufacturing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| EP1805799A1 true EP1805799A1 (en) | 2007-07-11 |
Family
ID=35520813
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP05794401A Withdrawn EP1805799A1 (en) | 2004-10-20 | 2005-10-18 | Substrate with electric contacts and method of manufacturing the same |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP1805799A1 (en) |
| JP (1) | JP2008517475A (en) |
| CN (1) | CN101044619A (en) |
| WO (1) | WO2006043235A1 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090310320A1 (en) * | 2008-06-16 | 2009-12-17 | Weston Roth | Low profile solder grid array technology for printed circuit board surface mount components |
| CN101754579B (en) * | 2009-11-16 | 2012-02-22 | 华为终端有限公司 | Castle-type module and terminal equipment |
| US8809123B2 (en) * | 2012-06-05 | 2014-08-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three dimensional integrated circuit structures and hybrid bonding methods for semiconductor wafers |
| CN103531562B (en) * | 2012-07-04 | 2016-07-06 | 颀邦科技股份有限公司 | Semiconductor package structure and its lead frame |
| CN104681530B (en) * | 2013-11-26 | 2017-09-26 | 日月光半导体制造股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN106252247B (en) * | 2016-09-05 | 2019-07-05 | 江苏纳沛斯半导体有限公司 | Semiconductor structure and forming method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB0001918D0 (en) * | 2000-01-27 | 2000-03-22 | Marconi Caswell Ltd | Flip-chip bonding arrangement |
| US6596618B1 (en) * | 2000-12-08 | 2003-07-22 | Altera Corporation | Increased solder-bump height for improved flip-chip bonding and reliability |
| US20020093106A1 (en) * | 2001-01-17 | 2002-07-18 | Ashok Krishnamoorthy | Bonding pad for flip-chip fabrication |
| US6862378B2 (en) * | 2002-10-24 | 2005-03-01 | Triquint Technology Holding Co. | Silicon-based high speed optical wiring board |
-
2005
- 2005-10-18 EP EP05794401A patent/EP1805799A1/en not_active Withdrawn
- 2005-10-18 CN CNA2005800361282A patent/CN101044619A/en active Pending
- 2005-10-18 JP JP2007537448A patent/JP2008517475A/en not_active Withdrawn
- 2005-10-18 WO PCT/IB2005/053408 patent/WO2006043235A1/en not_active Ceased
Non-Patent Citations (1)
| Title |
|---|
| See references of WO2006043235A1 * |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2006043235A1 (en) | 2006-04-27 |
| JP2008517475A (en) | 2008-05-22 |
| CN101044619A (en) | 2007-09-26 |
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