EP1777688B1

EP1777688B1 - Systems for controlling pixels

Info

Publication number: EP1777688B1
Application number: EP05109818.4A
Authority: EP
Inventors: Du-Zen Peng; Shih-Chang Chang
Original assignee: Innolux Corp
Current assignee: Innolux Corp
Priority date: 2005-10-21
Filing date: 2005-10-21
Publication date: 2014-08-27
Anticipated expiration: 2025-10-21
Also published as: EP1777688A1

Description

BACKGROUND

The present application relates in general to display devices and relates in particular to a system for controlling a light emitting pixel of a display device.
Electroluminescence (EL) display devices include organic light emitting diode (OLED) displays and polymeric light emitting diode (PLED) displays. In accordance with associated driving methods, an OLED can be an active matrix type or a passive matrix type. An active matrix OLED (AM-OLED) display typically is thin and exhibits lightweight characteristics, spontaneous luminescence with high luminance efficiency and low driving voltage. Additionally, an AM-OLED display provides the perceived advantages of increased viewing angle, high contrast, high-response speed, full color and flexibility.
An AM-OLED display is driven by electric current. Specifically, each of the matrix-array pixel areas of an AM-OLED display includes at least one thin film transistor (TFT), serving as a driving TFT, to modulate the driving current. Driving current is modulated based on the variation of capacitor storage potential to control the brightness and gray level of the pixel areas.
The gray level is selected by using a voltage divider comprising resistors. Fig. 1a is a schematic diagram of a conventional voltage divider. The voltage divider 10 comprises resistors serially connected between a high voltage source (Vcc) and a low voltage source (Gnd). Each point between two resistors has a corresponding voltage indicating a particular gray level.
A point 110 of voltage divider 10 can provide a maximum gray level indicating a maximum brightness of the AM-OLED. Since a voltage divider only provides one maximum gray level, if a user desires to adjust the maximum brightness of the AM-OLED higher, the AM-OLED requires several voltage dividers.
Fig. 1b is a schematic diagram of another conventional voltage divider. A voltage between two resistors can be adjusted according to the resistance of two resistors. In this case, a first maximum gray level provided by voltage divider 10 is 100nits, a second maximum gray level provided by voltage divider 12 is 150nits, and a third maximum gray level provided by voltage divider 14 is 200nits. Therefore, the brightness of the AM-OLED can be adjusted by providing different maximum gray levels; however, the cost and volume of the AM-OLED are increased.
EP 1 600 924 A1 , which is prior art according to Art. 54(3) of the European Patent Convention, discloses an organic light emitting display, wherein a first pixel and a second pixel share a data line, a select scan line, and a driving element, and wherein a field is divided into first and second subfields. An organic light emitting element of the first pixel is driven by a first emission control signal transmitted to a first emit scan line, and an organic light emitting element of the first pixel is driven by a second emission control signal transmitted to a second emit scan line. The first emission control signal has a low-level pulse in the first subfield, the second emission control signal has a low-level pulse in the second subfield, and a select signal transmitted to the select scan line has a low-level pulse in each of the first and second subfields. In addition, a scan driver for driving the select signal line, the first emit scan line, and the second emit scan line is provided. This document does not disclose in particular a combinatorial logic unit in the sense of claim 1.
WO 2005/036515 A1 discloses an active matrix electroluminescent display which has means for interrupting the drive of current through the display element. Row driver circuitry for the display has a shift register and logic arrangement for generating the drive voltage for the interrupting means, and which includes a pulse having a duration which can be varied up to substantially the full field period less the address period. The signal or signals propagated through the shift register arrangement control the pulse duration. Control for a row of the display is achieved by row addressing of the pixels with control of the overall light emission period of each row. The control enables a scrolling addressing scheme to be implemented. The logic arrangement receives, however, only two shifted signals to control a light emitting pixel.

SUMMARY

It is an object of the present invention to provide an improved system for controlling a first light emitting pixel of a display, which can be operated in a more flexible manner.
This problem is solved by a system for controlling a first light emitting pixel of a display according to claim 1. Further advantageous embodiments are the subject-matter of the dependent claims.
Systems for controlling pixels are provided. An exemplary embodiment of such a system comprises a scan driver comprising: a first shift-register unit operative to output a first shift signal according to a first start signal; a second shift-register unit operative to output a second shift signal according to the first shift signal for lighting the first pixel; a third shift-register unit operative to output a third shift signal according to the second shift signal; and a first processor operative to control the first pixel to receive the first data signal according to the first, the second, and the third shift signals. A duty cycle of the first start signal determines a light-emitting duration of the first pixel.
Another embodiment of a system for controlling a pixel comprises: a data signal line operative to provide data to the pixel; and a scan driver operative to control illumination of the pixel during sequential time periods such that, if data provided by the data signal line is different between a first time period and a second time period, brightness of the pixel differs during a third time period and a sequential fourth time period. The pixel is illuminated during the third time period and the fourth time period.
Another embodiment of a system for controlling a pixel comprises a display device. The display device comprises a display panel comprising a first pixel; an EL driver operative to output a start signal; a data driver operative to output a first data signal to the first pixel; and a scan driver operative to output a first scan signal and a second scan signal to the first pixel. The first pixel is operative to receive the first data signal according to the first scan signal and the first pixel is illuminated according to the second scan signal. The scan driver comprises: a first shift-register unit operative to output a first shift signal according to the first start signal; a second shift-register unit operative to output a second shift signal according to the first shift signal for lighting the first pixel; a third shift-register unit operative to output a third shift signal according to the second shift signal; and a first processor operative to control the first pixel to receive the first data signal according to the first, the second, and the third shift signals. A duty cycle of the first start signal establishes a light-emitting duration of the first pixel.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention can be more fully understood by reading the subsequent detailed description and examples with reference made to the accompanying drawings, wherein:

Fig. 1a: is a schematic diagram of a conventional voltage divider;
Fig. 1b: is a schematic diagram of another conventional voltage divider;
Fig. 2a: is a schematic diagram of an embodiment of a system for controlling pixels;
Fig. 2b: is a schematic diagram of an embodiment of a display device used in the system of Fig. 2a;
Fig. 3: is a schematic diagram of an embodiment of a scan driver;
Fig. 4: is a timing diagram of the scan driver of Fig. 3;
Fig. 5: is a schematic diagram of another embodiment of a scan driver;
Fig. 6: is a schematic diagram of another embodiment of a scan driver.

DETAILED DESCRIPTION

Systems for controlling pixels are provided. As will be described with reference to several exemplary embodiments, brightness of the pixels of a display can be adjusted, such as by increasing the light-emitting duration of the pixels. In this regard, Fig. 2a is a schematic diagram of an embodiment of a system for controlling pixels that is implemented as an electronic device. Note that such an electronic device can be provided in various configurations, such as a PDA, a display monitor, a notebook computer, a tablet computer, or a cellular phone. Electronic device 2 comprises a display device 20 and a digital-to-analog converter (DAC) 25. DAC 25 supplies power to display device 20.
Fig. 2b is a schematic diagram of an embodiment of display device 20. As shown in Fig. 2b, display device 20 comprises a display panel 21 comprising pixels P₁₁~P_mn, a data driver 22, a scan driver 23, and an electroluminescence (EL) driver 24, which can be implemented by an integrated circuit (IC).
Data driver 22 provides data signals D₁~D_m to pixels P₁₁~P_mn. Scan driver 23 receives a start signal (STV) output from EL driver 24 and controls pixels P₁₁~P_mn by scan signals S₁~S_n and XS₁~XS_n. Pixels P₁₁~P_mn receive data signals D₁~D_m according to scan signals S₁~S_n and pixels P₁₁~P_mn are illuminated according to scan signals XS₁~XS_n.
Fig. 3 is a schematic diagram of an embodiment of a scan driver. For clarity, only two pixels of the display are shown. The structures of the pixels shown in Fig. 3 are given as an example; however, in other embodiments, other configurations can be used.
Scan driver 23 comprises a shift register circuit 33 and processors 34~37. Shift register circuit 33 comprises shift register units VSR₁~VSR₄. Each shift register unit outputs a shift signal according to a duty cycle of start signal STV.
Processor 34 comprises logic units 341 and 342. A first input terminal of logic unit 341 is floating and a second input terminal of logic unit 341 receives shift signal SS₁. A first input terminal of logic unit 342 is coupled to an output terminal of logic unit 341 and a second input terminal of logic unit 342 receives shift signal SS₂. Since the first input terminal of logic unit 341 is floating, an output terminal of logic unit 342 does not control a pixel. Processor 35 comprises logic units 351 and 352. Logic unit 351 receives shift signals SS₁ and SS₂. Logic unit 352 receives an output signal of logic unit 351 and shift signal SS₃ to generate scan signal SD₁. Pixel 31 receives data signal DS according to scan signal SD₁. Shift signal SS₂ also corresponds to scan signals XSD₁. Pixel 31 is illuminated according to scan signal XSD₁.
Processor 36 comprises logic units 361 and 362. Logic unit 361 receives shift signals SS₂ and SS₃. Logic unit 362 receives an output signal of logic unit 361 and shift signal SS₄ to generate scan signal SD₂. Pixel 32 receives data signal DS according to scan signal SD₂. Shift signal SS₃ corresponds to scan signals XSD₂. Pixel 32 is illuminated according to scan signal XSD₂.
Processor 37 comprises logic units 371 and 372. Logic unit 371 receives shift signals SS₃ and SS₄. A first input terminal of logic unit 372 receives an output signal of logic unit 371 and a second input terminal of logic unit 372 is floating. Since the second input terminal of logic unit 372 is floating, an output terminal of logic unit 372 does not control a pixel.
In this embodiment, logic units 341, 351, 361, and 371 are XOR gates and logic units 342, 352, 362, and 372 are AND gates.
Fig. 4 is a timing diagram of the embodiment of the scan driver depicted in Fig. 3. In Fig. 3, shift register units VSR₁~VSR₄, respectively, output shift signals SS₁~SS₄ responsive to shift register unit VSR₁ receiving start signal STV.
Pixel 31 receives data signal DS according to shift signals SS₁~SS₃ received by processor 35. As shown in Fig. 4, a logic level of shift signal SS₁ is low and those of shift signals SS₂ and SS₃ are high such that a logic level of scan signal SD₁ is high in period P₁.
Therefore, transistor 311 can be turned on. A data signal is transmitted to capacitor 312 through transistor 311 to charge capacitor 312. Transistor 313 is turned on for outputting driving current I₁ as a voltage of capacitor 312 reaches a first preset value. Since a logic level of scan signal XSD₁ is high, transistor 314 is turned on in period P₁. Light-emitting element 315 is illuminated as driving current I₁ is transmitted to light-emitting element 315 by transistor 314.
In period P₂, the logic level of scan signal XSD₁ is low such that light-emitting element 315 is extinguished. Since the logic level of scan signal SD₂ is high, capacitor 322 is charged such that driving current I₂ is provided by transistor 323. Light-emitting element 325 receives driving current I₂ and is illuminated as the logic level of scan signal SD₂ is high.
In period P₃, the logic level of scan signal XSD₂ is low such that light-emitting element 325 is extinguished. In period P₄, the logic level of scan signal XSD₁ is high such that transistor 314 is turned on. Since the voltage of capacitor 312 maintains the first preset value, transistor 313 generates driving current I₁, which is provided to light-emitting element 315 for illuminating that element.
In period P₅, since the logic level of scan signal SD₁ is high, capacitor 312 is again charged according to data signal DS such that the voltage of capacitor 312 reaches a second preset value. Transistor 313 generates new driving current I₁ according to the new voltage of capacitor 312. Since the logic level of scan signal XSD₁ is also high, light-emitting element 315 is illuminated.
In period P₄, the voltage of capacitor 312 depends on the data signal DS received by transistor 311 in period P₁. In period P₅, the voltage of capacitor 312 depends on the data signal DS received by transistor 311 in period P₅. Although light-emitting element 315 is illuminated in periods P₄ and P₅, if data signal DS in period P₁ is different than the data signal DS in period P₅, the brightness of light-emitting element 315 in period P₄ differs from the brightness of light-emitting element 315 in period P₅.
In period P₆, the logic level of scan signal XSD₂ is high such that transistor 324 is turned on. Since the voltage of capacitor 322 can turn on transistor 323, light-emitting element 325 receives driving current I₂ and is illuminated.
In period P₇, since the logic level of scan signal SD₂ is high, capacitor 322 is again charged according to data signal DS. Transistor 323 outputs new driving current I₂ according to the voltage of capacitor 322. Since the logic level of scan signal XSD₂ is also high, light-emitting element 325 is illuminated.
The voltage of capacitor 322 in period P₆ depends on the data signal DS received by transistor 321 in period P₂. The voltage of capacitor 322 in period P₇ depends on the data signal DS received by transistor 321 in period P₇. Although light-emitting element 325 is illuminated in periods P₆ and P₇, if data signal DS in period P₂ is different than the data signal DS in period P₇, the brightness of light-emitting element 325 in period P₆ is different from the brightness of light-emitting element 325 in period P₇.
Taking pixel 31 as an example, since start signal STV only has a cycle in period P₈, the light-emitting state of light-emitting element 315 is luminous-dark-luminous in periods P₁~P₄. If transistor 314 is replaced by a PMOS transistor or the start signal cycle is inverted, the light-emitting state of light-emitting element 315 is changed to dark-luminous-dark in periods P₁~P₄. The light-emitting state of light-emitting element 315 is luminous-dark-luminous-dark-luminous as start signal STV has two cycles in period P₈.
Duration of each light-emitting state depends on the duty cycle of start signal STV. Assume a display panel requires 16.63ms to display an image and the light-emitting states of all light-emitting elements in the display panel are luminous-dark-luminous. Then, if the duration of the luminous state is 16.63ms, the brightness of the display panel is 100%, if the duration of the luminous state is 13.304ms, the brightness of the display panel is 80%. If the duration of the luminous state is 8.315ms, the brightness of the display panel is 50%.
For example, assume light-emitting element 315 is illuminated during periods P₁, P₄, and P₅ according to scan signal XSD₁. If the light-emitting duration (the duration of periods P₁, P₄, and P₅) of light-emitting element 315 is 13.304ms, the brightness of the display panel is 80%. Therefore, the duty cycle of start signal STV controls the light-emitting duration of light-emitting element and thus controls the brightness of the display panel. Because of this, a user can adjust the brightness of the display panel according to actual requirements for reducing power consumption.
Fig. 5 is a schematic diagram of another embodiment of a scan driver. Each of the logic units 342, 352, 362, and 372 further receives a vertical output enable signal ENBV. Each of the buffers 371~374 has an amplification function. Buffer 371 amplifies scan signal SD₁ for turning on transistor 311. Buffer 372 amplifies scan signal XSD₁ for turning on transistor 314. Buffer 373 amplifies scan signal SD₂ for turning on transistor 321. Buffer 374 amplifies scan signal XSD₂ for turning on transistor 324.
Fig. 6 is a schematic diagram of another embodiment of a scan driver. Each pixel comprises three sub-pixels for displaying red, green and blue, respectively. For clarity, Fig. 6 only shows a pixel comprising sub-pixels 61~63 respectively displaying red, green and blue.
Each shift register unit VSR_1B~VSR_3B provides a shift signal as shift register unit VSR_1B receives start signal STV_B. Processor 64 receives shift signals provided by shift register units VSR_1B~VSR_3B for generating scan signal SD₁. Sub-pixels 61~63 respectively receive data signals DS_R, DS_G and DS_B according to scan signal SD₁. A shift signal provided by shift register ister unit VSR_2B is scan signal XSD_1B. Sub-pixel 63 is illuminated according to scan signal XSD_1B.
When shift register unit VSR_1R receives start signal STV_R, a shift signal provided by shift register unit VSR_2R is used as scan signal XSD_1R. Sub-pixel 61 is illuminated according to scan signal XSD_1R.
When shift register unit VSR_1G receives start signal STY_G, a shift signal provided by shift register unit VSR_2G is used as scan signal XSD_1G. Sub-pixels 62 is illuminated according to scan signal XSD_1G.
The light-emitting duration of sub-pixels 61 ∼ 63 are respectively controlled by duty cycles of start signals STV_R, STV_G and STV_G.
In summary, the light-emitting duration of the pixels of a display can be controlled by the duty cycle of start signal STV. The brightness of the display panel is brighter as the light-emitting duration of the pixels is longer, and vice versa. Therefore, a user can adjust the brightness of the display panel according to actual requirements.

Claims

A system (2) for controlling a first light emitting pixel (31, 63) which is adapted to receive a first data signal (DS, DS_B) when a first scan signal (SD1) is active and to emit light when a first light emission control signal (XSD1, XSD_1B) is active, said system comprising:
a display device (20) comprising:
a scan driver (23) comprising:
a first shift-register stage (VSR1, VSR_1B) adapted to input a first start signal (STV, STV_B) and to output a first shifted signal (SS1);

a second shift-register stage (VSR2, VSR_2B) adapted to input the first shifted signal (SS1) and to output a second shifted signal (SS2);

a third shift-register stage (VSR3, VSR_3B) adapted to input the second shifted signal (SS2) and to output a third shifted signal (SS3); and

a first combinatorial logic unit (35, 64) adapted for generating the first scan signal (SD1) in accordance with the first (SS1), the second (SS2), and the third (SS3) shifted signals;

wherein said first shift-register stage (VSR1, VSR_1B), said second shift-register stage (VSR2, VSR_2B) and said third shift-register stage (VSR3, VSR_3B) form a shift register circuit (33);

a display panel (21) disposing the first light emitting pixel (31, 63);

an electroluminescence driver (24) adapted to output the first start signal (STV, STV_B); and

a data driver (22) adapted to output the first data signal (DS, DS_B) to the first light emitting pixel (31, 63);

wherein the second shifted signal (SS2) serves as the first light emission control signal (XSD1, XSD_1B); and

wherein the first combinatorial logic unit (35, 64) comprises:
a first logic unit (351) comprising a first input terminal adapted to receive the first shifted signal (SS1), a second input terminal adapted to receive the second shifted signal (SS2) and a first output terminal,

wherein the first logic unit (351) is adapted such that the first output terminal outputs a first logic level when a logic level of the first shifted signal (SS1) equals that of the second shifted signal (SS2) and such that the first output terminal outputs a second logic level when the logic level of the first shifted signal (SS1) differs from that of the second shifted signal (SS2); and

a second logic unit (352) comprising a third input terminal connected to the first output terminal, a fourth input terminal adapted to receive the third shifted signal (SS3), and a second output terminal connected to the first light emitting pixel (31, 63) to provide the first scan signal (SD1),

wherein the second logic unit (352) is adapted such that the second output terminal outputs the first logic level when one or both of the logic levels of the first output terminal and the third shifted signal (SS3) equal the first logic level and such that the second output terminal outputs the second logic level when the logic level of the first output terminal and that of the third shifted signal (SS3) equal the second logic level.
The system as claimed in claim 1, wherein the first light emitting pixel (31) comprises a first transistor (311), a second transistor (313), a third transistor (314), a light-emitting element (315) and a capacitor (312), wherein the first transistor (311) is adapted to transmit the first data signal (DS) to the gate of the second transistor (313) in accordance with the first scan signal (SD1), wherein the second transistor (313), the third transistor (314) and the light-emitting element (315) are serially connected between a first voltage level (Vcc) and a second level (Vss), the third transistor (314) is controlled by the second shifted signal (SS2) and the capacitor (312) is connected between the gate and the source of the second transistor (313).
The system as claimed in claim 1 or 2, wherein the second logic unit (352) further comprises a fifth input terminal adapted to receive a control signal (ENBV), wherein the second logic unit (352) is further adapted such that the second output terminal outputs the first logic level when at least one of the logic levels of the control signal (ENBV), the first output terminal or third shifted signal (SS3) equals the first logic level, and such that the second output terminal outputs the second logic level when the logic levels of the control signal (ENBV), of the first output terminal and of the third shifted signal (SS3) equal the second logic level.
The system as claimed in claims 1 or 3, wherein the display panel (21) further comprises a second light emitting pixel (61) and a third light emitting pixel (62) disposed on said display panel (21) and wherein the scan driver (23) further comprises:
a fourth shift register stage (VSR_1R) adapted to input a second start signal (STV_R) and to output a fourth shifted signal;

a fifth shift register stage (VSR_2R) adapted to input the fourth shifted signal and to output a fifth shifted signal as second light emission control signal (XSD_1R);

a sixth shift register stage (VSR_1G) adapted to input a third start signal (STV_G) and to output a sixth shifted signal;

a seventh shift register unit (VSR_2G) adapted to input the sixth shifted signal and to output a seventh shifted signal as third light emission control signal (XSD_1G); wherein the scan driver is adapted to provide the first scan signal (SD1) to the first light emitting pixel (63), the second light emitting pixel (69), and the third light emitting pixel (62) to control the first light emitting pixel (63), the second light emitting pixel (S1), and the third light emitting pixel (62), respectively, to receive the first data signal (DS_B), a second data signal (DS_R), and a third data signal (DS_G), respectively, and is adapted to control the light-emitting duration of the first light emitting pixel (63), the second light emitting pixel (61), and the third light emitting pixel (62), respectively, using the first light emission control signal (XSD_1B), second light emission control signal (XSD_1R) and third light emission control signal (XSD_1G), respectively, in accordance with a duty cycle of the first start signal (STV_B), the second start signal (STV_R), and the third start signal (STV_G), respectively.
The system as claimed in claim 4, wherein the first light emitting pixel (63) is adapted to display a blue color, the second light emitting pixel (61) is adapted to display a red color, and the third light emitting pixel (62) is adapted to display a green color.
The system as claimed in any of the preceding claims, wherein the first logic unit (351) is an XOR gate and the second logic unit (352) is an AND gate.
The system as claimed in claim 4 or 5, wherein the data driver (22) is further adapted to output the second data signal (DS_R) to the second light emitting pixel (61) and the third data signal (DS_G) to the third light emitting pixel (62).
The system as claimed in any of the preceding claims, further comprising:
a digital-to-analog converter (DAC) adapted to supply power to the display device (20).
The system as claimed in any of the preceding claims, further comprising:
means for supplying power to the display device (20).