EP1776636A2 - Procédé d'enregistrement d'erreurs et registre correspondant - Google Patents

Procédé d'enregistrement d'erreurs et registre correspondant

Info

Publication number
EP1776636A2
EP1776636A2 EP05769873A EP05769873A EP1776636A2 EP 1776636 A2 EP1776636 A2 EP 1776636A2 EP 05769873 A EP05769873 A EP 05769873A EP 05769873 A EP05769873 A EP 05769873A EP 1776636 A2 EP1776636 A2 EP 1776636A2
Authority
EP
European Patent Office
Prior art keywords
error
register
dual
computer system
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05769873A
Other languages
German (de)
English (en)
Inventor
Thomas Kottke
Andreas Steininger
Christian El Salloum
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP1776636A2 publication Critical patent/EP1776636A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G06F11/1679—Temporal synchronisation or re-synchronisation of redundant processing components at clock signal level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0736—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function
    • G06F11/0739—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function in a data processing system embedded in automotive or aircraft systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0766—Error or fault reporting or storing
    • G06F11/0772—Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0796—Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/845—Systems in which the redundancy can be transformed in increased performance

Definitions

  • the invention is based on a method for delaying the access to data and / or commands of a dual-computer system and a corresponding delay unit according to the features of the independent claims known from the prior art.
  • dual-computer systems or dual-processor systems are today's computer systems for safety-critical applications, in particular in vehicles such as for anti-lock braking systems, electronic stability program (ESP), X-by-wire systems such as drive-by-wire or steer-by-wire as well as break-by-wire, etc. or other networked systems.
  • ESP electronic stability program
  • X-by-wire systems such as drive-by-wire or steer-by-wire as well as break-by-wire, etc. or other networked systems.
  • powerful error mechanisms and error handling mechanisms are required, in particular to counteract transient errors that arise, for example, in miniaturization of the semiconductor structures of the computer systems.
  • Two-processor systems can only detect errors that have occurred, but they do not offer the possibility of performing effective error handling. Since the frequency of transient errors will increase sharply compared to permanent errors due to decreasing semiconductor structures, effective error handling will be necessary to increase the availability of future systems.
  • the invention is based on a method for error registration and a register which is assigned to a dual-computer system, wherein information in the form of bits are stored in the register, the dual-computer system having a
  • Error detection mechanism includes, wherein advantageously represent the bits in the register as error bits at least one error signal of the error detection mechanism and corresponding two-computer system.
  • the register is expediently designed so that the error detection mechanism can set a corresponding error bit and this error bit can be erased by the dual-computer system, the register being contained in a computer of the dual-computer system or being inserted into the memory area of a computer of the dual-computer system.
  • an error bit is set in the register only on the basis of a first error. Furthermore, it is expedient that a plurality of error signals are combined into a uniform error signal and that an interrupt is triggered by the uniform error signal.
  • a register is provided for each computer in a dual-computer system, wherein the two computers of the dual-computer system operate in one embodiment with a clock offset and also the setting of the error bit in the registers with this clock offset.
  • a register for each computer and triggered by each uniform error signal an interrupt, wherein the interrupts are triggered with the clock offset, wherein in the method for error registration in a dual-computer system, upon detection of an error at least one error bit is stored in the register and at least a register is evaluated and an error treatment is performed depending on the position of the error bit in the register or the at least one register is evaluated and error handling is performed depending on the error bits in the register and the register is reset or deleted after error handling.
  • FIG. 1 shows a dual-processor system or two-processor system with a delay unit according to the invention.
  • FIG. 2 shows a first embodiment of a delay unit according to the invention.
  • FIG. 3 shows a second embodiment of a delay unit according to the invention.
  • FIG. 4 shows a multiplex component, in particular a secure multiplexer, of a delay unit according to the invention.
  • Figure 5 shows a register for error registration and its function
  • FIG. 1 shows a dual-computer system with a first computer 100, in particular a master computer and a second computer 101, in particular a slave computer. The entire system is doing with a predetermined clock or in predetermined clock cycles
  • clock cycle CLK operated.
  • the clock is supplied to this.
  • a special feature for error detection is included in this dual-computer system, in which the first computer 100 and the second computer 101 work with a time offset, in particular a predefinable time offset or a specifiable clock offset.
  • any time can be predetermined for a time offset and also any desired clock with respect to an offset of the clock cycles.
  • This can be an integer offset of the clock cycle, but just as shown in this example, for example, an offset of 1.5 clock cycles, in which case the first computer 100 just 1.5 clock cycles before the second Calculator 101 works respectively is operated.
  • this system is designed to operate at a given skew or clock skew, particularly 1.5 clock cycles, i. while a computer, z. B. computer 100 directly the components, in particular the external components 103 and 104 responds, the second computer 101 operates with a delay of exactly 1.5 clock cycles to do so.
  • computer 101 is fed with the inverted clock, that is to say the inverted clock at the clock input CLK2.
  • Computers 100 and 101 are in communication.
  • 117 is a command bus in which 117A is a command address bus and 117B is the partial command (data) bus.
  • Address bus 117A is connected to computer 100 via a command address connection IA1 (instruction address 1) and to computer 101 via an instruction address connection IA2 (instruction address 2).
  • the instructions themselves are transmitted via the sub-command bus 117B, which is connected to computer 100 via a command terminal II (Instruction 1) and to computer 101 via a command terminal 12 (Instruction 2).
  • this command bus 117 consisting of 117A and 117B is a component 103 z.
  • B. an instruction memory, in particular a secure instruction memory or the like interposed.
  • a data bus which includes a data address bus or a data address line 116A and a data bus or a data line 116B.
  • 116A that is to say the data address line
  • DA1 data address 1
  • DA2 data address 2
  • DO1 data Out 1
  • DO2 data connection DO2
  • the data bus 116C which is connected to computer 100 or computer 101 via a data connection Dil (Data In 1) and a data connection DI2 (Data In 2), also belongs to data bus 116.
  • a component 104 is interposed, for example a data memory, in particular a secure data memory o. ⁇ . This component 104 is also supplied with the clock CLK in this example.
  • the components 103 and 104 are representative of any components which are connected via a data bus and / or command bus to the computers of the dual-computer system and corresponding to the accesses via data and / or commands of the dual-processor system with respect to write operations and / or read operations erroneous data and / or commands receive or give away.
  • error prevention are indeed
  • Error detection generators 105, 106 and 107 are provided which generate an error detection such as a parity bit or other error code such as an error correction code, so ECC, o. ⁇ .. are also provided the corresponding Starbuckskennungsprüf healthyen or check Means 108 and 109 for checking the respective misrecognition, for example, the
  • Parity bit or other error code such as ECC.
  • Clock cycle offset between the computers 100 and 101 either caused by a non-synchronous Zweiratiorsystem or in a synchronous Zweireaorsystem by errors in the synchronization or as in this particular example by a desired error detection time or clock cycle offset, in particular here of 1.5 clock cycles, so may in this time or Clock offset a computer here in particular computer 100 erroneous data and / or commands in components, in particular external components such. B. here in particular the memory 103 or 104, but also with respect to other participants or actuators or sensors write or read. Thus, it may also erroneously perform a write access instead of a designated read access by this clock offset.
  • these scenarios lead to errors in the entire system, in particular without clear display possibility which data and / or commands have just been changed incorrectly, which also causes the recovery problem.
  • a delay unit 102 is now connected as shown in the lines of the data bus and / or in the command bus. For reasons of clarity, only the activation in the data bus is shown. Of course, this is just as possible and imaginable with regard to the command bus.
  • This delay unit 102 or the delay unit delays the accesses, here in particular the memory accesses, in such a way that a possible time or clock offset is compensated, in particular in the event of an error detection, for example via the comparators 110 and 111, e.g. at least until the error signal is generated in the dual-computer system, that is, the error detection is performed in the dual-computer system.
  • delay of the read and write operations delay of only the write operations or, although not preferred, a delay of the read operations. It can be converted by a change signal, in particular the error signal, a delayed write operation in a read operation to prevent erroneous writing.
  • the purpose of the delay unit that is, of the delay unit 102, is to delay accesses in the context of said time offset or clock cycle offset in order to compensate for this, in particular to write operations of the computer 100 to a component, in particular external component, up to
  • FIG. 2 now shows a delay unit with two switching modules 201 and 200, in particular multiplex modules, a delay element 204 and a test device or test device 203, in particular a TSC checker.
  • the delay unit consists of two branches, a reading branch, the lower one
  • the delay unit consists, in particular if it is intended to delay only write operations, from two paths between which a switching device, in particular a multiplexer 200, can switch over.
  • the data and / or commands go here the data from DOl (Data Out 1), the corresponding addresses, here DAl (Data Address 1) and here in particular additional memory control signals MC (Memory Control) without delay, in the other branch delayed by the delay element 204.
  • the switching between the two paths is effected by a switching signal, in particular the read / write signal
  • the write branch that is the branch with the delay element 204, for example, there is a delay of two clock cycles with a predetermined delay of 1.5
  • Switching signal (in particular by using the read / write signal R / W or the derived Invert R / W).
  • R / W write / read signal
  • this is the inverted write / read signal by the inverter 205.
  • the second switching module 200 in particular the second multiplexer, which brings together the data and / or commands (here by way of example the data), is likewise replaced by this
  • Signal in particular the read / write signal R / W and inverted to the inverted.
  • the signal from the delayed path, that is to say behind the delay element 204, is advantageous here, as described below.
  • a gap of the duration of the write operation occurs at the output of the switching block 200.
  • the switch block 200 ie the multiplexer, would activate the read branch, ie the three lower inputs of multiplexer 200, the non-delayed data or addresses and control information of this branch still belonging to the write operation.
  • the previous operation get on the bus switching device 201 is provided, which in this case uncritical constants z. 2, to the lower input of the multiplexer 200 while this wait lasts, until multiplexer 200 may reach the top three Input paths, ie the delayed, switch over and the current write operation.
  • the signals are Data Address DAl (Data Address), Data Output DOl (Data Out) and
  • Control signal (MC) each secured in this example by a simple parity bit.
  • This parity is protected by the check units 109 and 108 for the command bus, wherein, as not shown in Figure 1, the memory control signal MC is secured by an additional memory checker 202.
  • the parity bit of this signal MC is equally delayed by the delay element 204 as are the other signals. Since the signals of each signal type DAl, DOl and MC are carried independently in the delay unit, this simple parity bit allows sufficient protection against single errors. With multi-error detection or protection as well as correction of multiple errors, as already mentioned, more powerful error detections can be used.
  • An additional function can be realized via the path DAE / DOE, 206, 207 and 208. This is a protection of write operations in case of failure with standard components such as a fail safe memory or the same
  • the error signal DAE / DOE of the dual core is available as a dual rail code. This is converted into a single-rail signal before a time offset between them. This takes place in a comparison block 206 which can be embodied, in particular, as an XOR block. At the same time, the XOR gate 206 makes a single signal from the multiple signal.
  • a time delay of 0.5 clock cycles is now added in a delay element 207 in order to achieve a time alignment of the resulting error signal with the corresponding data word in the delay unit. This is because the delay unit in our example delays by 2 clock cycles according to delay 204.
  • block 208 z. B. uses an AND gate, the Read / write signal R / W are masked to block a write access as shown in connection with the shadowing of block 208.
  • This DAE / DOE input so the error signal from the computers can also like the parity bit of the memory controller MC from 202 and the respective switching or
  • an either non-delayed or delayed data signal or data output signal DOId data out delayed depending on a read operation or write operation and in this particular example if a memory device is used as component, especially external component, a memory control signal or memory control signal MCd (Memory Control delayed ) which is either not delayed or delayed.
  • FIG. 3 once again shows a delay unit in a second embodiment, where the delay unit can also be designed as shown only from one switching module or multiplexer 200 and two branches.
  • the second multiplexer 200 is used from Figure 2 so that the inputs DAl, DOl and MC are fed directly to this.
  • the same inputs are delayed as before via a delay element 204 and also supplied to the multiplexer 200.
  • the data in this case data address DA1, data DO1 and memory controller MC
  • write operations in the non-delayed path are converted into read operations.
  • This change or switching of the write operations in read operations can also be performed inverted by the read / write signals R / W or the R / W derived therefrom.
  • the second embodiment is constructed similarly to the first embodiment except for the fact that the first multiplexer 201 has been omitted, whereby the terms and the functions as far as they are present are identical.
  • the exception is the test unit, as these are supplied by the missing multiplexer 201 fewer signals and therefore can be constructed slightly different and therefore designated here by 303.
  • the reusable error signal EO which can be used in the context of error handling, likewise outputs.
  • safe multiplexers according to FIG. 4 can be used as switching modules or multiplexers.
  • the data is by a
  • Error detection code here, for example, a parity bit hedged and the control signals so switching or change signals, in particular the
  • Read / write signal R / W and the inverse read / write signal RIW derived from it are also protected, here by way of example in dual rail logic. That the R / W and the inverse signal are first supplied to the secure multiplexer and from there to
  • Test unit to the TSC checker 203 or 303.
  • an error affecting a track of the write / read signal is detected by the test unit TSC 203 or 303 while a single error in the multiplex circuit will affect a simple output bit and thus by the parity Check can be determined. That the data and / or commands as previously executed are switched as in a standard multiplexer, wherein in addition the parity bit or another error identifier are switched.
  • the control signals ie changeover or change signals R / W and R / W Invert, are first fed to all switches for the individual bits, here represented in the blocks 401 to 406, in particular as AND gates, to which the respective inputs 110, Il 1, 120, 121 are fed to InO, InI.
  • Output signals from 401-406 are then combined in blocks 407-409, respectively, as shown in FIG.
  • the blocks 407-409 are designed in particular as OR gates. This then results in outputs of the multiplex block Ol, 02 to On.
  • the structure shown in Figure 4 is only a section of the Overall structure of a multiplex block according to Figures 2 and 3 with the bit widths exemplified therein of 17 bit or 5 bits per signal path.
  • both multiplex modules 201 and 200 corresponding to FIGS. 2 and 3 are advantageously designed in the form of FIG. 4 in order to make it possible to identify a data path which has been incorrectly switched over as already described, and
  • This security package is concluded by securing the interface to a component, in particular an external component corresponding to 103 and 104 from FIG. 1, by error detection units for generation of the error identification 105-107 and error checking units for checking the error detection such as 108 and 104 as already illustrated in FIG 109 are provided, in particular, as party bit checkers and party bit generators.
  • error detection units for generation of the error identification 105-107
  • error checking units for checking the error detection such as 108 and 104 as already illustrated in FIG 109 are provided, in particular, as party bit checkers and party bit generators.
  • the resulting error signals can then just as DAE / DOE signals according to Figure 2 and Figure 3 just as Data Address Error or Data Out Error in the delay module as described are used.
  • FIG. 5 shows the mode of operation of the register, in particular the error register.
  • interrupt controller must be designed to be fault-tolerant, or correspondingly many interrupt lines would have to be available. This is also because of the
  • Error detection mechanisms are not intelligent interrupt sources that could possibly provide an identifier.
  • an error register is proposed here, which is installed in each of the two processors of the dual-computer system.
  • This register need not necessarily be addressable like a register in the processor, but can also be stored in a memory area of the processor
  • Each bit of the error register represents the error signal of one
  • bits (A) to (H) represent correspondingly:
  • Command memory error e.g. a parity error in the instruction address
  • Data memory errors can also be represented by 2 bits. One e.g. for errors in the address and the other for errors in the data
  • error may be caused by e.g. be recognized in a parity test as in
  • Bit 0 slave This offset is necessary because in this example implementation, the two processors operate at a clock skew of 1.5 clocks.
  • the implementation can also be used for two-processor systems with different clock offsets from 0 to x (x from the natural numbers). In this case, the signal for the second processor must be delayed accordingly.
  • the error signals are available as dual-rail signals. But this is not absolutely necessary.
  • all individual error signals become a total signal summarized.
  • an interrupt can be triggered on the two-processor system. The interrupt is first triggered on the master (interrupt master) and with the corresponding clock offset on the slave (interrupt slave). The delay at the slave in the amount of the clock offset is necessary to ensure the synchronicity of the two-processor system even in the event of an error and during the error handling routine.
  • the error register of the master can now be read out by the master and the error register of the slave by the slave. By evaluating the set bit, an error handling routine can now be started. After completion of the
  • the error register does not have to be fault-tolerant since it is implemented individually for each processor. If an error occurs in a register, the two processors deal with an error handling (carry out different recovery measures) and thus errors are detected in this register. If the error register is only present in a simple manner, then it likewise does not have to be implemented in a fault-tolerant manner since, in the event of an error, a bit must be set in this register and an interrupt must also be triggered. If the interrupt is triggered and the bit is not set or two bits are set, an error has occurred in the error register.
  • the error register or error register pair can not only be used in two-processor systems. It can also be used in x-fold processor systems, where x can be from 1 to infinity.
  • Error detection mechanism represents (2) an error register in which the error detection mechanisms of the processor system can set the corresponding error bit and it can be cleared by the processor again and is executed as a processor register or faded into the memory area of the processor
  • an error register at Only the first occurring error may set a bit
  • each error detection mechanism is represented by a bit / symbol / symbol and sets this upon detection of an error.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Debugging And Monitoring (AREA)

Abstract

L'invention concerne un procédé d'enregistrement d'erreurs et un registre associé à un système informatique double, ce registre contenant des informations sous forme de bits et le système informatique double comprenant un mécanisme de détection d'erreur. Selon l'invention, les bits du registre représentent en tant que bits d'erreur au moins un signal d'erreur du mécanisme de détection d'erreur.
EP05769873A 2004-08-06 2005-08-01 Procédé d'enregistrement d'erreurs et registre correspondant Withdrawn EP1776636A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004038596A DE102004038596A1 (de) 2004-08-06 2004-08-06 Verfahren zur Fehlerregistrierung und entsprechendes Register
PCT/EP2005/053730 WO2006015955A2 (fr) 2004-08-06 2005-08-01 Procédé d'enregistrement d'erreurs et registre correspondant

Publications (1)

Publication Number Publication Date
EP1776636A2 true EP1776636A2 (fr) 2007-04-25

Family

ID=35583530

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Application Number Title Priority Date Filing Date
EP05769873A Withdrawn EP1776636A2 (fr) 2004-08-06 2005-08-01 Procédé d'enregistrement d'erreurs et registre correspondant

Country Status (5)

Country Link
US (1) US20090024908A1 (fr)
EP (1) EP1776636A2 (fr)
CN (1) CN1993678A (fr)
DE (1) DE102004038596A1 (fr)
WO (1) WO2006015955A2 (fr)

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Publication number Priority date Publication date Assignee Title
US9342832B2 (en) 2010-08-12 2016-05-17 Visa International Service Association Securing external systems with account token substitution
US20140195862A1 (en) * 2013-01-04 2014-07-10 Microsoft Corporation Software systems by minimizing error recovery logic
CN107133123A (zh) * 2017-04-28 2017-09-05 郑州云海信息技术有限公司 一种关于pmc‑raid卡奇偶校验错误的注错测试的方法
US10518801B2 (en) * 2017-10-19 2019-12-31 GM Global Technology Operations LLC Estimating stability margins in a steer-by-wire system
CN112015159B (zh) * 2019-05-31 2021-11-30 中车株洲电力机车研究所有限公司 一种基于双核mcu的故障记录存储方法及计算机系统

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Publication number Priority date Publication date Assignee Title
EP0415547A3 (en) * 1989-08-01 1993-03-24 Digital Equipment Corporation Method of handling nonexistent memory errors
US5295258A (en) * 1989-12-22 1994-03-15 Tandem Computers Incorporated Fault-tolerant computer system with online recovery and reintegration of redundant components
GB2317032A (en) * 1996-09-07 1998-03-11 Motorola Gmbh Microprocessor fail-safe system

Non-Patent Citations (1)

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Title
See references of WO2006015955A3 *

Also Published As

Publication number Publication date
CN1993678A (zh) 2007-07-04
WO2006015955A3 (fr) 2006-06-08
WO2006015955A2 (fr) 2006-02-16
US20090024908A1 (en) 2009-01-22
DE102004038596A1 (de) 2006-02-23

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