EP1761053A2 - Datenprüfungsvorrichtung und -verfahren - Google Patents

Datenprüfungsvorrichtung und -verfahren Download PDF

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Publication number
EP1761053A2
EP1761053A2 EP06291373A EP06291373A EP1761053A2 EP 1761053 A2 EP1761053 A2 EP 1761053A2 EP 06291373 A EP06291373 A EP 06291373A EP 06291373 A EP06291373 A EP 06291373A EP 1761053 A2 EP1761053 A2 EP 1761053A2
Authority
EP
European Patent Office
Prior art keywords
hdmi
data
stream
encrypted
data verification
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06291373A
Other languages
English (en)
French (fr)
Other versions
EP1761053A3 (de
Inventor
Jae Young 1009 Seonreung-Yeok Heo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LG Electronics Inc
Original Assignee
LG Electronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LG Electronics Inc filed Critical LG Electronics Inc
Publication of EP1761053A2 publication Critical patent/EP1761053A2/de
Publication of EP1761053A3 publication Critical patent/EP1761053A3/de
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
    • H04N21/4405—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving video stream decryption
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41—Structure of client; Structure of client peripherals
    • H04N21/426—Internal components of the client ; Characteristics thereof
    • H04N21/42646—Internal components of the client ; Characteristics thereof for reading from or writing on a non-volatile solid state storage medium, e.g. DVD, CD-ROM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/60—Network structure or processes for video distribution between server and client or between remote clients; Control signalling between clients, server and network components; Transmission of management data between server and client, e.g. sending from server to client commands for recording incoming content stream; Communication details between server and client 
    • H04N21/63—Control signaling related to video distribution between client, server and network components; Network processes for video distribution between server and clients or between remote clients, e.g. transmitting basic layer and enhancement layers over different transmission paths, setting up a peer-to-peer communication via Internet between remote STB's; Communication protocols; Addressing
    • H04N21/633—Control signals issued by server directed to the network components or client
    • H04N21/6332—Control signals issued by server directed to the network components or client directed to client
    • H04N21/6334—Control signals issued by server directed to the network components or client directed to client for authorisation, e.g. by transmitting a key
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/765—Interface circuits between an apparatus for recording and another apparatus
    • H04N5/775—Interface circuits between an apparatus for recording and another apparatus between a recording apparatus and a television receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/91—Television signal processing therefor
    • H04N5/913—Television signal processing therefor for scrambling ; for copy protection
    • H04N2005/91357—Television signal processing therefor for scrambling ; for copy protection by modifying the video signal
    • H04N2005/91364—Television signal processing therefor for scrambling ; for copy protection by modifying the video signal the video signal being scrambled
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/84—Television signal recording using optical recording
    • H04N5/85—Television signal recording using optical recording on discs or drums
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/79—Processing of colour television signals in connection with recording
    • H04N9/80—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback
    • H04N9/804—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback involving pulse code modulation of the colour picture signal components
    • H04N9/8042—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback involving pulse code modulation of the colour picture signal components involving data reduction

Definitions

  • the present invention relates to a data verification apparatus and a data verification method, and more particularly, to a data verification apparatus and method which can verify digital multimedia data to be transmitted and received.
  • LCD liquid crystal display
  • a Digital Visual Interface which is one of the digital interfaces, is a standard that, when being connected with a digital device, can transmit and receive digital signals to/from the digital device without converting them into analog signals.
  • pixel data and control data are transmitted as channel data in a Transition-Minimized Differential Signaling (TMDS) manner.
  • TMDS Transition-Minimized Differential Signaling
  • pixel data and control data are acquired and displayed from TMDS data.
  • the DVI inputs a digital image directly without converting it into an analog image.
  • the use of the DVI enables the provision of a distortionless high-quality picture without analog signal losses, such as blurring due to sharpness loss, afterimage, poor gradation, and low legibility.
  • the generalization of the DVI will reduce a serious deviation in output signal quality among respective graphic board makers, which is a problem in transmitting and receiving an analog signal.
  • a High Definition Multimedia Interface is a next-generation digital interface standard based on the aforementioned DVI technology, which can not only transmit audio data in addition to video data based on the DVI, but also perform content protection.
  • This HDMI is adopted in High Definition (HD) multimedia products being currently introduced to the market.
  • FIG. 1A shows a connection between a digital versatile disc (DVD) player and a television (TV) when the HDMI is not used
  • FIG. 1B shows a connection between the DVD player and the TV when the HDMI is used.
  • DVD digital versatile disc
  • the use of the HDMI enables the DVD player and the TV to be connected with each other via only one cable, not a plurality of cables.
  • Signal transmission in the HDMI can be made in the TMDS manner as in the DVI.
  • the HDMI performs encryption for content protection, and generally uses High-bandwidth Digital Content Protection (HDCP) as an encryption scheme.
  • HDMI High-bandwidth Digital Content Protection
  • FIG. 2A and FIG. 2B are block diagrams showing examples of application of the HDCP encryption scheme to an HDMI stream.
  • FIG. 2A shows an implementation of the HDCP encryption scheme in an HDMI transmitter chip
  • FIG. 2B shows an implementation of the HDCP encryption scheme in a Moving Picture Experts Group (MPEG) decoder chip.
  • MPEG Moving Picture Experts Group
  • a stream outputted from the HDMI transmitter chip is an HDCP-encrypted TMDS stream.
  • HDMI-format data In addition, in transmission and reception of HDMI-format data, provided that a verification cannot be made as to whether an HDCP-encrypted signal has been accurately processed, the HDMI-format data will be degraded in reliability even though being transmitted and received.
  • the present invention is directed to a data verification apparatus and a data verification method that substantially obviate one or more problems due to limitations and disadvantages of the related art.
  • An object of the present invention is to provide a data verification apparatus and method which can verify HDMI-format data to be transmitted and received HDMI-format data in transmission and reception of the HDMI-format data.
  • Another object of the present invention is to provide a data verification apparatus and method which can perform transmission/reception algorithms for HDMI-format data and provide an environment for development of a transmitter/receiver module for the HDMI-format data.
  • a receive data verification apparatus comprises: a decrypter for decrypting an encrypted High Definition Multimedia Interface (HDMI) stream and outputting the decrypted, resulting raw data in the form of an HDMI stream; and a receive data verifier for receiving the HDMI stream from the decrypter and performing HDMI reception algorithms to verify the received HDMI stream.
  • HDMI High Definition Multimedia Interface
  • the decrypter comprises: an HDMI receiver module for receiving and decrypting the encrypted HDMI stream; and an HDMI transmitter module for receiving and outputting the decrypted HDMI stream from the HDMI receiver module.
  • the decrypted raw data may be multimedia data including video data for three video channels and audio data.
  • the encrypted HDMI stream may be a stream encrypted in a High-bandwidth Digital Content Protection (HDCP) encryption scheme.
  • HDMI High-bandwidth Digital Content Protection
  • the receive data verifier comprises: a Digital Visual Interface (DVI) receiver module for receiving the HDMI stream from the decrypter; a reception algorithm processor for receiving data from the DVI receiver module and performing the reception algorithms with respect to the received data to verify and output it; and a DVI transmitter module for encoding and outputting the output data from the reception algorithm processor in a Transition-Minimized Differential Signaling (TMDS) manner.
  • DVI Digital Visual Interface
  • TMDS Transition-Minimized Differential Signaling
  • the reception algorithm processor may be implemented with a Field-Programmable Gate Array (FPGA) chip.
  • FPGA Field-Programmable Gate Array
  • the data received by the reception algorithm processor may be multimedia data including video data and audio data.
  • a transmit data verification apparatus comprises: a decrypter for decrypting and outputting an encrypted HDMI stream; and a transmit data verifier for performing HDMI transmission algorithms with respect to raw data outputted from the decrypter.
  • the raw data outputted from the decrypter may be multimedia data including video data for three video channels and audio data.
  • the encrypted HDMI stream may be a stream encrypted in an HDCP encryption scheme.
  • the transmit data verifier comprises: a transmission algorithm processor for converting the raw data outputted from the decrypter into an HDMI stream and performing the HDMI transmission algorithms with respect to the converted HDMI stream to verify and output it; and a DVI transmitter module for encoding and outputting the HDMI stream from the transmission algorithm processor in a TMDS manner.
  • the transmission algorithm processor may be implemented with an FPGA chip.
  • a receive data verification method comprises: receiving and decrypting an encrypted HDMI stream; outputting the decrypted, resulting raw data in the form of an HDMI stream; receiving the outputted HDMI stream and performing reception algorithms with respect to the received HDMI stream to verify HDMI reception performance; and encoding and outputting the verified HDMI stream in a TMDS manner.
  • a transmit data verification method comprises: receiving and decrypting an encrypted HDMI stream; converting the decrypted, resulting raw data into an HDMI stream and performing transmission algorithms to verify the converted HDMI stream; and encoding and outputting the verified HDMI stream in a TMDS manner.
  • the encrypted HDMI stream may be a stream encrypted in an HDCP encryption scheme.
  • the decrypted HDMI stream may be multimedia data including video data for three video channels and audio data.
  • FIG. 1A is a schematic diagram showing a connection between a DVD player and a TV when an HDMI is not used;
  • FIG. 1B is a schematic diagram showing a connection between the DVD player and the TV when the HDMI is used;
  • FIG. 2A is a block diagram showing an example of implementation of an HDCP encryption scheme in an HDMI transmitter chip
  • FIG. 2B is a block diagram showing an example of implementation of the HDCP encryption scheme in an MPEG decoder chip
  • FIG. 3 is a block diagram of a data verification apparatus which performs reception algorithms for HDMI data, according to an embodiment of the present invention
  • FIG. 4 is a block diagram of a data verification apparatus which performs transmission algorithms for HDMI data, according to an embodiment of the present invention
  • FIG. 5 is a flow chart illustrating a receive data verification method according to an embodiment of the present invention.
  • FIG. 6 is a flow chart illustrating a transmit data verification method according to an embodiment of the present invention.
  • HDMI data or HDMI stream For the convenience of description, data or stream capable of being transferred through an HDMI will hereinafter be referred to as HDMI data or HDMI stream.
  • FIG. 3 is a block diagram of a data verification apparatus which performs reception algorithms for HDMI data, according to an embodiment of the present invention.
  • FIG. 3 comprises a digital versatile disc (DVD) player 300, decrypter 310, receive data verifier 320, and display unit 330.
  • DVD digital versatile disc
  • the decrypter 310 receives an HDCP-encrypted HDMI stream from the DVD player 300, HDCP-decrypts the received HDMI stream, and outputs the HDCP-decrypted HDMI stream.
  • the HDMI stream outputted from the DVD player 300 is an HDCP-encrypted stream, which cannot be used for verification of HDMI receive data without a verified HDCP decryption module.
  • the decrypter 310 HDCP-decrypts and outputs the received HDMI stream.
  • the decrypter 310 includes an HDMI receiver module 311, and an HDMI transmitter module 313.
  • the HDMI receiver module 311 receives and decrypts the HDCP-encrypted HDMI stream from the DVD player 300.
  • the decrypted raw digital signal is multimedia data including 24-bit video data for three channels, namely, 8-bit video data for each channel, and audio data.
  • the HDMI transmitter module 313 outputs the decrypted multimedia data in the form of an HDMI stream.
  • HDMI receiver module 311 and HDMI transmitter module 313 can process data of HDMI version 1.1 or above.
  • HDMI version 1.0 data cannot be HDCP-decrypted
  • data of HDMI version 1.1 or above must be used for the HDCP decryption.
  • the receive data verifier 320 performs various reception algorithms capable of verifying signal quality, display conditions, etc. in screen display using the HDMI stream received from the decrypter 310, and then outputs the resulting HDMI stream to the display unit 330.
  • the receive data verifier 320 includes a Digital Visual Interface (DVI) receiver module 321, reception algorithm processor 323, and DVI transmitter module 325.
  • DVI Digital Visual Interface
  • the DVI receiver module 321 receives the decrypted HDMI stream from the HDMI transmitter module 313 and outputs an audio data-embedded 24-bit video data stream.
  • the reception algorithm processor 323 receives the 24-bit video data stream and performs various HDMI reception algorithms with respect to the received data stream.
  • the use of the reception algorithm processor 323 enables reception and display environments of an HDMI stream to be tested and HDMI-associated modules to be developed.
  • the reception algorithm processor 323 is implemented with a Field-Programmable Gate Array (FPGA) chip.
  • FPGA Field-Programmable Gate Array
  • the FPGA chip refers to a prototype integrated circuit (IC) that is made for final verification of operation and performance of pre-designed hardware just before producing the hardware in the form of a semiconductor device.
  • IC integrated circuit
  • the FPGA chip comes within the category of general-purpose ICs in view of the semiconductor manufacturer because it is mass-produced and used for general purposes, and within the category of Application Specific Integrated Circuits (ASICs) in view of the user because it can be programmed and used according to the user's request.
  • ASICs Application Specific Integrated Circuits
  • the receive data verifier 320 may be an HDMI module which is incorporated in an HDMI receiver installable in a digital TV, monitor, or the like.
  • the HDMI receiver developer may implement and execute various HDMI reception algorithms in the reception algorithm processor 323.
  • Multimedia data outputted from the reception algorithm processor 323 includes 24-bit video data of three channels and audio data.
  • the DVI transmitter module 325 encodes the output data from the reception algorithm processor 323 in a TMDS manner and outputs the encoded data to the display unit 330.
  • the results of the algorithm processing can be confirmed through the display unit 330.
  • the display unit 330 may be a display unit of a digital television (DTV) or a monitor.
  • DTV digital television
  • FIG. 4 is a block diagram of a data verification apparatus which performs transmission algorithms for HDMI data, according to an embodiment of the present invention.
  • FIG. 4 comprises a digital versatile disc (DVD) player 400, decrypter 410, transmit data verifier 420, and display unit 430.
  • DVD digital versatile disc
  • the decrypter 410 receives an HDCP-encrypted HDMI stream from the DVD player 400, HDCP-decrypts the received HDMI stream, and outputs the HDCP-decrypted HDMI stream.
  • the decrypter 410 includes an HDMI receiver module for receiving and decrypting the HDCP-encrypted HDMI stream.
  • the transmit data verifier 420 includes a transmission algorithm processor 421, and a DVI transmitter module 423.
  • the transmission algorithm processor 421 extracts video data, audio data and control data from a decrypted raw digital signal and converts the extracted data into HDMI-format data. To this end, the transmission algorithm processor 421 performs HDMI transmission algorithms with respect to the decrypted raw digital signal, and verifies or tests and outputs HDMI-format data to be transmitted.
  • the transmission algorithm processor 421 is implemented with an FPGA chip.
  • the use of the transmission algorithm processor 421 enables transmission environments of an HDMI stream, to be transmitted, to be tested and HDMI-associated modules to be developed.
  • the DVI transmitter module 423 encodes the HDMI stream verified by the transmission algorithm processor 421 in the TMDS manner and outputs the resulting data to the display unit 430. As a result, the results of the HDMI transmission algorithm processing can be confirmed or verified through the display unit 430.
  • FIG. 5 is a flow chart illustrating a receive data verification method according to an embodiment of the present invention.
  • an encrypted HDMI stream is received and decrypted (S510).
  • the decrypted raw data is outputted in the form of an HDMI stream (S520).
  • the decrypted raw data is multimedia data including video data for three video channels and audio data.
  • the outputted HDMI stream is received and reception algorithms are performed therefor to verify HDMI reception performance (S530).
  • the verified HDMI stream is encoded and outputted in the TMDS manner (S540).
  • the verification results of the reception algorithms can be confirmed from the outputted results.
  • HDCP encryption and decryption, HDMI stream, and HDMI reception algorithms are the same as those described in the embodiment of FIG. 3.
  • FIG. 6 is a flow chart illustrating a transmit data verification method according to an embodiment of the present invention.
  • an encrypted HDMI stream is received and decrypted (S610).
  • the decrypted raw data is converted into an HDMI stream and transmission algorithms are performed to verify the converted HDMI stream (S620).
  • the verified HDMI stream is encoded and outputted in the TMDS manner (S630).
  • the verification results of the transmission algorithms can be confirmed from the outputted results.
  • HDCP encryption and decryption Details of the HDCP encryption and decryption, HDMI stream, and HDMI transmission algorithms are the same as those described in the embodiment of FIG. 4.
  • an HDCP-decrypted stream can be obtained by using an input/output (I/O) board equipped with a Field-Programmable Gate Array (FPGA) and a pre-developed HDMI chip.
  • an HDMI module can be easily developed by performing various HDMI reception or transmission algorithms with respect to the obtained stream.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Computer Security & Cryptography (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
EP06291373A 2005-08-30 2006-08-29 Datenprüfungsvorrichtung und -verfahren Withdrawn EP1761053A3 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020050080093A KR100662459B1 (ko) 2005-08-30 2005-08-30 Ｈｄｍｉ 수신기 및 전송기 개발 장치 및 그 방법

Publications (2)

Publication Number Publication Date
EP1761053A2 true EP1761053A2 (de) 2007-03-07
EP1761053A3 EP1761053A3 (de) 2007-11-21

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EP06291373A Withdrawn EP1761053A3 (de) 2005-08-30 2006-08-29 Datenprüfungsvorrichtung und -verfahren

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US (1) US20070049117A1 (de)
EP (1) EP1761053A3 (de)
KR (1) KR100662459B1 (de)

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WO2009108819A1 (en) * 2008-02-28 2009-09-03 Silicon Image, Inc Method, apparatus and system for deciphering media content stream
WO2013095447A1 (en) * 2011-12-21 2013-06-27 Intel Coproration Perceptual lossless compression of image data for transmission on uncompressed video interconnects

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US8971525B2 (en) * 2007-02-26 2015-03-03 Ati Technologies Ulc Method, module and system for providing cipher data
US9398344B2 (en) * 2012-06-08 2016-07-19 Lg Electronics Inc. Image display apparatus, mobile terminal and method for operating the same
WO2015194101A1 (ja) * 2014-06-16 2015-12-23 パナソニックＩｐマネジメント株式会社 再生方法および再生装置

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KR100662464B1 (ko) * 2005-09-28 2007-01-02 엘지전자 주식회사 멀티미디어 단말기

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US20050063541A1 (en) * 2002-11-05 2005-03-24 Candelore Brant L. Digital rights management of a digital device
US20050144468A1 (en) * 2003-01-13 2005-06-30 Northcutt J. D. Method and apparatus for content protection in a personal digital network environment
EP1519581A1 (de) * 2003-09-26 2005-03-30 Genesis Microchip, Inc. Paketbasierter Schutz von digitalen Inhalten mit hoher Bandbreite und hohe Auflösung
WO2005057535A2 (en) * 2003-12-05 2005-06-23 Motion Picture Association Of America Secure video system for display adaptor

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WO2009108819A1 (en) * 2008-02-28 2009-09-03 Silicon Image, Inc Method, apparatus and system for deciphering media content stream
JP2011518453A (ja) * 2008-02-28 2011-06-23 シリコン イメージ，インコーポレイテッド メディアコンテンツストリームを暗号解読するための方法、装置およびシステム
US8644504B2 (en) 2008-02-28 2014-02-04 Silicon Image, Inc. Method, apparatus, and system for deciphering media content stream
KR101499925B1 (ko) * 2008-02-28 2015-03-06 실리콘 이미지, 인크. 미디어 콘텐츠 스트림의 복호화 방법과 장치와 시스템
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WO2013095447A1 (en) * 2011-12-21 2013-06-27 Intel Coproration Perceptual lossless compression of image data for transmission on uncompressed video interconnects

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EP1761053A3 (de) 2007-11-21
US20070049117A1 (en) 2007-03-01
KR100662459B1 (ko) 2007-01-02

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