EP1730785A2 - Bipolar-transistor and method for the production of a bipolar-transistor - Google Patents
Bipolar-transistor and method for the production of a bipolar-transistorInfo
- Publication number
- EP1730785A2 EP1730785A2 EP05728216A EP05728216A EP1730785A2 EP 1730785 A2 EP1730785 A2 EP 1730785A2 EP 05728216 A EP05728216 A EP 05728216A EP 05728216 A EP05728216 A EP 05728216A EP 1730785 A2 EP1730785 A2 EP 1730785A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- doped layer
- buried
- collector
- space charge
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
- H01L29/7322—Vertical transistors having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor
Definitions
- the invention relates to an integrable NPN bipolar transistor and PNP bipolar transistor and a method for producing the same.
- Bipolar transistors are generally known as semiconductor components. A brief overview of the diverse manufacturing processes for bipolar transistors is given in the magazine article "Advances in Bipolar VLSI" by George R. Wilson in Proceedings of the IEEE, Vol. 78, No. 11, 1990, pp. 1707 to 1719.
- a subcoUector zone also referred to as a buried layer, is diffused into a p-doped semiconductor substrate, by means of which the collector level resistance of the transistor can be effectively reduced.
- the semiconductor substrate is then coated with an epitaxial n-type layer. Thereafter, electrically isolated areas are partitioned off in the epitaxial layer. These so-called epi islands are isolated via reverse-biased pn junctions, which are created by deeply diffused p-zones. Further diffusion steps follow, with which the base and emitter regions of the NPN bipolar transistor are defined. The contacting for the transistor connections is then carried out.
- DE 198 44 531 AI describes a simplified process for the production of semiconductor components, in particular bipolar transistors, in which an epitaxial and isolation process as in the standard bipolar process is no longer required.
- the simplified procedure is characterized in that a mask is defined on the semiconductor substrate which defines a window that is delimited by a circumferential edge, and an n-doped or p-doped trough is produced in the semiconductor substrate by means of high-voltage implantation.
- the high-voltage implantation is carried out with an energy that is sufficiently high that a p-doped or n-doped inner zone remains on the surface of the semiconductor substrate, while the edge zone of the n-doped or p-doped well extends to the surface of the substrate is sufficient.
- NPN and PNP transistors can be manufactured.
- DE 198 44 531 AI proposes an implantation of phosphorus ions with an implantation energy of 6 MeV.
- the stationary, negatively charged A-acceptors and the stationary, positively charged donors remain in this, so that a space charge arises that builds up an electric field. Therefore the depletion zone is also called space charge zone.
- the local field strength E (x) is obtained by integrating the space charge from an edge xi of the space charge zone to the depth x divided by the dielectric constant.
- the space charge zone is depleted of majority charge carriers, the space charge results from the product of the elementary charge q and the difference between the (volume) concentrations of the donors ND and the acceptors NA.
- the negatively charged acceptors dominate on the p-doped side and on the n - endowed the positively charged donors. Because of the neutrality condition, the charges on both sides of the pn transition must be of the same size.
- V: 2 E (x ') dx' (2)
- the integration limits xi and x 2 correspond to the edges of the space charge zone.
- the invention has for its object to bipolar transistors with high collector-emitter reverse voltage with an open base U CEO and high collector Create basic reverse voltage UC B O ZU and specify a process for their production.
- the basic principle of the transistors according to the invention or of the method according to the invention lies in the relatively low doping concentration of the buried layer.
- the dose of the implantation is in a range which is far below the implantation dose in the known methods.
- the principle of the voltage-proof NPN bipolar transistor can also be applied to PNP transistors in the same technology.
- a mask 2 is applied to a weakly p-doped semiconductor substrate 1 (wafer), which has a window 4a which is delimited by a peripheral edge 4b.
- a wafer of weakly doped monocrystalline silicon with a resistance of approximately 6 ⁇ cm is preferably used for the basic material, which corresponds to a basic doping of approximately 2.3 x 10 cm " .
- the mask material can be made of photoresist, metal, glass or other materials
- the structure is preferably produced by photolithographic processes created. A new mask is applied between the individual implantation steps. This is also known to the person skilled in the art.
- a doping preferably an implantation of phosphorus ions takes place with an implantation dose which, depending on the substrate doping, is between 5 ⁇ 10 11 atoms / cm “2 and 5 ⁇ 10 12 atoms / cm “ 2 .
- the dose is 1.7 x 10 12 atoms / cm "2 and the implantation energy 6 MeV.
- This creates a buried n-doped layer 3 in the p-substrate 1, which forms the collector K of the transistor buried layer is also referred to as a trough (Fig. la).
- the doping concentration drops not only into the depth of the substrate, but also towards the wafer surface, from the average range of the ions. In contrast to diffused tubs, this is referred to as an n-tub with a "retrograde" profile. If the ion implantation is sufficiently deep or the base or substrate doping is sufficiently high, the substrate doping is retained on the wafer surface -Transistors in the p-substrate are not absolutely necessary.
- an annular n-doped layer 5 is introduced into the p-substrate 1 by implantation or diffusion, which extends to the buried n-doped layer 3.
- the lateral isolation can also be carried out, for example, by etching a trench. This procedure is known to the person skilled in the art (FIG. 1b).
- the insulation layer (insulator) is then built up (FIG. 1f) and the contacting (metal) of the transistor connections at the n + and p + transition zones is carried out using the known methods (see above: GR Wilson).
- the n-doped well 3.5 forms the collector K
- the p-doped inner layer 7 together with the p + transition zone 10 and the p " -doped layer 6 forms the base B
- the n + -doped layer 9 the emitter E of the NPN transistor.
- FIG. 2 shows the doping concentration N and the field strength E as a function of the depth along the line A-A of FIG. 1g assuming that the doping concentration of the n-doped well 3 corresponds to a relatively high concentration according to the prior art.
- FIG. 2 shows the formation of the first space charge zone RLZ 1 between the p-doped layer 7, which forms the base B, and the n-doped well 3 forming the collector K.
- a second space charge zone RLZ 2 is formed between the well 3 and the p " substrate 1.
- a field-free zone is retained in between.
- the field strength E for different potentials on the collector is shown in FIG. 2.
- collector-emitter breakdown voltage UCEO which is related to the collector-base breakdown voltage U CBO (cf. equation (3)), is increased considerably when the area dose of the collector is reduced.
- an n-doped well 3, 5 is produced in the p-substrate by means of ion implantation, which is such that the first and second space charge zones RLZ 1 and 2, which expand when the transistor is operating, decrease with potential on the collector penetrate the entire depth of the buried n-doped layer 3 before the critical field strength for a breakthrough between collector and emitter is reached.
- the collector implantation dose of 1.7 x 10 atoms / cm " which depends in particular on the substrate doping. 3 shows that as the potential at the collector increases and the field strength increases, the space charge zones converge and finally meet. It is crucial that the space charge zones meet before the critical field strength for the collector-emitter breakdown is reached.
- the collector which is spatially below the base, is then completely depleted, ie the maximum available space charge of the collector is thus exhausted. This means that the space charge zones cannot expand any further. As a result, the field strength in the collector-base barrier layer cannot increase further. The charge carrier multiplication remains below the critical threshold. Thus, not only the Uc E o breakthrough but also the (vertical) U CBO breakthrough is suppressed. This required total depletion sets a lower limit on the collector dose.
- the voltage at the coUector connection may be increased further as long as there is no avalanche breakdown between the coUector connection and the substrate. However, this requires adequate precautions against lateral openings to the base and the substrate.
- the collector which is completely depleted in the blocked transistor, is very high-impedance, but as soon as the transistor switches on, the collector potential approaches the emitter potential and the collector regains its conductivity.
- the collector In order to achieve complete depletion, the collector must have a potential raised in the middle with respect to the substrate and the base. This forms a sufficient barrier for the holes in the base to prevent the holes from draining into the substrate. Only if the collector doping is so weak that the space charge zone between Kolle-ctor and substrate passes through the collector region, a so-called r punch-through breakdown takes place. The holes come out of the Base into the substrate. This breakthrough possibility sets a lower limit for the collector dose.
- the collector dose should be as close to the upper limit as possible.
- Both limits of the collector dose depend mainly on the substrate doping and lie between 5 x 10 ⁇ atoms / cm “2 and 5 x 10 12 atoms / cm “ 2 .
- the upper limit of substrate doping for voltage-proof transistors is given by the avalanche breakdown between the collector and the substrate. The corresponding breakdown voltage drops with decreasing wafer resistance.
- a still sensible upper limit for substrate doping is a wafer resistance of approx. 0.6 ⁇ cm.
- the permissible collector dose Further influencing factors on the permissible collector dose are the implantation depth, the desired punch-through strength between the base and substrate, the base depth and the thickness of the collector doping. They also determine the tolerance range of the permissible dose range, which is greater, the greater the depth of the collector, the thinner the collector trough and the lower the maximum voltage difference between base and substrate. With small tolerance ranges for the collector doping, it may be necessary to adapt the dose to the fluctuations of the substrate doping.
- a dose of 2 x 10 13 atoms / cm "2 is, for example U CEO 26V, at 2 xlO 12 atoms / cm" 2 30V and 1.7 x 10 12 atoms / cm "2 more than 120V.
- the use of high-voltage implantation has proven to be particularly advantageous in order to be able to set the implantation dose precisely to a value which should only be just below the critical limit.
- 4a to 4g illustrate the process steps for producing a PNP bipolar transistor in a p-doped substrate.
- a high-volume implantation again creates a buried n-doped layer 11, also referred to as a well, in the weakly p " -doped substrate 1 (FIGS. 4a and 4b).
- the high-voltage implantation is so to be dimensioned in such a way that either the substrate conduction type is retained on the wafer surface or is restored by an additional doping .
- the trough is isolated and connected to the side by another doping 13.
- the p " -doped layer 12 remains.
- a central n-doped layer 14 is introduced into the p " -doped layer 12 in a further implantation step (FIG. 4c).
- a circumferential near-surface n + transition zone is then placed in the Edge zone 13 of the trough 11 and a near-surface lateral n + transition zone 16 are introduced into the central n-layer 14 by ion implantation (FIG. 4d).
- a peripheral p + transition zone 18 near the surface is then introduced into the p " layer 12 and a lateral near the p + layer 17 into the central n layer 14 by ion implantation (FIG. 4e).
- the inner p " layer 12 now forms the collector K, which Central n-layer 14, the base B and the lateral p + -layer 17 the emitter E of the PNP transistor, the highly doped transition zones being provided to establish an ohmic connection to the transistor connections.
- the transistor connections can be contacted again using the known processes.
- the (p) collector below the n base must also be completely depleted in the PNP transistor in the p-substrate before the UC E O is reached.
- the n-well must not impoverish at this point, since it in turn should impoverish the (p) collector. This results in an interdependency between an upper limit for the (p) collector doping and a lower limit for the implantation dose of the n-well.
- FIG. 5 shows the doping concentration N and the field strength E as a function of the depth along the line BB of FIG. 4g.
- a first space charge zone RLZ 1 is formed between the n-doped layer 14 and the p " -doped layer 12 and a second space charge zone RLZ 2 between the p " -doped layer 12 and the buried n-doped layer 11.
- the two space charge zones expand on both sides during operation of the transistor with decreasing potential at the collector K.
- the ion implantation produces the buried n-doped layer with a doping profile which is such that the space charge zones RLZ 1 and RLZ 2 which expand at the collector during operation of the transistor with decreasing potential expand the entire depth of the p " -doped Penetrate layer 12 before the critical field strength for a breakthrough between collector K and emitter E is reached.
- a third space charge zone forms between the buried n-doped layer 11 and the p " substrate 1.
- the blocking voltages are further increased if the doping profile is also such that is excluded that the second and third space charge zones RLZ 2 and? Hit LZ 3 while operating the transistor.
- a parasitic NPN transistor extends from the n base via the p collector to the n well. Because of the required complete depletion of the p-collector, to which the n-well has a considerable share, on the one hand the base of this NPN transistor is comparatively weak and the emitter of the NPN transistor is comparatively highly doped. The result is a high current gain and a low collector-emitter punch-through breakdown voltage. Therefore, the differential voltage between the n-well and the n-base of the PNP transistor must be kept low. Another reason for this is the desired blocking voltage between the p-collector and the n-well, because of the intended depletion of the p-collector (from below). In order to avoid the n-well as the fourth connection of the transistor, which requires separate shading, the following two options are available:
- the n-well is connected to the emitter.
- the voltage difference between the n-base and the n-well is limited to a diode flux voltage of approx. 0.7 V.
- An advantage of this configuration is that the n-well is always at a higher potential than - even when the transistor is saturated the collector and thus the substrate PNP (coUector connection - n-well - substrate) always remains blocked, thereby avoiding an unwanted substrate current.
- the n-tub can also be connected to the base. This deactivates the parasitic NPN transistor (n-base / p-collector / n-well) because its collector-emitter path is short-circuited. As a result, the PNP transistor can be operated at higher collector currents than with a connection between the n-well and the emitter. In the latter case, the parasitic NPN, in the (quasi) saturation case, the base-emitter path of the Main PNP transistor short, leading to a premature drop in current gain. This disadvantage is avoided with the n-well at the base, but it is purchased through a substrate current in the (quasi) saturation case.
- collector doping The relationship between the collector doping and the collector base or collector emitter reverse voltage is explained in more detail below.
- the (p) collector Since the (p) collector is located within the n-well or above the concentration maximum of the well profile, i.e. is less deep below the base than in the case of the NPN transistor, the result would be a smaller U CEO for a highly doped collector than for the NPN transistor with a highly doped collector (n-well), assuming that for NPN and PNP - Transistors the same implantation depth or energy is used. As a result, the (p) collector must be completely depleted even at lower (negative) collector voltages compared to the base, so that this results in an upper limit for the (p) collector doping and thus for the collector conductivity. A complete depletion with smaller collector voltages initially means that the maximum permitted (p) collector dose is rather lower than with the NPN transistor. However, since the p-collector is not only depleted from above by the n-base, but also from below by the N-well, which is more highly doped than the p-collector, the disadvantage of the smaller U CEO is at least partially compensate
- the n-well for the PNP transistor performs the same function as the substrate for the NPN transistor. The difference, however, is that with the PNP transistor, the collector-volume doping concentration is lower than that of the n-well underneath. In the case of the NPN transistor, on the other hand, the collector-volume doping concentration is higher than that of the underlying substrate. As a result, the space charge zone under the collector of the PNP transistor has a higher penetration capacity than that of the? NPN with the same applied voltage. In order to be able to operate the PNP transistor at supply voltages above the avalanche breakdown voltage between the p-collector connection and the n-well, the n-well must be completely depleted in this area before the avalanche breakdown begins.
- the doping profile and the field strength curve correspond to the NPN transistor in the area of the p-base.
- the difference, however, is that complete depletion only has to start at a significantly higher voltage, which corresponds to the U CBO for the NPN transistor.
- the resulting upper limit for the implantation dose of the n well is therefore higher than in the case of the NPN transistor.
- FIG. 6 shows the doping concentration N and the field strength E as a function of the depth along the line C-C of FIG. 4g.
- This section plane does not include the n-doped zone 14.
- the second and third space charge zones RLZ 2 and RLZ 3 again penetrate the n-well 11 when the transistor is operating with a decreasing collector potential. Since the substrate is connected to the negative potential within the circuit in which the transistor is used, it is always on top of that Collector potential or more negative. However, the potential of the n-well is at or at least close to the base potential. It can therefore be assumed that the reverse voltage at the third space charge zone RLZ 3 is at least as large as that at the second space charge zone RLZ 2.
- the doping concentration is chosen to be sufficiently low so that the space charge zones meet before the critical field strength for a breakthrough between the connector and the n-well is reached, this breakthrough is suppressed.
- the blocking voltages are increased even further if there is also a doping concentration in this sectional plane, which is created in such a way that the second and third space charge zones meet with decreasing collector potential during operation of the transistor before the critical field strength for a breakdown between the connector connection and n-tub is reached. Since the p-collector can in general assume any potential between ground and supply voltage, the punch-through breakdown of the substrate PNP transistors (coUector connection - n-well - substrate) must be avoided - similar to the NPN transistor. This results in a further lower limit for the implantation dose of the n-well.
- FIGS. 7a to 7d show the method steps for producing a PNP transistor in the n-substrate.
- the individual process steps correspond to the steps in FIGS. 1a to 1g, which illustrate the manufacturing process for the NPN transistor in the p-type substrate.
- the structure of the PNP transistor in the n-substrate differs from the NPN transistor in the p-substrate only in that all p-dopings are replaced by n-dopings and all n-dopings are replaced by p-dopings. Otherwise, the process steps are the same.
- the corresponding layers are therefore also provided with the same reference symbols. The same relationships apply between the level of the blocking voltages and the doping concentration.
- FIGS. 4a to 4g show the process steps for producing an NPN transistor in the n-substrate.
- the individual process steps again correspond to the process steps for producing the PNP transistor in the p-substrate, which illustrate FIGS. 4a to 4g.
- all p-dopings are replaced by n-dopings and all n-dopings by p-doping.
- the corresponding layers are therefore also provided with the same reference symbols.
- the same relationships between the level of the blocking voltages and the doping concentration also apply.
- the complementary process using a weakly n-doped substrate is an advantageous embodiment in that a p-well takes the place of the n-well. If the p-well is created with a boron ion implantation, the same can be done with much smaller ion energies Trough depth is reached or deeper troughs are generated with the same ion energy.
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Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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DE102004016992A DE102004016992B4 (en) | 2004-04-02 | 2004-04-02 | Method for producing a bipolar transistor |
PCT/EP2005/003129 WO2005098960A2 (en) | 2004-04-02 | 2005-03-24 | Bipolar-transistor and method for the production of a bipolar-transistor |
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Publication Number | Publication Date |
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EP1730785A2 true EP1730785A2 (en) | 2006-12-13 |
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EP05728216A Withdrawn EP1730785A2 (en) | 2004-04-02 | 2005-03-24 | Bipolar-transistor and method for the production of a bipolar-transistor |
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US (1) | US7563685B2 (en) |
EP (1) | EP1730785A2 (en) |
JP (1) | JP5031552B2 (en) |
DE (1) | DE102004016992B4 (en) |
WO (1) | WO2005098960A2 (en) |
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US7550787B2 (en) * | 2005-05-31 | 2009-06-23 | International Business Machines Corporation | Varied impurity profile region formation for varying breakdown voltage of devices |
US9006864B2 (en) * | 2012-11-06 | 2015-04-14 | Texas Instruments Incorporated | Radiation induced diode structure |
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JPS5753977A (en) * | 1980-09-17 | 1982-03-31 | Matsushita Electronics Corp | Transistor |
JPS59189671A (en) * | 1983-04-13 | 1984-10-27 | Nec Corp | Semiconductor device |
US4639761A (en) | 1983-12-16 | 1987-01-27 | North American Philips Corporation | Combined bipolar-field effect transistor resurf devices |
JPH0494545A (en) * | 1990-08-10 | 1992-03-26 | Fujitsu Ltd | Bipolar transistor |
JPH0750306A (en) * | 1993-08-05 | 1995-02-21 | Sharp Corp | Manufacture of bipolar transistor |
US5656531A (en) * | 1993-12-10 | 1997-08-12 | Micron Technology, Inc. | Method to form hemi-spherical grain (HSG) silicon from amorphous silicon |
JPH08195399A (en) | 1994-09-22 | 1996-07-30 | Texas Instr Inc <Ti> | Insulated vertical pnp transistor dispensing with embedded layer |
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2004
- 2004-04-02 DE DE102004016992A patent/DE102004016992B4/en not_active Expired - Fee Related
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2005
- 2005-03-24 EP EP05728216A patent/EP1730785A2/en not_active Withdrawn
- 2005-03-24 US US11/547,532 patent/US7563685B2/en active Active
- 2005-03-24 JP JP2007505455A patent/JP5031552B2/en active Active
- 2005-03-24 WO PCT/EP2005/003129 patent/WO2005098960A2/en not_active Application Discontinuation
Non-Patent Citations (1)
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See references of WO2005098960A2 * |
Also Published As
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JP2007531292A (en) | 2007-11-01 |
DE102004016992B4 (en) | 2009-02-05 |
DE102004016992A1 (en) | 2005-10-27 |
JP5031552B2 (en) | 2012-09-19 |
WO2005098960A2 (en) | 2005-10-20 |
WO2005098960A3 (en) | 2006-04-20 |
US20070273007A1 (en) | 2007-11-29 |
US7563685B2 (en) | 2009-07-21 |
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