EP1724940A1 - RAKE receiver for radiomobile devices - Google Patents

Abstract

Rake receiver device has step-down transformer (DC), which converts the signal supplied by the antenna into an analog time discrete signal. A delay system is provided, at whose input, an analog, time discrete signal produced by step-down transformer is applied and has number of outputs. Plurality of amplifier is provided, to which, in each case, a delayed imaging is supplied. A path selector is provided for controlling the plurality of amplifier, and at least a combined capacitor is provided on the plurality of output signal of the amplifier depending on the controlling of the switching of the path selector. A transformer device is provided for transforming the analog time discrete signal on the output side of the combined capacitor into the digital symbols for the base band signal processing.

Description

The invention relates to a RAKE receiver arrangement for mobile devices, as they can be used in the prior art in particular for applications of the mobile radio standard UMTS.

It is known to realize such RAKE receiver arrangements in the area of baseband signal processing of a mobile radio device. These receiver arrays are designed to process a composite input signal provided by an antenna and composed of sub-signals associated with different propagation paths such as to allow constructive superposition of the sub-signals received on the various propagation paths. This results in an improved signal-to-noise ratio for the digital signal to be supplied for further baseband signal processing.

Basic elements of such RAKE receiver arrays are a delay arrangement that provides various time-delayed images of the input signal, each supplied to a different RAKE finger. To select just relevant RAKE fingers is used a search device which examines an input signal received from the antenna on its temporal structure and thus determines suitable delay times for the individual RAKE fingers, so that a constructive overlay within a combiner of the RAKE receiver arrangement of equip can. All mentioned components of a known RAKE receiver arrangement are realized in the digital baseband of a receive path for a mobile device. This means that consuming for baseband signal processing Circuits are required to implement the RAKE receiver arrangement.

Proceeding from this, the object of the invention is to specify a RAKE receiver arrangement in which the technical realization is less complicated.

This object is achieved by a RAKE receiver arrangement according to the patent claim 1.

Thereafter, a PAKE receiver arrangement for mobile devices is provided,
in which
a down converter is provided which converts a signal supplied by the antenna into an analog, time discrete signal,
a delay arrangement is provided at the input of which the analog, discrete-time signal generated by the buck converter is applied and which has a plurality of outputs, each of which provides a different time-delayed image of the time-discrete analog signal,
a plurality of amplifiers is provided, to each of which one of the delayed images of the analog, time-discrete signal are supplied and which are adjustable in their gain,
a path selector is provided for controlling the plurality of amplifiers,
at least one combiner capacitor is provided, to which a plurality of output signals of the amplifier, depending on a control of the path selector, can be switched through and
converter means are provided for converting an analog time discrete signal present on an output side of the combining capacitor into digital symbols for baseband signal processing.

With such a RAKE receiver arrangement, a major portion of signal processing for obtaining within the range of the signal supplied to the antenna in an analog area. While, for example, known RAKE receivers already undertake an analog / digital conversion of the input signals at a very early stage, whereby the delay arrangement already operates with digital signals, according to the invention use is made of analog signal processing at this point.

In this case, the down converter, but also the delay arrangement, the amplifiers and the combination capacitor are preferably implemented using CMOS technology. In this respect, a digital radio processor (DRP) can be used to implement the buck converter and all other components that can be produced using CMOS technology. This technology, for example, allows the signal supplied by the antenna to be sampled at a very high frequency, such as more than one GHz, so that the signal delivered by the antenna can be converted with high temporal resolution into a sequence of temporally successive analog signal values. In this case, the buck converter typically operates within the RAKE receiver arrangement with the highest operating frequency, so that the other, also implemented in CMOS technology components of the RAKE receiver arrangement make lower demands on a required operating frequency.

Each amplifier is preferably designed as a complex amplifier and comprises four sub-amplifiers, which are controlled by a pseudo-noise generator. For example, if the signals provided by the antenna are UMTS signals using a spreading code discriminated multiple access method (W-CDMA), it is the pseudo-noise generator's task, for example, to despread both the signals provided by the delay device and to execute a so-called. Descrambling, wherein a so-called scrambling code for distinguishing different base stations of a Mobile network is used. In the context of despreading and descrambling the analog signals present at the amplifiers, it may happen that the sequences provided by the pseudo-noise generator for this purpose are complex. Therefore, the training of these amplifiers is recommended as a complex amplifier.

In order to carry out in a conventional manner parallel processing of in-phase and quadrature signal components of the signals received by the antenna, it is advantageous that the plurality of amplifiers are divided into in-phase amplifiers and quadrature amplifiers and a second combining capacitor is provided so that the first combiner capacitor is associated with an in-phase signal component and the second combiner capacitor is associated with a quadrature signal component.

For prefiltering the output signals supplied by the two combining capacitors, a sigma-delta converter is preferably used whose output signal is supplied to a decimation filter which integrates the digital output signal of the sigma-delta converter into the digital symbols.

The decimation filter used, which can be implemented as a cascaded integration comb filter and whose execution is preferably adapted to the realization of the sigma-delta converter, advantageously results in a reduction of a sampling rate of the analog, time-discrete signal. For example, UMTS operates at a symbol rate in the baseband of less than one MHz, so that the decimation filter, while ensuring a favorable signal-to-noise ratio, reduces the sampling rate of the signals coming from the Kornbinier capacitors.

Preferably, the down converter is for sampling the signal provided by the antenna into the analog time discrete signal at a rate higher than the chip rate of the analog signal Antenna received signal executed. This ensures oversampling of the received signal, which improves signal-to-noise ratio for subsequent signal processing and is favorable for the sigma-delta converter and the decimation filter. This is based on the fact that in general for an analog-to-digital conversion, the bandwidth of the signal to be converted should be significantly above the bandwidth of the output signal (Nyquist theorem).

A preferred value range for the sampling rate of the buck converter is adapted to a carrier frequency of the signal received by the antenna.

Figur 1

eine schematische Übersichtsdarstellung einer RAKE-Empfängeranordnung ohne Analog-/Digital-Wandlung,

Figur 2A, 2B

jeweils einen komplexen Verstärker für einen In-Phase-Signalanteil und einen Quadratur-signalanteil zum Einsatz bei der RAKE-Empfängeranordnung nach Figur 1 und

Figur 3

ein Blockschaltbild der RAKE-Empfängeranordnung insgesamt.

The invention will be described in more detail by way of example with reference to the drawings. Show it:

FIG. 1

FIG. 2 is a schematic overview of a RAKE receiver arrangement without analog / digital conversion. FIG.

FIGS. 2A, 2B

each a complex amplifier for an in-phase signal component and a quadrature signal component for use in the RAKE receiver arrangement of Figure 1 and

FIG. 3

a block diagram of the RAKE receiver assembly as a whole.

The overview of Figure 1 shows on an input side of the RAKE receiver arrangement, an antenna A of a communication terminal, which may be, for example, a base station or a mobile communication terminal of a mobile radio system. The input signal is in a conventional manner a modulated carrier signal, wherein in the present case the example of a UMTS signal is to be considered, in which various communication links within a mobile radio cell with the same carrier frequency, but differ by different spread signals (CDMA method). However, the presented RAKE receiver arrangement can basically be used for all mobile radio standards in which multipath reception is to be realized.

The signal received by the antenna A passes through a low-noise amplifier, which is typically provided and is not shown in the figure, to a down converter DC, which samples the UMTS signal, for example at a frequency of 2 GHz, and at a frequency of 500 MHz decimated. Since the UMTS chip rate is 3.84 Mchip / s, the down converter DC provides a heavily oversampled analog signal S on its output side. This output signal contains an in-phase component S _I and a quadrature component S _Q. The complete signal S arrives at a delay arrangement which has a multi-stage design and provides delay stages V ₁ , V ₂ ,..., V _n . The delay arrangement is implemented as an analog discrete-time shift register which provides time-shifted images of the time-discrete analog signal S from the down converter DC with its taps.

Both the original analog time-discrete signal S and its delayed images, generated by the delay stages V ₁ , V ₂ ,..., V _n , are supplied to two different amplifier arrangements VI, VQ, the amplifier arrangement VI being for an in-phase amplifier. Signal component and the amplifier arrangement VQ is provided for a quadrature signal component. For the sake of clarity, only the amplifier arrangement VI is shown in detail in FIG. 1, while the amplifier arrangement VQ belongs to a combination arrangement K _Q , which is shown as a block in FIG.

The amplifier arrangement VI is composed of parallel-connected amplifiers VI ₀ VI ₁ VI _2, ..., _n VI, each of said amplifier VI ₁ VI ₂ VI _3, ... _n as VI Input signal is a different delayed image, the original analog time-discrete signal S from the buck converter DC receives as input signal. Associated delay stages V ₁ , V ₂ , ..., V _n , and amplifiers VI ₁ , VI ₂ , ..., VI _n each together form a RAKE finger in a conventional sense.

Each of the amplifiers VI ₀ , VI ₁ , VI ₂ , ..., vI _n is controlled in its gain by an associated factor C ₀ , C ₁ , ..., C _n , which channel characteristics of the respective delayed image of the original signal S considered.

For selecting output signals of those amplifiers from the amplifiers VI ₀ , VI ₁ , VI ₂ , ..., VI _n , which in fact correspond to an existing propagation path of the signal received by the antenna A, a path selector PS is provided, in which Help of a searcher, which makes a rough version of those gain levels to which actual propagation paths are assigned, information on which output signals of the amplifier VI ₀ , VI ₁ , VI ₂ , ..., VI _n , are to be switched. Switched output signals of the amplifiers VI ₀ , VI ₁ , VI ₂ , ..., VI _n are combined into a total signal, which is supplied to a combiner capacitor C _I for a later analog / digital conversion. The amplifiers VI ₀ , VI ₁ , VI ₂ ,..., VI _n together with the combining capacitor C _{I form} a combining device K _I for the in-phase signal component.

Thus, the output signal of the combiner K _{I represents} the in-phase signal component S _K , wherein payload signals based on multipath propagation are added together. The same applies to the combination arrangement K _Q , which refers to the quadrature component S _K.

The signal processing for the in-phase component S _I will be explained below, such as the despreading required in CDMA methods such as CDMA 2000 or WCDMA Descrambling on the amplifiers VI ₀ , VI ₁ , VI ₂ , ..., VI _{n is} made. In a known manner, but there for digital signal processing, a pseudo-noise generator PG generates a sequence P = P _I + iP _Q , which is suitable for these purposes. The influence of the pseudo-noise generator PG is illustrated with reference to FIGS. 2A, 2B, wherein FIG. 2A shows one of the identically constructed amplifiers VI ₀ , VI ₁ ,..., VI _n for the in-phase signal component S _I. FIG. 2B illustrates a corresponding amplifier for the quadrature signal component S _{Q of} a propagation path of the output signal received via the antenna A. For simplicity, the in-phase signal component S _I and the quadrature signal component S _{Q are} denoted by the same reference numerals as the respective components of the output signal S, because they differ only by different time delays due to the delay arrangement. For both amplifiers, the pseudo-noise generator PG provides an in-phase sequence P _I and a quadrature sequence P _Q. The amplifier VI ₀ of Figure 2A comprises a total of four sub-amplifiers VU ₁ , ..., VU ₄ , whose outputs are connected together. The two sub-amplifiers VU ₁ , VU ₂ are controlled in terms of their gain by the quadrature channel coefficient C _Q , while the sub-amplifiers UV ₃ , UV ₄ are acted upon in terms of their gain factor of the in-phase channel coefficient C _I. At the sub-amplifiers VU ₂ and VU ₄ is present as the input of the corresponding propagation path associated quadrature signal component S _I , while the sub-amplifiers UV ₁ , UV ₃ receive as input the in-phase signal component S _Q same propagation path.

With regard to the channel coefficient C, which is complex-valued, C = C _I + iC _Q applies in this context.

The sub-amplifiers UV ₁ , UV ₂ and UV ₄ are controlled by the quadrature sequence P _Q , wherein in each case an inverter is connected upstream, while the sub-amplifier UV ₃ are controlled by the in-phase sequence P _I. The effect of the just circuit arrangement of the amplifier VI ₀ is the one that has at its output by means of a summation capacitor C _SI an analog, time-discrete and the in-phase signal component S _{I of} the respective propagation path reproducing signal which is despread and has undergone descrambling.

The amplifier VQ ₀ illustrated in FIG. 2B corresponds in circuit terms to the amplifier VI ₀ explained with reference to FIG. 2A, so that in FIG. 2B functionally similar components are designated by the same reference symbols as in FIG. 2A. The only difference is that the sub-amplifier VU ₂ is the only sub-amplifier to receive the quadrature sequence P _Q from the pseudo-noise generator PG via an inverter. The circuit of the amplifier VQ ₀ is designed such that a quadrature signal is generated at a summation capacitor C _Q , which corresponds to an associated propagation path. Figure 1 is simplified in that the lines for P and S are shown only as one line, but in fact consist of a line pair, namely a line for I and a line for Q.

In addition, both amplifiers VI ₀ , VQ ₀ each have a switch SW, which is controlled by the already explained above in its operation path selector PS, that is closed when the relevant delayed image of the output signal S is associated with an actual propagation path of the multipath signal ,

The combiner arrangements K _Q and K _I operate in the processing of a UMTS signal, for example, with a clock frequency of 500 MHz (sampling at 2 GHz), which corresponds to about a quarter of the sampling frequency, is operated with the buck converter DC.

After the now combined quadrature and in-phase signal components have been generated due to the multipath reception are still present discrete-time analog signals, is now still their analog / digital conversion and conversion to in-phase symbols and quadrature symbols.

The output signals SK _I , SK _{Q of} the two combiner arrangements K _I , K _Q are fed to a sigma-delta converter SD, wherein there is still a strongly oversampled signal. Output signals of the sigma-delta converter in the form of a bit stream arrive at a decimation filter D implemented as a cascaded integrator comb filter, which simultaneously integrates the signal chips into in-phase symbols and quadrature symbols and adapts the sampling rate to the rate suitable for UMTS for further baseband signal processing.

It should be emphasized that all components shown in FIG. 3 can be implemented on a single digital radio processor (DRP).

Claims (8)

RAKE receiver arrangement for mobile devices,
characterized,
in that a down converter (DC) is provided which converts a signal (S) supplied by the antenna (A) into an analog, time-discrete signal,
a delay arrangement is provided at the input of which the down-converter (DC) generated analog discrete-time signal (S) is applied and which has a plurality of outputs, each of which provides a different time-delayed image of the time-discrete analog signal (S),
a plurality of amplifiers (VI ₁ , VI ₂ , ..., VI _n ) is provided, to each of which one of the delayed images of the analog, time-discrete signal (S) are fed and in their gain factor (C ₀ , C ₁ , .. ., C _n ) are adjustable,
a path selector (PS) is provided for controlling the plurality of amplifiers (VI ₁ , VI ₂ , ..., VI _n ),
at least one combiner capacitor (C _I ) is provided, to which a plurality of output signals of the amplifier (VI ₁ , VI ₂ , ..., VI _n ), depending on a control of the path selector (PS), is switched through and
a converter means is provided for converting an analog time-discrete signal (S) present on an output side of the combining capacitor (C _I ) into digital symbols for baseband signal processing. RAKE receiver arrangement according to claim 1,
characterized,
that the buck converter (DC) is realized in CMOS technology. RAKE receiver arrangement according to one of claims 1 to 2,
characterized,
that each amplifier (VI _1, V1 _2, ..., _n VI) is formed as a complex amplifier and comprises four sub-amplifier, by a pseudo-noise generator are controlled. RAKE receiver arrangement according to one of claims 1 to 3,
characterized,
that the plurality of amplifiers (VI ₁ VI _2, ..., _n VI) in the in-phase and quadrature amplifier amplifiers are divided, and a second combining capacitor (C _I) is provided, so that the first capacitor combining (C _I ) is associated with an in-phase signal component (S _I ) and the second combination capacitor (C _I ) is associated with a quadrature signal component (S _Q ). RAKE receiver arrangement according to one of claims 1 to 4,
characterized,
in that the converter device has a sigma-delta converter whose output signal is fed to a decimation filter which integrates the output signal of the sigma-delta converter into the digital symbols. RAKE receiver arrangement according to claim 5,
characterized,
in that the decimation filter is designed to reduce a sampling rate of the analog, time-discrete signal (S). RAKE receiver arrangement according to one of claims 1 to 6,
characterized,
in that the down-converter (DC) for sampling the signal (S) delivered by the antenna (A) into the analog time-discrete signal (S) has a rate higher than a chip rate of the signal received by the antenna (A) ( S) is executed. RAKE receiver arrangement according to claim 7,
characterized,
in that the sampling rate applied to the output of the down-converter (DC) corresponds to an integral divider of a carrier frequency of the signal supplied by the antenna (A).

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