EP1709533A2 - Method and related device for use in decoding executable code - Google Patents
Method and related device for use in decoding executable codeInfo
- Publication number
- EP1709533A2 EP1709533A2 EP05702640A EP05702640A EP1709533A2 EP 1709533 A2 EP1709533 A2 EP 1709533A2 EP 05702640 A EP05702640 A EP 05702640A EP 05702640 A EP05702640 A EP 05702640A EP 1709533 A2 EP1709533 A2 EP 1709533A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- code
- bit
- sub
- portions
- shuffling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000004590 computer program Methods 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 2
- 238000003066 decision tree Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44521—Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44557—Code layout in executable memory
Definitions
- the present invention relates to a method and related device for use in decoding executable code in processors such as VLIW processors and in particular in a run-time operating system for use, in particular, for the loading and relocation of processor executables in memory.
- TriMedia executables are examples of such codes as discussed above and subsequent to the patching of the executable, the text segment containing the TriMedia executable code has to be bit-shuffled in order to allow the processor to decode the executable in a cache-efficient manner, specifically at run-time.
- bit-shuffling comprises a memory- intensive, and computationally expensive operation and is also found to be proportional to the size of the program being loaded.
- bit-shuffling forms a major component of the load-time experienced.
- run-time operating systems such as where it is required that executables be loaded frequently, or where large statically linked programs are to be loaded, such bit-shuffling operations are considered to represent considerable restraints on performance.
- the present invention seeks to provide for a method and related device for use in decoding executable code in a run-time operating system and which exhibits advantages over known such methods and devices.
- a method for use in decoding executable code in a processing system including bit-shuffling code, and including the steps of: dividing the code into a plurality of sub-portions; identifying sub-portions of the code that can be bit-shuffled prior to processing; and bit-shuffling the said identified sub-portions prior to processing so as to reduce the processing bit-shuffling required.
- the invention can advantageously be applied to processing stages on pre-shuffled binaries, for example linking pre-shuffled binary object code during a later link time phase.
- the processing system comprises a run time operating system and involving bit shuffling at run time and the identification of sub-portion that can be bit shuffled prior to run time.
- the pre-shuffling of the said a portion of the code can lead to a reduction in the run-time shuffling delays within the order of 20-25% and this advantageously serves to increase the executable load and relocate time. Improved run-time performance can therefore be achieved and it will be appreciated that the invention proves particularly advantageous when handling TriMedia programs and executables.
- the method includes the step of, at link time, generating a relocation patch-up table for the loading and relocation of the code.
- the relocation patch-up table is examined at the end of the aforesaid linking so as to determine which addresses in the code are patched.
- the method includes the step of generating a record of the sub-portions to be patched and shuffled at run-time in the form of a bitmap.
- the invention may also include the step of reading code elements within a program loader for the execution of the program. Then, the program loader can be arranged to read the relocation patch- up table and the executable code and write the result back within the executable code.
- decoding apparatus for decoding executable code in a processor and including means for bit-shuffling code, the apparatus further comprising: means for dividing the code into a plurality of sub-portions; means for identifying sub- portions of the code that can be bit-shuffled prior to processing; and means for bit-shuffling the said identified sub-portions prior to processing so as to reduce the processing bit-shuffling required.
- the processor comprises a run-time operating system.
- the application includes means for generating a relocation patch-up table for the loading and relocation of the code at link time.
- the invention can include means for bit-shuffling the identified sub-portions at link time.
- Fig. 1 comprises a schematic block diagram illustrating the generation of the program executable image in accordance with an embodiment of the present invention
- Fig. 2 is a schematic block diagram illustrating the loading and relocating of the program executable image of Fig. 1.
- the bit-shuffling operation is advantageously manipulated such that the shuffling operation is conducted against sub-portions of the code, which sub-portions advantageously comprise cache-sized blocks.
- the code can be broken down into instruction cache-sized blocks in the form of 64 byte blocks.
- pre-shuffling of non-patched 64 byte blocks advantageously serves to reduce the run-time shuffling overhead commonly experienced by 20-25% leading to an advantageous increase in the executable load and relocate time.
- the invention advantageously provides for the bit-shuffling prior to run-time and as the program is being linked. At link time, therefore, the linker is advantageously arranged to generate a relocation patch-up table for the loading and relocation of the executable at run-time.
- the linker is arranged to examine the relocation patch-up table to determine which addresses in the text segment are then patched. Through identification of such patched segments, it is readily identified which of the 64 byte blocks need to be patched and shuffled at runtime. The 64 byte blocks that are not affected by patching are then pre- shuffled at link time and a record of which blocks are to be patched and shuffled at run-time is generated by the linker in the form of a bitmap which is advantageously added to the executable image. Such a bitmap can advantageously be arranged with each single bit representing a 64 byte block in the executable text segment.
- Fig. 1 there is illustrated, in schematic block form, an arrangement according to the present invention for producing a program executable image having pre-shuffled portions of code.
- a program linker 12 arranged to read object files 14A, 14B so as to link the objects together and thereby form the required program executable image.
- a table 16 of the addresses of the text segment to be patched is formed within the linker 12 and a 64 byte block of the text segment not requiring patching at run-time is then pre-shuffled by a Text Segment Pre-Shuffler 20 through reference to the table 16 of text segment patch addresses 18.
- the executable 22 can then be read out in the directions of arrows B and contains a executable header 24 for example an a.out or ELF header, a shuffle bitmap 26 indicating which 64 byte blocks of the text segment that remain need shuffling at run-time, a relocation patch-up table 28 arranged to patch the text and data segments at run-time, text and data segments 30, 32 and a BSS segment 34.
- a executable header 24 for example an a.out or ELF header
- a shuffle bitmap 26 indicating which 64 byte blocks of the text segment that remain need shuffling at run-time
- a relocation patch-up table 28 arranged to patch the text and data segments at run-time
- text and data segments 30, 32 and a BSS segment 34 arranged to patch the text and data segments 30, 32 and a BSS segment 34.
- a program loader 36 is arranged for reading the relocation patch-up table and shuffle bit-map and executable text code as indicated by way of arrows B and C, from the executable image 22 and serves to relocate the image and write this back as relocated text segment 30 as indicated by means of arrow D.
- the program loader 36 then reads the shuffle bitmap bit by bit as indicated by arrow A and this determines if each 64 byte block of the text segment needs to be shuffled by a text segment shuffler 38 found within the program loader 36.
- the text segment shuffler 38 can read the 64 byte block from the text segment as indicated by arrow C and then shuffle it, and write it back, as indicated by arrow D.
- the advantages offered by the present invention are applicable for use with any executable code required within a run-time operating system such as TriMedia executable code that has to be loaded and relocated before execution.
- the invention applies not only to program executables but also to runnable libraries, such as TriMedia dynamic link libraries (DLL's).
- the loading of programs and libraries is generally undertaken either by loader library, for example in a pSOS real time operating system, or by a binary loader function such as in monolithic kernels in UNIK- like operating systems such as Linux, or real-time operating systems.
- loader library for example in a pSOS real time operating system
- binary loader function such as in monolithic kernels in UNIK- like operating systems such as Linux, or real-time operating systems.
- a particularly advantageous use of the present invention is with an operating system that has to load and relocate TriMedia executable code.
- the invention is not restricted to the details of the foregoing embodiment.
- the concept is not restricted to use with a run-time operation system but is equally applicable to, for example, processing stages on pre-shuffled binaries such as listing pre-shuffled binary object code during a later link time phase.
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Storage Device Security (AREA)
- Stored Programmes (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Devices For Executing Special Programs (AREA)
- Executing Machine-Instructions (AREA)
- Circuits Of Receivers In General (AREA)
- Error Detection And Correction (AREA)
- Indexing, Searching, Synchronizing, And The Amount Of Synchronization Travel Of Record Carriers (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GBGB0400660.7A GB0400660D0 (en) | 2004-01-13 | 2004-01-13 | Method and related device for use in decoding executable code |
PCT/IB2005/050122 WO2005069124A2 (en) | 2004-01-13 | 2005-01-11 | Method and related device for use in decoding executable code |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1709533A2 true EP1709533A2 (en) | 2006-10-11 |
EP1709533B1 EP1709533B1 (en) | 2008-07-16 |
Family
ID=31503817
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP05702640A Active EP1709533B1 (en) | 2004-01-13 | 2005-01-11 | Method and device for use in decoding executable code |
Country Status (8)
Country | Link |
---|---|
US (1) | US7334111B2 (en) |
EP (1) | EP1709533B1 (en) |
JP (1) | JP4751835B2 (en) |
CN (1) | CN100533379C (en) |
AT (1) | ATE401602T1 (en) |
DE (1) | DE602005008196D1 (en) |
GB (1) | GB0400660D0 (en) |
WO (1) | WO2005069124A2 (en) |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0475137A (en) * | 1990-07-18 | 1992-03-10 | Hitachi Ltd | Data processor |
WO1994027216A1 (en) * | 1993-05-14 | 1994-11-24 | Massachusetts Institute Of Technology | Multiprocessor coupling system with integrated compile and run time scheduling for parallelism |
US6131152A (en) * | 1996-05-15 | 2000-10-10 | Philips Electronics North America Corporation | Planar cache layout and instruction stream therefor |
US5862398A (en) * | 1996-05-15 | 1999-01-19 | Philips Electronics North America Corporation | Compiler generating swizzled instructions usable in a simplified cache layout |
CN1145099C (en) * | 1996-05-15 | 2004-04-07 | 特莱麦迪雅技术公司 | Processor with instruction cache |
US6745319B1 (en) * | 2000-02-18 | 2004-06-01 | Texas Instruments Incorporated | Microprocessor with instructions for shuffling and dealing data |
-
2004
- 2004-01-13 GB GBGB0400660.7A patent/GB0400660D0/en not_active Ceased
-
2005
- 2005-01-11 CN CNB2005800022936A patent/CN100533379C/en active Active
- 2005-01-11 EP EP05702640A patent/EP1709533B1/en active Active
- 2005-01-11 AT AT05702640T patent/ATE401602T1/en not_active IP Right Cessation
- 2005-01-11 US US10/585,801 patent/US7334111B2/en active Active
- 2005-01-11 JP JP2006548546A patent/JP4751835B2/en active Active
- 2005-01-11 DE DE602005008196T patent/DE602005008196D1/en active Active
- 2005-01-11 WO PCT/IB2005/050122 patent/WO2005069124A2/en active IP Right Grant
Non-Patent Citations (1)
Title |
---|
See references of WO2005069124A3 * |
Also Published As
Publication number | Publication date |
---|---|
EP1709533B1 (en) | 2008-07-16 |
ATE401602T1 (en) | 2008-08-15 |
US20070162725A1 (en) | 2007-07-12 |
CN1910551A (en) | 2007-02-07 |
WO2005069124A2 (en) | 2005-07-28 |
US7334111B2 (en) | 2008-02-19 |
CN100533379C (en) | 2009-08-26 |
WO2005069124A3 (en) | 2006-03-16 |
JP2007520811A (en) | 2007-07-26 |
GB0400660D0 (en) | 2004-02-11 |
JP4751835B2 (en) | 2011-08-17 |
DE602005008196D1 (en) | 2008-08-28 |
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