EP1705549A1 - System und Verfahren zur Stromversorgung eines Peripherigerätes - Google Patents

System und Verfahren zur Stromversorgung eines Peripherigerätes Download PDF

Info

Publication number
EP1705549A1
EP1705549A1 EP05102328A EP05102328A EP1705549A1 EP 1705549 A1 EP1705549 A1 EP 1705549A1 EP 05102328 A EP05102328 A EP 05102328A EP 05102328 A EP05102328 A EP 05102328A EP 1705549 A1 EP1705549 A1 EP 1705549A1
Authority
EP
European Patent Office
Prior art keywords
host
peripheral device
current
power
host device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP05102328A
Other languages
English (en)
French (fr)
Other versions
EP1705549B1 (de
Inventor
David Mak-Fan
Dusan Veselic
Max Matton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BlackBerry Ltd
Original Assignee
Research in Motion Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Research in Motion Ltd filed Critical Research in Motion Ltd
Priority to DE602005001197T priority Critical patent/DE602005001197T2/de
Priority to AT05102328T priority patent/ATE363093T1/de
Priority to EP05102328A priority patent/EP1705549B1/de
Priority to CA2540609A priority patent/CA2540609C/en
Publication of EP1705549A1 publication Critical patent/EP1705549A1/de
Application granted granted Critical
Publication of EP1705549B1 publication Critical patent/EP1705549B1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips

Definitions

  • This invention relates to peripheral devices that can be connected to a computer, and more specifically to powering such peripheral devices.
  • Widespread peripheral devices that can be connected to a computer, such as personal data assistants (PDA), cell phones and printers, are powered by the computer to which they are connected, and/or are self-powered by their own power supply, typically a battery pack. When re-charging is necessary, the peripheral device with the battery pack contained therein, can be powered by a computer to re-charge the battery pack.
  • PDA personal data assistants
  • a convenient method to power a PDA in a mobile setting involves the use of a laptop computer. If the PDA is running low on batteries in the field, the PDA can be connected to a battery-operated laptop computer for powering. If one power outlet is available, the computer can be plugged into the one outlet and the PDA can be connected to the computer to power the PDA for recharging the batteries and to provide power to the components of the PDA.
  • Device drivers can be categorized according to the communication standard to which they adhere.
  • USB universal serial bus
  • PCs personal computers
  • USB permits many peripheral device connections at one time.
  • Another convenient USB feature is that it distributes electrical power to many peripherals.
  • USB lets the PC automatically sense the power that is required and deliver it to the device.
  • USB "hot-swapping" obviates the need to shut down and restart the PC to attach or remove a peripheral device: the PC automatically detects the peripheral device and configures the necessary software. This feature is especially useful for users of multi-player games, as well as laptop PC users who want to share peripheral devices.
  • USB As convenient as USB is, however, one major drawback is that the maximum current that one USB port is allowed to supply to a peripheral device is limited to some maximum level, typically 100mA or 500mA. Thus, the rate at which battery packs can be recharged, and the types of devices that can run from the power supplied by a USB host device are curtailed.
  • the present invention addresses the aforementioned drawback of limited available current from a USB port by exploiting the fact that a typical host device comes equipped with a plurality of USB ports.
  • a system for powering a peripheral device with a host device is described below that includes N host interface power ports, where N is an integer greater than zero.
  • Each host interface power port is adapted for coupling to a corresponding host port on the host device to deliver power to the peripheral device.
  • the system for powering further includes a current adding unit for adding current received from the host device via at least the N host interface power ports to produce a total current.
  • a power terminal in the device for powering is coupled to the peripheral device to send the total current from the current adding unit to the peripheral device.
  • Figure 1 shows a block diagram of a system for powering a peripheral device, in accordance with an embodiment of the invention
  • FIG 2 shows the control logic unit and the current adding unit of the system of Figure 1;
  • Figure 3 shows a block diagram of another embodiment of a system for powering a peripheral device.
  • Figure 1 shows a system 10 for powering a peripheral device 12 with a host device 14.
  • the system 10 includes N host interface power ports 16, where N is any integer greater than zero, a host interface data port 18, N microcontrollers 19, a current adding unit 20, a control logic unit 21, a data terminal 22, a power connection 23, a power terminal 24 and N power connections 25, a data connection 27 and N data connections 29.
  • Each of the N host interface power ports 16 is coupled to a corresponding host port 26 on the host device 14 to deliver power to the peripheral device 12.
  • the N host power ports 26 can be universal serial bus (USB) ports that exchange data with and deliver power to the N host interface power ports 16 in conformity with the USB standard.
  • the N host interface power ports 16 are coupled to the N host power ports 26 via cables 30. Power received by the N host interface power ports 16 from the host device 14 is delivered to the peripheral device 12, as described below.
  • the host interface data port 18 is coupled to a host data port 28 on the host device 14 to exchange data between the host device 14 and the peripheral device 12.
  • data received by the host interface data port 18 is transmitted to the data terminal 22, and then to the peripheral device data port 40.
  • the host interface data port 18 can also receive current from the host data port 28 for powering the peripheral device 12. This current can be delivered to the current adding unit 20 by the power connection 23.
  • the host data port 28 can be similar to the N host power ports 26.
  • the host data port 28 can be a USB port that exchanges data with and delivers power to the host interface data port 18 in conformity with the USB standard.
  • the host interface data port 18 can be coupled to the host data port 28 via a cable 32. Data and power received by the host interface data port 18 from the host device 14 is delivered to the peripheral device 12, as described below.
  • Each of the N host interface power ports 16 is coupled to a corresponding microcontroller 19.
  • Each of the N microcontrollers 19 is enumerated by the host device 14 via the respective N host interface power ports 16. The enumeration allows the system 10 to draw current from each of the N host power ports 26 of the host device 14.
  • the N microcontrollers 19 identify themselves to the host device 14 and negotiate the maximum current that can be drawn therefrom. The current received by the N microcontrollers 19 from the host device 14 is delivered to the current adding unit 20 via respective N connections 25.
  • the current adding unit 20 adds current received from the host device 14 via the N host interface power ports 16 and the N microcontrollers 19. In those embodiments in which the host interface data port 18 draws current from the host device 14, like the embodiment shown in Figure 1, the current adding unit 20 also adds current received from the host interface data port 18 via a power connection 23 to produce a total current. Thus, the total current is the current produced by the current adding unit 20 by adding current received from the N host interface power ports 16 and the host interface data port 18.
  • the data terminal 22 of the system 10 is connected to the peripheral device 12 by a data cable 38.
  • Data flows along a path that starts at the host data port 28, travels along the cable 32, crosses the host interface data port 18, travels along the data connection 27, crosses the data terminal 22, and travels along the data cable 38 to the peripheral device data port 40.
  • the power cable 34 and the data cable 38 are one in the same, and can deliver both power and data.
  • the data terminal 22 and the power terminal 24 are coincident, as are the peripheral device power port 36 and the peripheral device data port 40.
  • the system 10 can also include a control logic unit 21 that is coupled to the N microcontrollers 19 for configuring the current adding unit 20 to produce a maximum total current that is available to the peripheral device.
  • the available maximum total current depends on the maximum current that each of the N microcontrollers 19 negotiates with the host device 14.
  • the control logic unit 21 uses enumeration information obtained by the N microcontrollers 19 from the host device 14 and delivered to the control logic unit 21 by the respective N data connections 29. This enumeration information is used by the control logic unit 21 to configure the current adding unit 20 for delivery of the maximum total current available to the peripheral device 12.
  • This maximum total current dictates the speed at which the peripheral device 12 can be charged by the host device 14, for example. If the maximum total current available should change, as the N host interface power ports 16 are disconnected and reconnected, the control logic unit 21 reconfigures the current adding unit 20 accordingly. The maximum rate at which the host device 14 can charge the peripheral device 12 can correspondingly change.
  • the total current that is delivered from the current adding unit 20 to the peripheral device 12 fluctuates as a function of time according to the demands of the peripheral device 12.
  • the maximum total current is set by the control logic unit 21 according to what was negotiated between the N microcontrollers 19 and the host device 14 during the enumeration process, as described in more detail below.
  • the system 10 allows the total current delivered to the peripheral device 12 to be larger than could be delivered from the host interface data port 18 alone. For example, if each one of the N host interface power ports 16 and the host interface data port 18 is constrained by the USB standard to deliver a maximum of 500mA of current, then the current adding unit 20 adds the individual currents to make available a maximum total current of (N+1)x500mA to the peripheral device 12, instead of just 500mA from the one host data port 28. To deliver this current to the peripheral device 12, the current adding unit 20 sends this maximum total current to the power terminal 24, which is coupled to the peripheral device 12 by a power cable 34. From the power terminal 24, the total current is delivered to the peripheral device 12 via the power cable 34 at a peripheral device power port 36.
  • the processor 19' includes a VBUS1 terminal 50, an ENbus1 terminal 52, an 1100bus1 terminal 54 and an 1500busl terminal 56.
  • the processor 19" includes a VBUS2 terminal 60, an ENbus2 terminal 62, an 1100bus2 terminal 64 and an 1500bus2 terminal 66.
  • the 1100bus1 terminal 54 is coupled to a first FET 70 of the control logic unit 21, and the 1500busl terminal 66 is coupled to a second FET 72 of the control logic unit 21.
  • the l100bus2 terminal 64 is coupled to a third FET 74 of the control logic unit 21, and the l500bus2 terminal 66 is coupled to a fourth FET 76 of the control logic unit 21.
  • the control logic unit 21 further includes four resistors 78-81.
  • the current adding unit 20 includes an EN1 terminal 82 coupled to the ENbus1 terminal 52, and an Iset1 terminal 84 coupled to the first and second FETs 70 and 72.
  • the current adding unit 20 also includes an EN2 terminal 86 coupled to the ENbus2 terminal 62, and an lset2 terminal 87 coupled to the third and fourth FETs 74 and 76.
  • the current adding unit 20 further includes an in1 terminal 88 and an in2 terminal 90 respectively coupled to the VBUS1 terminal 50 and the VBUS2 terminal 60, via respective power connections 25' and 25".
  • An out1 terminal 92 and an out2 terminal 94 of the current adding unit are coupled to the power terminal 24.
  • the microcontrollers 19' and 19" negotiate the maximum current that each can draw from the host device 14 via the N host power ports 26 and the N host interface power ports 16 to which they are coupled. If the N host power ports 26 are USB ports, then typically the host device 14 offers a choice of two maximum currents, 100mA and 500mA. If the microcontrollers 19' and 19" negotiate for a maximum current of 100mA each, then respective voltages are asserted on the l100bus1 terminal 54 and the l100bus2 terminal 64 via the data connections 29' and 29", which close the gates on the first and third FETS 70 and 74. These steps result in a voltage being applied at the Iset1 terminal 84 and at the lset2 terminal 87 that configure the current adding unit 20 for producing a maximum total current from the microcontrollers 19' and 19" of 200mA.
  • microcontrollers 19' and 19" negotiate for a maximum current of 500mA each, then respective voltages are asserted on the l500bus1 terminal 56 and the l500bus2 terminal 66, which close the gates on the second and fourth FETS 72 and 76. These steps result in a voltage being applied at the Iset1 terminal 84 and at the lset2 terminal 87 that configure the current adding unit 20 for producing a maximum total current from the microcontrollers 19 and 19' of 1000mA.
  • the microcontroller 19' asserts a voltage at the EN1 terminal 82, via the ENbus1 terminal 52 and the data connection 29', to allow the current adding unit 20 to draw current from the microcontroller 19' for the peripheral device 12.
  • a current pathway is established between the in1 terminal 88 and the out1 terminal 92 that permits current to flow from the host device 14 to the peripheral device 12.
  • the microcontroller 19" asserts a voltage at the EN2 terminal 86, via the ENbus1 terminal 62 and the data connection 29", to allow the current adding unit 20 to draw current from the microcontroller 19" for the peripheral device 12.
  • a current pathway is established between the in1 terminal 90 and the out1 terminal 94 that permits current to flow from the host device 14 to the peripheral device 12.
  • a maximum total current whose value depends on the maximum currents negotiated by the microcontrollers 19' and 19" during enumeration, is available to the peripheral device 12. If the maximum amount of current is negotiated by the microcontrollers 19' and 19", under the conditions stated above, then the maximum total current available from the microcontrollers 19' and 19" is 1000mA.
  • the peripheral device 12 negotiates with the host device 14 the maximum current available from the host data port 28 (not shown if Figure 2), which is coupled to the host interface data port 18 (not shown in Figure 2) of the system 10.
  • the host data port 28 can provide a maximum current of 500mA, then the total maximum current available to the peripheral device 12 from the host device 14 is 1500mA. This can be favorably compared to only 500mA if the peripheral device 12 could only draw current from the one host data port 28. It should be understood that 1500mA is the maximum current that can be drawn by the peripheral device in this example. At any particular time, the current drawn by the peripheral device 12 from the host device 14 can be less than this maximum since USB permits the N host power ports 26 and the host data port 28 to supply current on demand up to some maximum current per port, which in this example is 500mA.
  • FIG. 3 a different embodiment of a system 110 for powering a peripheral device 112 with a host device 114 is shown.
  • the system 110 includes N host interface power ports 116, where N is any integer greater than zero, N microcontrollers 119, a current adding unit 120, a control logic unit 121, and a power terminal 124.
  • the host data port 28 of the host device 14 is directly connected to the peripheral device data port 40 with the data cable 38, instead of connected to the peripheral device data port 40 indirectly via the system 10.
  • internal connections similar to 23 and 27 are not required.
  • the host data port 28 can transfer data and power to the peripheral device 12, but, as mentioned above, in some implementations, the transfer of power can be reserved for the N host power ports 26.
  • Each of the N host interface power ports 116 is coupled to a corresponding host port 26 on the host device 14 to deliver power to the peripheral device 12.
  • the N host power ports 26 can be universal serial bus (USB) ports that exchange data with and deliver power to the N host interface power ports 116 in conformity with the USB standard.
  • the N host interface power ports 116 are coupled to the N host power ports via cables 30. Power received by the N host interface power ports 116 from the host device 14 is delivered to the peripheral device 12.
  • the host data port 28 on the host device 14 is connected to a peripheral device data port 40 on the peripheral device 12 via the data cable 38 to allow data to be exchanged there between.
  • the data cable 38 can also carry current from the host device 114 to the peripheral device 112 for powering the peripheral device 112, as mentioned above.
  • the host data port 28 can be similar to the N host power ports 26.
  • the host data port 28 can be a USB port that exchanges data with the peripheral device data port 40 in conformity with the USB standard.
  • Each of the N host interface power ports 116 is coupled to a corresponding microcontroller 119.
  • Each of the N microcontrollers 119 is enumerated by the host device 114 via the respective N host interface power ports 116. The enumeration allows the system 110 to draw current from each of the N host power ports 126 of the host device 114.
  • the N microcontrollers 119 can negotiate the maximum amount of current that can be drawn from the respective N host power ports 26.
  • the current received by the microcontrollers 119 from the host device 114 is delivered to the current adding unit 120 via N power connections 125.
  • the current adding unit 120 adds current received from the host device 114 via the N host interface power ports 116 and the N microcontrollers 119.
  • the system 110 also includes a control logic unit 121 coupled to the N host interface power ports 116, via the N microcontrollers 119 and respective N data connections 129, to configure the current adding unit 120.
  • the control logic unit 121 and the current adding unit 120 are similar to the control logic unit 21 and current adding unit 20, which were described in detail above.
  • the system 110 allows the maximum allowed current from each of the N host power ports 26 to be delivered to the peripheral device 112, in addition to whatever current from the one host data port 128 is available.
  • the peripheral device 112 can thus be charged by the host device 114 at a faster rate.
  • the host device 114 can power peripheral devices 112 requiring currents larger than can be supplied by just the one host data port 128.
EP05102328A 2005-03-23 2005-03-23 System und Verfahren zur Stromversorgung eines Peripheriegerätes Active EP1705549B1 (de)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE602005001197T DE602005001197T2 (de) 2005-03-23 2005-03-23 System und Verfahren zur Stromversorgung eines Peripheriegerätes
AT05102328T ATE363093T1 (de) 2005-03-23 2005-03-23 System und verfahren zur stromversorgung eines peripheriegerätes
EP05102328A EP1705549B1 (de) 2005-03-23 2005-03-23 System und Verfahren zur Stromversorgung eines Peripheriegerätes
CA2540609A CA2540609C (en) 2005-03-23 2006-03-21 System and method for powering a peripheral device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP05102328A EP1705549B1 (de) 2005-03-23 2005-03-23 System und Verfahren zur Stromversorgung eines Peripheriegerätes

Publications (2)

Publication Number Publication Date
EP1705549A1 true EP1705549A1 (de) 2006-09-27
EP1705549B1 EP1705549B1 (de) 2007-05-23

Family

ID=35478299

Family Applications (1)

Application Number Title Priority Date Filing Date
EP05102328A Active EP1705549B1 (de) 2005-03-23 2005-03-23 System und Verfahren zur Stromversorgung eines Peripheriegerätes

Country Status (4)

Country Link
EP (1) EP1705549B1 (de)
AT (1) ATE363093T1 (de)
CA (1) CA2540609C (de)
DE (1) DE602005001197T2 (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1967940A1 (de) 2007-03-09 2008-09-10 Archos Stromversorgungsvorrichtung für tragbares elektronisches Gerät über eine Kombination aus Eingangs- und Ausgangsanschlüssen mindestens eines anderen elektronischen Geräts, sowie entsprechendes System, Verfahren und entsprechende Anwendungen
JP2017521990A (ja) * 2014-07-16 2017-08-03 華為技術有限公司Ｈｕａｗｅｉ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ｃｏ．，Ｌｔｄ． 電子デバイス高速充電方法、装置、及びデバイス

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030075984A1 (en) * 2001-10-23 2003-04-24 Sun Microsystems, Inc. System for distributing power in CPCI computer architecture
US20030154340A1 (en) * 2002-02-13 2003-08-14 Thomas Bolt Use of the universal serial bus as an internal architecture within IDE disk array
EP1487081A2 (de) * 2003-06-11 2004-12-15 Research In Motion Limited Universeller serieller Bus (USB) Ladungssystem für ein mobiles Gerät

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030075984A1 (en) * 2001-10-23 2003-04-24 Sun Microsystems, Inc. System for distributing power in CPCI computer architecture
US20030154340A1 (en) * 2002-02-13 2003-08-14 Thomas Bolt Use of the universal serial bus as an internal architecture within IDE disk array
EP1487081A2 (de) * 2003-06-11 2004-12-15 Research In Motion Limited Universeller serieller Bus (USB) Ladungssystem für ein mobiles Gerät

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1967940A1 (de) 2007-03-09 2008-09-10 Archos Stromversorgungsvorrichtung für tragbares elektronisches Gerät über eine Kombination aus Eingangs- und Ausgangsanschlüssen mindestens eines anderen elektronischen Geräts, sowie entsprechendes System, Verfahren und entsprechende Anwendungen
FR2913508A1 (fr) * 2007-03-09 2008-09-12 Archos Sa Dispositif pour alimenter un appareil electronique portable par combinaison de ports d'entree/sortie d'au moins un autre equipement electronique,systeme,procede et application associes.
US8108694B2 (en) 2007-03-09 2012-01-31 Archos S.A. Apparatus, system and method for supplying a portable electronic device by combining a plurality of I/O ports belonging to at least one other electronic device
JP2017521990A (ja) * 2014-07-16 2017-08-03 華為技術有限公司Ｈｕａｗｅｉ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ｃｏ．，Ｌｔｄ． 電子デバイス高速充電方法、装置、及びデバイス
US10333326B2 (en) 2014-07-16 2019-06-25 Huawei Technologies Co., Ltd. Devices and methods for fast charging using determined maximum charging current values
US11621568B2 (en) 2014-07-16 2023-04-04 Honor Device Co., Ltd. Electronic device fast charging method, apparatus, and device

Also Published As

Publication number Publication date
CA2540609A1 (en) 2006-09-23
EP1705549B1 (de) 2007-05-23
DE602005001197T2 (de) 2008-01-24
DE602005001197D1 (de) 2007-07-05
ATE363093T1 (de) 2007-06-15
CA2540609C (en) 2011-08-09

Similar Documents

Publication Publication Date Title
US20060218415A1 (en) System and method for powering a peripheral device
US8880909B2 (en) Auto-detect polling for correct handshake to USB client
CN103080868B (zh) 充电端口
KR101504104B1 (ko) 역 로컬 데이터 전송 접속을 통하여 전력을 제공하는 시스템 및 방법
US8898485B2 (en) Power transfer between devices
CN104007801A (zh) 用于向电子设备提供功率的方法和装置
EP2866310A1 (de) Datenkabel für schnelles laden
US11256647B2 (en) Docking system utilizing multimode USB-C power transmission and conversion
CN101853970A (zh) 一种通过通用串行总线接口充电的方法和装置
CN105932733A (zh) Otg电源及其供电方法、otg设备和移动通讯设备
WO2005003983A1 (en) Mobile telephone adapter
EP1705549B1 (de) System und Verfahren zur Stromversorgung eines Peripheriegerätes
US7654861B2 (en) Connector and method thereof
WO2011023718A1 (en) Management of a configuration of a usb device
US11880253B2 (en) Smartphone and add-on device power delivery system
KR20160081676A (ko) 트래블 어댑터
US20210232193A1 (en) Multimode usb-c power transmission and conversion
CN104635902A (zh) 通用串行总线的集线装置及其电力管理方法
CN113162161A (zh) 一种基于Type-c接口的充放电电路控制方法、电路以及控制器
CN105098766A (zh) 电力输送控制器
CN2702367Y (zh) 集成供电功能的usb手机数据线
CN209282858U (zh) 一种支持手机快充的usb集线器
KR101799487B1 (ko) 오티지 메모리가 내장된 보조배터리
CN205264968U (zh) Y形充电数据线
TW202127266A (zh) 用於快充的數據線

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20050405

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU MC NL PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL BA HR LV MK YU

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU MC NL PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL BA HR LV MK YU

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CH

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20070523

Ref country code: LI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20070523

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20070523

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

AKX Designation fees paid

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU MC NL PL PT RO SE SI SK TR

AXX Extension fees paid

Extension state: HR

Payment date: 20050405

Extension state: BA

Payment date: 20050405

Extension state: AL

Payment date: 20050405

Extension state: YU

Payment date: 20050405

Extension state: LV

Payment date: 20050405

Extension state: MK

Payment date: 20050405

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

REF Corresponds to:

Ref document number: 602005001197

Country of ref document: DE

Date of ref document: 20070705

Kind code of ref document: P

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20070823

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20070903

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20070923

ET Fr: translation filed
NLV1 Nl: lapsed or annulled due to failure to fulfill the requirements of art. 29p and 29m of the patents act
PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20070523

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20070523

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20070523

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20071023

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20070523

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20070523

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20070523

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20070523

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20070823

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20070523

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20070523

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20080226

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20070523

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20070824

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20070523

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20080331

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20070523

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20080324

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20070523

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20080323

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20071124

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20070523

REG Reference to a national code

Ref country code: DE

Ref legal event code: R082

Ref document number: 602005001197

Country of ref document: DE

Representative=s name: MERH-IP MATIAS ERNY REICHL HOFFMANN, DE

REG Reference to a national code

Ref country code: DE

Ref legal event code: R082

Ref document number: 602005001197

Country of ref document: DE

Representative=s name: MERH-IP MATIAS ERNY REICHL HOFFMANN, DE

Effective date: 20140925

Ref country code: DE

Ref legal event code: R081

Ref document number: 602005001197

Country of ref document: DE

Owner name: BLACKBERRY LIMITED, WATERLOO, CA

Free format text: FORMER OWNER: RESEARCH IN MOTION LTD., WATERLOO, ONTARIO, CA

Effective date: 20140925

Ref country code: DE

Ref legal event code: R082

Ref document number: 602005001197

Country of ref document: DE

Representative=s name: MERH-IP MATIAS ERNY REICHL HOFFMANN PATENTANWA, DE

Effective date: 20140925

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 12

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 13

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 14

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20230327

Year of fee payment: 19

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20240328

Year of fee payment: 20

Ref country code: GB

Payment date: 20240319

Year of fee payment: 20