EP1678746B1 - Method for forming a dielectric on a copper-containing metallisation - Google Patents

Abstract

The invention relates to a method that permits the direct application of a dielectric layer to a metallic layer containing copper. According to said method, two process gases (26, 28) are excited by means of respectively different plasma powers for each substrate surface or one of the process gases (26) is excited by means of a plasma and the other process gas (28) is not excited. The dielectric layer consists e.g. of Si3N4 or AIN and is applied e.g. by remote plasma enhanced chemical vapour deposition (RPE-CVD) or RPE atomic layer CVD (RPE-ALCVD).

Description

• Erzeugen einer Metallisierung auf einem Substrat, wobei die Metallisierung als einen Metallisierungsbestandteil Kupfer enthält, insbesondere aus Kupfer besteht,
• Heranführen mindestens zweier Prozessgase,
• Ausbilden eines Dielektrikum mit mindestens zwei Arten von Bestandteilen, die aus voneinander verschiedenen Prozessgasen stammen.

The invention relates to a method for forming a dielectric on a copper-containing metallization, comprising the steps:

• Producing a metallization on a substrate, wherein the metallization contains as a metallization constituent copper, in particular consists of copper,
• Introducing at least two process gases,
• Forming a dielectric with at least two types of components, which come from mutually different process gases.

• der Leckstrom bzw. der Kriechstrom,
• die Durchbruchspannung,
• die Zuverlässigkeit.

The primary electrical properties of a dielectric include:

• the leakage current or leakage current,
• the breakdown voltage,
• the reliability.

From the European patent application EP 1 130 654 A1 a capacitor arrangement is known in which an additional measure is to apply a metallically conductive barrier layer on a copper metallization before the dielectric is generated. Additional process steps are associated with the application and structuring of the metallically conductive barrier layer. In addition, the barrier layer conducts less well than the metallization, so that the electrical properties of the capacitor are reduced. Incidentally, conductive barrier layers do not always fully fulfill their barrier function.

Out Lucovsky, G. et al., "Formation of thin film dielectrics by remote plasma-enhanced chemical vapor deposition (Remote PECVD), Applied Surface Devices, North Holland, Vol. 39, 1989, pages 33 to 56 ; Tsu, DV and Lucovsky, G., "Silicon nitride and silicon diimides grown by remote plasma enhanced chemical vapor deposition", J. Vac. Sci. Technol., A, Vol. 4, No. 3, May / Jun 1986, pages 480 to 485 ; as well as out Richard, PD, Markunas, RJ, Lucovsky, G. et al., "Remote plasma enhanced CVD deposition of silicon nitride and oxides for gate insulators in (In, Ga) As FET devices", J. Vac. Sci. Technol. A3 (3), May / Jun 1985, pp. 867-872 , Remote Plasma CVD methods are known.

The US 2003/0013320 A1 and US 2003/0024477 A1 refer to batch processes that may also be executed with remote plasma. From the US 2003/0040199 A1 is a light-assisted plasma CVD apparatus known. From the US 2003 / 0011043A1 and the US 5,946,567 For example, methods for producing MIM capacitors are known.

It is an object of the invention to provide a simple method for forming a capacitor dielectric on a copper-containing metallization.

The object related to the method is achieved by the method steps indicated in claim 1. Further developments are specified in the subclaims.

• Ausbilden des Dielektrikums angrenzend an die Metallisierung, wobei die beiden Prozessgase mit voneinander verschiedener Plasmaleistung je Substratfläche angeregt werden oder wobei das eine Prozessgas mit einem Plasma angeregt wird und das andere Prozessgas nicht angeregt wird.

In addition to the method steps mentioned at the outset, the following method steps are carried out in the method according to the invention:

• Forming the dielectric adjacent to the metallization, wherein the two process gases are excited with different plasma power per substrate surface or wherein the one process gas is excited with a plasma and the other process gas is not excited.

By these methods, the early decomposition of the not or only weakly excited process gas is prevented. This decomposition would prevent or significantly interfere with the formation of a high quality dielectric on copper. On the other hand, the strong excitation of the other process gas is also a prerequisite for the formation of a high quality dielectric on copper.

• Verwenden mindestens eines problematischen bzw. kritischen Prozessgases das selbst oder ein Bestandteil dessen mit mindestens einem Metallisierungsbestandteil ohne zusätzliche Maßnahmen bzw. bei Überschreitung einer Grenzplasmaleistung je freiliegender Substratfläche eine Nebenphase bilden würde, welche die elektrischen Eigenschaften eines Dielektrikums erheblich beeinträchtigen würde. Die Grenzplasmaleistung wird bezüglich des problematischen Prozessgases nicht überschritten und bleibt bspw. unter 0,1 W/cm² oder 0,5 W/cm² Substratfläche, wobei auf die von außen angelegte Leistung bezug genommen wird.

In one embodiment, the following steps are performed:

• Use at least one problematic or critical process gas itself or a component thereof with at least one metallization component would form a secondary phase without additional measures or exceeding a limit plasma power per exposed substrate surface, which would significantly affect the electrical properties of a dielectric. The limit plasma power is not exceeded with respect to the problematic process gas and, for example, remains below 0.1 W / cm ² or 0.5 W / cm ² substrate area, referring to the externally applied power.

• Ausbilden des Dielektrikums angrenzend an die Metallisierung, wobei das Dielektrikum mindestens eine Art problematischer Bestandteile enthält, die aus einem problematischen Prozessgas stammen, und wobei das Dielektrikum mindestens eine Art unproblematischer Bestandteile enthält, die aus mindestens einem unproblematischen Prozessgas des Prozessgasgemisches stammen,
• wobei , das Verhältnis des problematischen Prozessgases zu dem unproblematischen Prozessgas so eingestellt wird, dass das Verhältnis der Anzahl der problematischen Verbindungs-Bestandteile im Prozessgasgemisch und der Anzahl der unproblematischen Verbindungs-Bestandteile im Prozessgasgemisch kleiner als 10 Prozent oder kleiner als 0,1 Prozent des Verhältnisses der Anzahl der problematischen Verbindungs-Bestandteile im Dielektrikum und der unproblematischen Verbindungs-Bestandteile im Dielektrikum ist. Ein Verbindungsbestandteil ist bspw. Silizium. Der andere Verbindungsbestandteil ist bspw. Stickstoff.

In one embodiment, the following steps are performed:

• Forming the dielectric adjacent to the metallization, wherein the dielectric contains at least one kind of problematic constituents originating from a problematic process gas, and wherein the dielectric contains at least one kind of unproblematic constituents originating from at least one unproblematic process gas of the process gas mixture,
• wherein, the ratio of the problematic process gas is adjusted to the unproblematic process gas so that the ratio of the number of problematic compound components in the process gas mixture and the number of unproblematic compound components in the process gas mixture less than 10 percent or less than 0.1 percent of the ratio the number of problem compound components in the dielectric and the unproblematic compound components in the dielectric. A compound component is, for example, silicon. The other component of the compound is, for example, nitrogen.

In this embodiment of the method according to the invention, the proportion of problematic constituents in the process gas mixture is in particular substoichiometric in comparison to the proportion of problematic constituents in the dielectric, so that the formation of the interfering minor phase is already reduced on account of the substoichiometry.

The lower limit for the proportion of problematic constituents is determined by the growth rates required. Preferably, said percentages are greater than 0.01 percent or greater than 0.001 percent.

If the dielectric contains several problematic components, the condition mentioned must be for each problematic component be complied with in order to prevent the formation of the secondary phase.

In a further development, the dielectric is produced by means of a deposition process, in which the process gases are introduced separately from one another, starting with the introduction of unproblematic process gas. The development is based on the consideration that the unproblematic process gas forms a thin protective layer on the metallization, which impairs or prevents the formation of interfering secondary phases. The process forms only one atomic layer or only a few atomic layers in each cycle, which is why the process is also referred to as atomic layer deposition (ALD). In further cycles, the protective effect is increased more and more in comparison to the first cycle, so that again different deposition methods are used in one embodiment.

In the case of the further development, the separate introduction of the process gases is therefore particularly important, so that no reaction products flocculate uncontrollably and lead to inhomogeneous atomic layers.

In both alternatives, the metallization is cleaned immediately prior to the generation of the dielectric in a cleaning step, for example by back sputtering or by a wet-chemical cleaning step.

In the invention, the dielectric is applied without an additional barrier layer disposed between the dielectric and the lower electrode. This allows new integration concepts that are considerably simpler than previous concepts and are explained in more detail below with reference to the embodiments, in particular a so-called POWER-LIN concept in which linear capacitors without additional photolithographic step between copper operating voltage lines are arranged in Kupfermetallisierungslagen.

A so-called PAD-LIN-CAP concept is also possible, in which capacitors are formed without an additional photolithographic step between the last copper metallization layer and an overlying aluminum layer, the aluminum layer serving for bonding.

In a further development, the dielectric, i. an electrically nonconductive material formed of a material that is a diffusion barrier for copper and that opposes the electromigration of copper. Additional layers for providing these effects are not deposited, in particular no electrically conductive barrier layers. Silicon nitride is a particularly suitable material because it can be easily manufactured and is compatible with the other common materials for semiconductor circuits. For the production of silicon nitride, a silicon-containing process gas is used, which is problematic due to the silicon content. Thus, without the additional measure, a silicide could increasingly form as a disturbing secondary phase, in particular copper silicide. Suitable silicon-containing process gases are silane, disilane, dichlorosilane, trichlorosilane, bis (tert-butylamino) silane or BTBAS or a gas mixture as at least two of these gases.

In one development, the metallization content of the copper is at least ninety percent by volume of the metallization. A direct deposition of a dielectric on copper is only possible by the inventive method in a simple manner.

In one embodiment, the invention relates to a method for forming a dielectric on a metallization, in which the process gases from which the constituents of the dielectric originate have been selected so that neither these process gases nor their constituents form a secondary phase with the copper of a metallization significantly affect the electrical properties of the dielectric would. The embodiment is based on the consideration that the formation of disturbing secondary phases can also be prevented by a suitable choice of the material of the dielectric and the process gases. Also in the method according to the embodiment, the dielectric is applied without an additional barrier layer arranged between the dielectric and the lower electrode. This also allows the above-mentioned new integration concepts. But also high quality dielectrics for other applications than in capacitors are produced by the method according to the invention.

In a further development of the method, a dielectric made of aluminum nitride is produced. In particular, trimethylaluminum and a nitrogen-containing gas are used as the process gases. Thus, neither in the dielectric nor in the process gas problematic components such as oxygen or silicon are included, which lead to the formation of disturbing secondary phases. In particular, no copper silicide and no copper oxide can form.

In another development with the material selection mentioned, the dielectric is produced with the aid of a deposition method, in which the process gases with constituents for forming the dielectric are introduced separately, preferably cyclically, in particular in at least five or at least ten cycles. This process is referred to as atomic layer deposition and leads to Dielelektrikumschichten with particularly uniform layer thickness, especially in comparison to other deposition processes. For example. Aluminum nitride can be deposited with the atomic layer deposition in a sufficiently uniform layer thickness. The thickness of the dielectric or the dielectric stack is preferably in the range of three nanometers to fifty nanometers.

In a further development, a process gas with a component which is also contained in the dielectric, in comparison to at least one other process gas, in particular compared to a process gas with a component which is also contained in the dielectric, less strongly excited. In particular, the problematic process gas is less stimulated. This ensures that the formation of the secondary phases is prevented particularly effectively not only by the reduced concentration of the problematic constituents but also by their reduced excitation state. On the other hand, the additional excitation of the unproblematic gas means that the problematic constituents primarily react with the excited constituents with the formation of the dielectric.

In an atomic layer deposition process, the activation of the one process gas results in increased interactions with the surface of the metallization, in particular, uniform aggregation of constituents, which then forms the dielectric upon admission of the other process gas.

In addition, both in a CVD deposition (chemical vapor deposition) and in an atomic layer deposition too strong excitation of certain process gases, for example of silicon-containing gases, lead to the early decomposition and thus also to an undesirable deposition, for example of amorphous or polycrystalline silicon in the excitation chamber, for example in an antechamber.

In the invention, the more excited process gas is excited separately from the less or unexcited process gas in a separate chamber from a reaction chamber. Separate excitation chamber methods are also referred to as remote plasma methods. However, in atomic layer deposition, the reaction chamber is also used for excitation because the process gases are in the reaction chamber at different times. For excitation, in particular a plasma is suitable, which, for example, by inductive coupling, is generated by capacitive coupling or otherwise.

In the invention, the dielectric is the dielectric of a capacitor, in particular a capacitor with two metallic electrodes, between which the dielectric is arranged. In a next development, the entire dielectric of the capacitor is produced with a method according to the invention or one of its developments and thus with a small number of different method steps.

In an alternative development, the dielectric is produced as a layer stack. Thus, according to a method of the invention, at least one further dielectric layer is produced adjacent to the dielectric layer, wherein the further layer has a different material composition and / or is produced with a different method and / or process parameters than the dielectric layer. After the formation of secondary phases has initially been prevented, the already applied dielectric acts as a protective layer. Materials with a higher relative dielectric constant than the first applied dielectric can be applied without any problems, for example aluminum oxide, in particular aluminum trioxide Al ₂ O ₃ , aluminum oxynitride, tantalum oxide, in particular tantalum pentoxide Ta ₂ O ₅ , tantalum oxynitride, hafnium oxide, barium strontium titanate or the like. Aluminum oxides are particularly easy to form starting from an aluminum nitride layer. In particular, however, the materials aluminum nitride and silicon nitride are used, both in a base layer of aluminum nitride but also in a base layer of silicon nitride.

In the first deposition step, for example, a deposition condition is selected, which in particular does not generate secondary phases and gives a good barrier layer, e.g. with a thickness of 5 to 10 nm. Subsequently, in a second deposition step, the deposition is optimized for best dielectric properties, for example, to a stoichiometric ratio of the compound components in the dielectric.

Surprisingly, it has been found in a development that the electrical properties of the dielectric of the capacitor continue to improve, even if an upper layer of the dielectric stack is formed with a method according to the invention or one of its further developments.

Figur 1

eine Anlage zum Durchführen eines RPE-CVD Si₃N₄ Verfahrens,

Figur 2

Verfahrensschritte bei der Durchführung eines RPE-ALCVD Si₃N₄ Verfahrens bzw. eines RPE-ALCVD AlN Verfahrens,

Figur 3

eine Kondensatoranordnung, die mit zwei zusätzlichen Maskenschritten erzeugt worden ist,

Figur 4

eine Kondensatoranordnung, die mit einem zusätzlichen Maskenschritten erzeugt worden ist, und

Figur 5

eine Kondensatoranordnung, die keinen zusätzlichen Maskenschritten benötigt.

In the following, embodiments of the invention will be explained with reference to the accompanying drawings. Show:

FIG. 1

a plant for carrying out an RPE-CVD Si ₃ N ₄ process,

FIG. 2

Process steps in carrying out an RPE-ALCVD Si ₃ N ₄ process or an RPE-ALCVD AlN process,

FIG. 3

a capacitor arrangement which has been produced with two additional mask steps,

FIG. 4

a capacitor arrangement which has been produced with an additional mask steps, and

FIG. 5

a capacitor arrangement that does not require additional mask steps.

FIG. 1 leaves showing a process reactor 10 by means of which, inter alia, a RPE-CVD (Remote Plasma Enhanced Chemical Vapor Deposition) Si ₃ N ₄ perform method. However, with the process reactor 10 and the bottom of the hand FIG. 2 explained atomic layer method.

The process reactor 10 contains a process chamber 15, in which a substrate 12 to be coated is arranged on a substrate electrode 11, for example a semiconductor wafer. Above the surface to be coated of the substrate 12 to be coated, an inlet electrode 14 is arranged on the ceiling of the process chamber 15, which has a plurality of small passage openings for the process gases.

A high-frequency voltage is applied between the electrodes 11 and 14 when a plasma is to be generated in the process chamber, for example in the course of the two explained below with reference to the figures two methods.

If, on the other hand, separate decomposition and excitation of process gases are required, the process gases can be supplied separately via supply lines 17. Each supply line 17 is associated with an energy source 16, for example a microwave transmitter, by means of which a plasma 16a can be ignited in the respective supply line. The supply lines 17 open into an antechamber 13, which is connected via the passage openings in the inlet electrode 14 to the process chamber 15.

If only one process gas is to be excited, a supply line 17 and one energy source are sufficient. The leads are, for example, made of ceramic material.

In addition to process gases, inert gases are also excited in the feed lines 17, for example argon or helium, in other embodiments. For supplying non-excitation process gases, a supply 18 is used, the also opens into the pre-chamber 13. Reaction products and unused process gases are extracted by means of a pump 20 from the process chamber 15.

• Mikrowellenleistung einer Energiequelle 16 zwischen 700 und 850 Watt,
• Druck in der Prozesskammer 15 zwischen 5 Pa und 100 Pa,
• Hochfrequenzleistung zwischen 0,02 bis 0,1 W/cm²,
• stickstoffhaltiger Gasfluss 200 bis 400 sccm/min,
• Silanfluss 10 bis 30 sccm/min.

For example. the following operating parameters are used:

• Microwave power of an energy source 16 between 700 and 850 watts,
• Pressure in the process chamber 15 between 5 Pa and 100 Pa,
• High frequency power between 0.02 and 0.1 W / cm ² ,
• nitrogen-containing gas flow 200 to 400 sccm / min,
• Silane flow 10 to 30 sccm / min.

For the deposition of silicon nitride according to the inventive method, for example, nitrogen is introduced through the supply lines 17 and excited with the aid of the remote plasma 16a, see arrows 22. Silane SiH ₄ is introduced through the supply line 18 without excitation, see arrow 24. Excited nitrogen radicals 26 and silane molecules 28 react on the hot surface of the substrate 12 to silicon nitride at temperatures between 200 ° C and 500 ° C. In the process chamber 15 no plasma is ignited in the embodiment. In one embodiment, a low-power plasma is ignited in the process chamber 15 with said high-frequency power, so that the silane is also weakly excited.

The ratio between silane and nitrogen is adjusted as indicated in the introduction to avoid formation of copper silicide.

FIG. 2 shows process steps in the implementation of an RPE-ALCVD (Remote Plasma Enhanced Atomic Layer Chemical Vapor Deposition) Si ₃ N ₄ method or an RPE-ALCVD AlN method. For carrying out the method, for example, the process reactor 10 is used.

First, the RPE-ALCVD Si ₃ N ₄ method will be explained. The method begins in a method step 50 with a Pre-cleaning step, eg a back sputtering step. In a method step 52 following the method step 50, nitrogen gas excited subsequently via the supply lines 17 is subsequently introduced into the process chamber, wherein no further process gas is contained in the process chamber 15, in particular no silicon-containing process gas.
Thereafter, in a following method step 54, the process chamber 15 is purged with an inert gas, for example with argon. The argon is, for example, introduced through a supply line, not shown, in the process chamber. Residues of the nitrogen-containing gas are completely sucked out of the process chamber 15 with the aid of the pump 10.

In a next process step 56, after rinsing, a silane-containing process gas, e.g. Dichlorosilane, introduced via the supply line 18, which in turn no further process gas is contained in the process chamber 15. The dichlorosilane reacts with nitrogen which has attached to the surface of the substrate 12 in step 52 to a single layer of silicon nitride. The silane-containing process gas is not excited. In another embodiment, the silane-containing process gas is weakly excited.

After the method step 56, the material is rinsed again in a method step 58. The procedure is as explained above for method step 54.

If the dichlorosilane is completely sucked out of the reaction chamber 15, it is checked in a method step 60 whether the predetermined number of cycles has been reached. In the exemplary embodiment, 30 cycles are to be run through, resulting in a layer thickness of, for example, three nanometers. If further cycles are to be carried out, process step 52 follows directly after process step 60. The process is now in a loop from process steps 52 to 60, in which nitrogen and dichlorosilane are alternately introduced into the process chamber 15 a plurality of layers of silicon nitride are formed on the substrate 12.

The loop from the method steps 52 to 60 is only left in method step 60 when the predetermined number of cycles has been reached. Once the predetermined number of cycles has been reached, immediately after method step 60, a method step 62 follows in which the method for producing the dielectric is terminated. Optionally, further layers of a dielectric stack are produced from mutually different layers with different methods or with different process parameters.

By the hand of the FIG. 2 As explained method can be deposited a multi-layer silicon nitride layer in good quality at temperatures in the range of 200 to 500 degrees Celsius.

• an Stelle des silanhaltigen Prozessgases wird im Verfahrensschritt 56 ein Aluminiumhaltiges Prozessgas über die Zuleitung 18 eingeleitet, z.B. Trimethylaluminium.

The following is an explanation of the RPE-ALCVD AlN process, except for the following differences as the RPE-ALCVD Si ₃ N ₄ process:

• Instead of the silane-containing process gas, in process step 56, an aluminum-containing process gas is introduced via the feed line 18, for example trimethylaluminum.

It is possible to produce a multi-layer aluminum nitride layer of good quality, i. with low defect density and high barrier effect.

In other embodiments, at least one further dielectric layer of a dielectric stack is subsequently produced, but a conventional method is used. Very good results were achieved with a layer stack comprising, in the order given, an RPE-CVD Si ₃ N ₄ layer, an ALD layer (atomic layer deposition) of Al ₂ O ₃ and an RPE-CVD Si ₃ N ₄ layer contains.

FIG. 3 shows a capacitor arrangement 100 which has been produced with two additional mask steps. The capacitor assembly 100 includes a bottom electrode 102 made of copper or a copper alloy with an alloy content of other than copper of less than five percent. The bottom electrode 102 is contained in a planar metallization layer 104. The metallization layer 104 is terminated by a diffusion barrier layer 106 which has been deposited by a conventional method. Although in FIG. 3 not shown, the bottom electrode 102 is surrounded on all sides by a barrier layer.

• eine elektrisch isolierende Dielektrikumschicht 110 aus Siliziumnitrid Si₃N₄ oder aus Aluminiumnitrid AlN, bzw. aus einem Schichtstapel,
• eine elektrisch leitfähige Deckelektrode 112, bspw. aus Titannitrit TiN, Tantalnitrid TaN o.ä.,
• eine Siliziumnitridschicht Si₃N₄.

The capacitor assembly also includes in a substrate-remote metallization layer 108 as the distance from the substrate increases:

• an electrically insulating dielectric layer 110 of silicon nitride Si ₃ N ₄ or of aluminum nitride AlN, or of a layer stack,
• an electrically conductive cover electrode 112, for example of titanium nitride TiN, tantalum nitride TaN or the like,
• a silicon nitride layer Si ₃ N ₄ .

The metallization layer 108 is terminated by an electrically insulating barrier layer 120. A metallization layer 122 disposed over the metallization layer 108 includes a conductive trace 124, e.g. a copper conductor. From the interconnect 124, a via 126 leads to the cover electrode 112. The metallization layers 104, 108, and 122 each contain an intraluminal dielectric 130, 132, and 134, respectively, for electrical isolation of interconnects within a metallization layer 104, 108, and 122. For example. For example, silicon dioxide or a low-k dielectric is used as the material for the intraluminal dielectric 130, 132, and 134, respectively.

Until the application of the barrier layer 106, the procedure is as usual. Subsequently, however, a first sub-layer of the intralagum dielectric 132 is applied, eg in FIG a layer thickness that is less than one third of the final thickness of the intraluminal dielectric 132. In a first additional photolithographic step, the position of a recess 140 is determined, in which the capacitor 100 is to be generated. The recess 140 is etched after exposure and development of a resist, for example with an RIE (Reactive Ion Etching) method. The recess 140, after etching, penetrates the first sublayer of the intraluminal dielectric 132 and the barrier layer 106 so that the bottom of the recess 140 lies on the bottom electrode 102. The bottom electrode 102 projects on all sides beyond the bottom of the recess 140.

Subsequently, the dielectric layer 110 with one of the hand on the Figures 1 and 2 explained method deposited over the entire surface. Optionally, further sub-layers of the dielectric layer 110 are then produced from other materials or by other methods.

Thereafter, the cover electrode layer 112 is deposited over the entire surface. Optionally, the entire surface deposition of the silicon nitride layer 114 follows. The deposition of the layers 110 to 114 is compliant.

Thereafter, a second additional photolithographic step for determining the position of the edge of the cover electrode 112 is performed. After exposing and developing a resist, etching is stopped while stopping on the lower sublayer of the intra-valley dielectric 132. In the exemplary embodiment, the edge of the cover electrode 112 lies completely outside the recess 140 and has an outline that corresponds to the outline of the bottom electrode 102.

Subsequently, the still missing partial layer of the intraluminal dielectric 132 is deposited. After an optional planarization step is then according to known method steps further processed, among other things, the Via 126 is generated.

FIG. 4 shows a capacitor assembly 200, which has been produced with only one additional mask step, in a cross section. A substrate having a multiplicity of semiconductor components, eg of transistors, lies below the illustrated arrangement. A lower, preferably planar, metallization layer 201 contains conductor tracks for lateral current transport between nonconductive diffusion barriers 202, eg a conductor track 203. Via conductor 204 for vertical current transport, conductor track 203 is connected to a lower electrode 206 of capacitor arrangement 200 arranged in a second metallization layer 205. In the exemplary embodiment, in the metallization level 205 to the left of the electrode 206, there is a conductive track 208. The lower electrode 206 and the conductive track 208 are embedded in an intermediate dielectric 209 in order to isolate them from one another, for example in silicon dioxide. In contrast, an intermediate dielectric 210 insulates the interconnects 203 of the lower metallization layer 203 from one another.

On the lower electrode 206, a capacitor dielectric 211 is arranged, for example a single-layer or a multi-layered dielectric. On the capacitor dielectric 211, an upper electrode 212 is disposed. The capacitor dielectric 211 has, in the region of the upper electrode 212, a thickness which is greater than the thickness of a barrier layer 207 which is arranged in the same plane as the capacitor dielectric 211.

Top electrode 212 and interconnect 208 are electrically conductively connected via vias 213 to interconnects 214 in a third metallization layer 215 that includes an intermediate dielectric 216. Above the metallization layer 215 are a non-conductive diffusion barrier 217 and further passivation layers 218a and 218b.

The conductive lines 203, 208, and 214, the lower electrode 206 and the vias 204, 213 are made of a copper alloy or of pure copper, for example by means of a dual damascene method. Here, for example, conductive barrier layers 219, 220 or 221 made of titanium nitride are introduced into the trenches or holes to be filled with copper.

The diffusion barriers 202, 207, 217, the capacitor dielectric 211 and the passivation layer 218b consist in the exemplary embodiment of silicon nitride Si ₃ N ₄ . The passivation layer 218a consists in the exemplary embodiment of silicon dioxide.

Deviations from the known dual damascene method result in the production of the capacitor 200. After the planarization of the metallization layer 205, for example with a chemical mechanical polishing method, silicon nitride is deposited over the whole area for the capacitor dielectric 211 and for the diffusion barrier 207. In this case, a method is used, as described above with reference to the Figures 1 and 2 has been explained. In an alternative embodiment, instead of the silicon nitride, aluminum nitride is used as the material for the barrier layer 207 and the capacitor dielectric 211, and as described above with reference to FIGS FIG. 2 explained method applied.

After the deposition of the material for the barrier layer 207 or for the capacitor dielectric 211, a metallic layer is deposited over the whole area to form the electrode 212, for example a titanium nitride layer. Alternatively, the electrode 212 is formed as a layer stack. Subsequently, an additional photolithographic step is performed to define the edge of the electrode 212. After exposing and developing a resist, it is etched, stopping on the barrier layer 207 with light overetching. The further processing takes place again according to the known dual Damascus method.

In an alternative embodiment, a silicon nitride layer is applied to the electrode, which i.a. during the etching of the vias 213 serves as an etch stop. Instead of multiple vias for connecting one electrode 206 or 212, in another embodiment, only one via is used. The lower electrode 206 can also be connected with a plurality of vias or "from above", i. from a side facing away from the semiconductor substrate.

FIG. 5 shows capacitor arrays that do not require an additional masking step. An integrated circuit 310 includes a plurality of semiconductor integrated devices in a silicon substrate 312, but which are incorporated in FIG FIG. 5 are not shown. The components arranged in the silicon substrate 312 form two spatially separated regions, namely an analog part 314 and a digital part 316. In the analog part 314, mainly analog signals are processed, ie signals which have a continuous value range. In digital part 316, on the other hand, mainly digital signals are processed, ie signals having, for example, only two values associated with two switching states.

The circuit arrangement 310 also contains at least four metallization layers above the silicon substrate 312, in the exemplary embodiment nine metal layers 320 to 334, between which no further metal layers but insulating layers are arranged. The metal layers 320 to 334 are each arranged in a plane. The planes of the metal layers 320 to 334 are arranged parallel to each other and also parallel to the main surface of the silicon substrate 312. The metal layers 320 to 334 each extend both in the analog part 314 and in the digital part 316.

The bottom four metal layers 320, 322, 324 and 326 include in the analog part 314 in the order named connecting sections 340, 342, 344 and 346, respectively, which connections form between the components of the analog part 314. In FIG. 5 are a variety of interconnects indicated as blocks. Of course, there are also interconnects between these blocks for the connection of analog part 314 and digital part 316. In the digital part 316, the metal layers 320, 322, 324 and 326 in this order contain connection sections 350, 352, 354 and 356, respectively, which provide local connections between them Form components of the digital part 316. The connecting sections 340 to 356 have a thickness D of, for example, 100 nm perpendicular to the substrate 312.

The metal layer 328 contains in the analog part 314 connecting sections 360 which carry analog signals and connect the components of the analog part 314. In the digital part 316, the metal layer 328 includes connecting portions 362 which connect the components of the digital part 316 and thus carry digital signals. Likewise, the metal layer 330 in the analog part 314 contains analog signal connection sections 364 and in the digital section 316 digital signal connection sections 366.

The metal layer 331 contains in the analog part 314 a connecting portion 367, which covers the analog part 314 over the entire surface and serves to shield the analog part 314 from overlying components. In the digital part 316, however, the metal layer 331 contains connecting sections 368, which, for example, carry an operating voltage or ground potential. The connecting portions 360 to 368 are twice the thickness D.

The metal layers 332 and 334 form the two uppermost metal layers. In the analog part 314, the metal layer 332 includes a bottom electrode 370 of a capacitor 372 having a linear transfer function and a capacitance C1. The capacitor C1 is used to process analog signals, for example in an analog / digital converter. A cover electrode 374 of the capacitor 372 lies in the metal layer 334 above the electrode 370. The cover electrode 374 is connected to a connection section 375 in the metal layer 332.

In the digital part 316, the metal layer 332 includes a connecting portion 382 which carries an operating potential P1 of, for example, 2.5 volts. Above the connecting portion 382 is a connecting portion 386, which leads a ground potential P0 of 0 volts. Between the connecting sections 382 and 386, a capacitance C3 is formed, which belongs to a blocking capacitor. The connecting portion 386 is connected to a connecting portion 368 in the metal sheet 331 via a connecting portion 387 in the metal sheet 332 and vias.

At least the metal layer 332 contains copper-containing electrically conductive material, so that in particular the bottom electrode 370 of the capacitor 372 and the connecting section 382 are copper-containing. Optionally, other metal layers 320 to 334 are copper-containing.

The size of the capacitances C1 and C3 is determined on the one hand by the size of the overlapping electrodes 370 and 374 and the overlapping connecting portions 370 to 386, respectively. On the other hand, the area-related capacitance between the connection portions 370 and 374 and 382 and 386 is determined by the formation of an intermediate layer 390 which lies between the metal layers 332 and 334. The intermediate layer 390 is designed such that a surface-related capacity of, for example, greater than 0.5 fF / μm ² results.

The connecting portions 370 to 386 have four times the thickness D, and are thus particularly suitable for conducting high currents, such as occur in connection sections 382 and 386 for supplying the operating voltage.

The capacitance C3 is formed from electrically conductive sections of two metallization layers 332 and 334 which, for example, do not carry signals but are used exclusively for carrying the operating voltage. In so far signals are guided, the signal line are designed with the same course in both metallization.

At the in FIG. 5 In the case shown, in the case of the so-called "PAD-LIN-CAP" concept, these are the upper copper metallization layer and thereon an aluminum metallization layer which contains at least 90% by volume of aluminum. The aluminum metallization layer is also used for bonding, see a bond pad 392 in the metal layer 334 and a bond opening 394 in a passivation 396. The bond pad 392 is connected to a connection section 391 in the metal layer 334.

Dielectric 390 between the two metallization layers 332 and 334 is a dielectric or dielectric stack fabricated according to one of the methods discussed above. The mixed signal part 314 of the chip results in linear capacitors C1 whose capacitance is determined by the size of the copper plate 370. At line crossovers in the digital part 316 also arise capacitors C3, but they are not parasitic and do not disturb, because they contribute to the stabilization of the supply voltage. Since less metallization layers are generally required in the mixed-signal part 314 of the circuit 310 of the chip than in the digital part 316, this concept works without additional mask steps.

It is also possible to use the above-described dielectric 390 or the above-described dielectric stack for the so-called "POWER-LIN-CAP" concept. In this case, the dielectric 390 or the dielectric stack is located between the two last copper metallization layers. The aluminum metallization layer is then no longer needed. The bonding then takes place directly on copper.

In summary, in particular, high frequency circuits in BIPOLAR, BICMOS (BIpolar Complementary Metal Oxide Semiconductor) and CMOS technology (Complementary Metal Oxide Semiconductor) require capacitors with high surface capacitance, eg higher than 0.7 fF / μm ² , and with low parasitic capacitances. The previously used conventional MOS or MIS capacitors show as disadvantageous properties a strong voltage dependence due to voltage-induced space charge zones and high parasitic capacitances due to the small distance to the substrate. These problems can be circumvented by the use of MIM capacitors (metal insulator metal), which should be integrated as possible into the metallization without changing and influencing the adjacent metal tracks, in particular in a multi-layer metallization. Also, for the insertion of the MIM capacitors as few additional process steps are required, in particular additional photolithographic steps.

In order to obtain a defect-free capacitor with a long service life, the choice of suitable dielectric interfaces is of crucial importance. In particular, in the case of copper metallizations, the application of conventional dielectrics without additional measures leads to unacceptable defect densities or to reduced reliability. For these defect densities mainly impurities of the dielectric by copper diffusion or secondary phases as well as copper hillocks are responsible, which lead to singularities in the field distribution or to field peaks. These impurities and copper hillocks are reduced or prevented by the illustrated methods of applying the dielectric.

Claims (10)

1. A process for forming a dielectric (110) on a metallization (102),
   comprising the steps of:

   producing a metallization (102) on a substrate, the metallization (102) containing copper as a metallization constituent,

   supplying at least two process gases (26, 28),

   forming the dielectric (110) adjacent to the metallization (102),

   the dielectric (110) containing at least two types of constituents which originate from different process gases (26, 28),

   the dielectric (110) is the dielectric (110) of a capacitor (100),

   the capacitance per unit area of the capacitor is higher than 0.7 fF/µm²,

   characterized in that the two process gases (26, 28) being excited with different plasma powers per unit substrate area, or in that one process gas (26) being excited with a plasma and the other process gas (28) not being excited,

   whereby the more strongly excited process gas (26) is excited separately from the less strongly excited or unexcited process gas (28) in a chamber (13) that is separate from a reaction chamber (15).
2. The process as claimed in one of the preceding claims, characterized in that the process gases are supplied as a process gas mixture,
   or in that the dielectric (110) is produced with the aid of a deposition process in which the process gases (26, 28) are supplied to the metallization (102) separately from one another, preferably cyclically, in particular in at least 10 cycles.
3. The method as claimed in one of the preceding claims, characterized by at least one of the following steps:

   forming the dielectric (110) from a material which is a diffusion barrier to copper,

   forming the dielectric (110) from a material which counteracts the electromigration of copper,

   forming the dielectric (110) from silicon nitride, in particular from Si₃N₄, or from a material which contains silicon nitride,

   supplying a silicon-containing process gas (28), in particular silane, disilane, dichlorosilane, trichlorosilane, bis(tertbutylamino)silane or a gas mixture comprising at least two of these gases,

   supplying a nitrogen-containing gas (26), in particular nitrogen, ammonia gas or a mixture of these gases.
4. The process as claimed in one of claims 1 or 2, characterized by at least one of the following steps:

   forming the dielectric (110) from a material which is a diffusion barrier to copper,

   forming the dielectric (110) from a material which counteracts the electromigration of copper,

   forming the dielectric (110) from aluminum nitride or from a material which contains aluminum nitride,

   supplying an aluminum-containing process gas, in particular trimethyl aluminum,

   supplying a nitrogen-containing gas, in particular nitrogen, ammonia gas or a mixture of these gases.
5. The process as claimed in one of the preceding claims, characterized in that the metallization fraction amounts to at least five percent by volume or at least forty percent by volume or at least ninety percent by volume of the metallization.
6. The process as claimed in one of the preceding claims, characterized in that the dielectric (110) is the dielectric (110) of a capacitor (100) with two metallic electrodes (102, 112), between which the dielectric (110) is arranged.
7. The process as claimed in claim 6, characterized in that the entire dielectric (110) of the capacitor (100) is produced by the process as claimed in one of claims 1 to 5.
8. The process as claimed in one of claims 1 to 6, characterized by the steps of:

   forming a dielectric layer (110) by the process as claimed in one of claims 1 to 6,

   then forming at least one further dielectric layer adjacent to the dielectric layer, the further layer having a different material composition and/or being produced by a different process and/or using different process parameters than the dielectric layer (110),

   preferably forming the further layer by oxidation, in particular anodic oxidation.
9. The process as claimed in claim 8, characterized by the step of:

   forming a dielectric layer by the process as claimed in one of claims 1 to 10 after the further layer has been formed, in particular adjacent to the further layer.
10. The process as claimed in claim 8 or 9, characterized in that the further layer has a relative dielectric constant of greater than seven and in particular contains an oxide, preferably contains aluminum oxide, tantalum oxide or hafnium oxide.

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