EP1665029A2

EP1665029A2 - Digital signal processing device

Info

Publication number: EP1665029A2
Application number: EP04761027A
Authority: EP
Inventors: Alois Hahn; Premysl Vaclavik; Heinz Gerald Krottendorfer; Christian Tiringer
Original assignee: On Demand Microelectronics GmbH
Current assignee: ON DEMAND MICROELECTRONICS AG
Priority date: 2003-09-08
Filing date: 2004-09-07
Publication date: 2006-06-07
Also published as: ATA14062003A; AT413895B; WO2005024542A3; WO2005024542A2; CA2537549A1; US20070033152A1

Abstract

The invention relates to a digital signal processing device comprising: input storage means (3; 5); a computational device (4) that is connected to said means, defines a data path (9) and contains at least one arithmetic unit (6) in addition to a control input (2a) for specifying calculation operations; and output storage means (8). The data path (9) between the arithmetic unit (6; 7) and the output storage means (8) is equipped with a number-format conversion unit (10) comprising a shift unit (17). A number-format specification unit (11) and a control unit (17'), which is connected to the latter and calculates required shift operations on the basis of the number-format specification, are assigned to the number-format conversion unit (10). Formatting operations are calculated automatically using input and output format information and corresponding commands are applied to the shift unit (17).

Description

Digital signal processing device

The invention relates to a digital signal processing device, in particular a digital computing device, according to the introductory part of claim 1.

In digital signal processing, digital signals are treated digitally using a wide variety of algorithms, the digital signals being derived, for example, from originally analog signals by sampling. The signal processing can take place in the form of calculations in accordance with telecommunications algorithms, for example in order to implement a bandpass filter or the like. For such digital signal processing, the digital signal values are stored in binary form in the storage means, the values usually being stored in a 2's complement representation as an integer or else as a fixed-point number. In certain applications, the more complex floating point format (floating point format) can also be used.

To carry out digital signal processing, digital signal processors (DSP) are mostly used; in applications with very high throughput rates, such as in the course of image compression or in DSL (digital subscriber line) technology, specially tailored computing units are used which have significantly higher computing speeds allow.

In the course of signal processing, a format conversion is often required, ie the number display must be changed with a view to the desired accuracy. It is typical here that the number of bits used, i.e. the bit width of the data words, is increased for greater accuracy, whereby a reduction is again required subsequently, and moreover, the position of the decimal point must also be adapted in the case of these format changes. These format conversions and decimal point adjustments naturally result in numerical errors, which subsequently affect the accuracy of the result and thus the quality of the output signal; the reduction in the quality of the output signal can in signaling applications, for example, as signal noise, and it can, for example in the case of the implementation of integrating filters, cause a total failure of these filters.

The exact format conversion and possibly also a rounding in terms of signal technology are accordingly very critical aspects in the course of such digital signal processing, these manipulations also frequently occurring in the usual practical applications in addition to the actual mathematical calculations, such as multiplication or addition. Such a format conversion accordingly also has a significant impact on the processing speeds that can be achieved, i.e. on the clock frequency that can be achieved in each case, which subsequently also determines the technical and economic feasibility.

In the signal processors currently used or known, format adjustments and roundings are carried out programmatically with the aid of a series of individual commands, several clock cycles being required for the execution of these commands; in some cases, the number of clock cycles required for this can then be greater than the number of clock cycles for the actual algorithmic signal processing or calculation, which is of course particularly disadvantageous.

Processor devices are known from US Pat. No. 4,041,461 A, US Pat. No. 4,876,660 and US Pat. No. 5,844,827, in which reformatting is also carried out in the course of signal processing operations. However, in the known techniques, the information for reformatting is predetermined in advance on the basis of appropriate programming via a control processor and stored in a register, i.e. the respective shifting operations are to be specified individually by programming, a transition to other number formats requiring corresponding new programming inputs. These known techniques are therefore rigid and unwieldy with regard to format changes.

It is an object of the invention to provide a particularly efficient To enable processing of digital signals using flexible number format conversions and, if necessary, rounding operations, in particular an arbitrarily predeterminable format conversion within a single clock cycle should be made possible, and also in the same step as the actual mathematical operations.

To achieve this object, the invention provides a digital signal processing device with the features of claim 1. Particularly advantageous embodiments and further developments are defined in the subclaims.

According to the invention, a special format conversion unit, preferably with a rounding unit, is thus integrated directly into the data path of the arithmetic unit in accordance with a particularly preferred aspect. The possible format conversions and possibly rounding operations thus become a direct component of each signal processing command, so that no separate clock cycle is generally required. Another advantage is that program creation is significantly simplified since the problems associated with format conversion are automatically relieved from the programmer. The number format conversion unit, possibly with the integrated rounding unit, does not need to be designed for a predetermined format, but rather a format specification or setting is particularly advantageously possible, for which purpose a format register is preferably provided as the format specification unit. This format register is loaded once as required and then determines the format conversions and roundings and therefore the exact functioning of these units based on its content. In particular, the format tab contains fields for specifying the data format, such as the number of digits in total and the number of digits after the decimal point, for the starting format as well as for the target format.

Furthermore, a saturation function (also called a clipping function) can be integrated into the number format conversion unit in order to prevent a signal value from overflowing when the maximum value is exceeded in the wrong sign. By integrating such a saturation function, ie Installation of a saturation unit in the format conversion unit also ensures that no additional clock cycle is required, and, as mentioned, errors which could arise in connection with the format conversion and rounding function are prevented by this saturation function. A comparable saturation function is preferably also assigned to the rounding unit, in order to identify any overflow when rounding up and to deliver the correct result.

The invention is explained in more detail below on the basis of preferred exemplary embodiments, to which, however, it should not be restricted. The drawing shows in detail:

1 shows a block diagram of a signal processor known per se;

2 shows a schematic block diagram of an arithmetic unit of such a processor, with a number format conversion unit according to the invention, to which a format specification unit is assigned;

3 shows such an arithmetic unit with a number format conversion unit in more detail;

4 schematically shows a format of a format register as a format specification unit;

5 shows, in two related sub-figures 5A and 5B, a detailed structure of the number format conversion unit including rounding unit and saturation unit;

6 shows an example of a table with signed positive and negative 4-bit binary numbers, with a value range from -8 to +7;

7 shows a comparable table with 4-bit binary numbers, each having two digits before the decimal point and two digits after the decimal point, the values extending from -2 to +1.75; FIG. 8 schematically, in association with the arrangement of FIG. 5, an example of a number format conversion with rounding and saturation, with an overflow; and

Fig. 9 shows a comparable example for a number format conversion with rounding and saturation, but now with an underflow (underflow).

1 schematically shows in a block diagram the known structure of a processor, a program memory 1 being provided to which a program controller 2 is connected in order to correspondingly control an arithmetic logic unit 4 receiving the data to be processed from a data memory 3. The Harvard architecture, as shown, or also the Von Neumann architecture are known for the construction of such arithmetic units 4, wherein a computer unit 4 with Harvard architecture is also assumed here, although this is of course not to be seen as restrictive. The arithmetic unit 4 contains, as will be explained in more detail below with reference to FIG. 3, in general, an arithmetic unit (ARU - arithmetic unit), and it defines a data path.

In such a digital signal processor, each program instruction is carried out in three phases, the sequence being controlled with the aid of the program controller 2. In the first phase, the so-called "fetch" phase (fetch - command call), a command word is read out of the program memory and fed to the program controller 2, as illustrated in FIG. 1 with the reference symbol la. In the following one In the “decode” phase, this command word is decoded and split into individual microoperations with which the arithmetic and logic unit 4 is controlled. This is indicated in Fig. 1 with the connection 2a between the program controller 2 and the arithmetic unit 4. In the third phase, the "Execute" phase, the instruction is processed, and accordingly in this phase the micro-operations are passed on in the form of control signals via the connection 2a and the arithmetic unit 4 for actual execution, in addition via the data connection 3a data from the data memory 3 into the computation plant 4 can be loaded; In arithmetic unit 4, this data is processed arithmetically and temporarily stored in registers. After this processing, the data obtained are stored again in the data memory 3, for example via a connection 4a. In this respect, the data store 3 forms, for example, input storage means and at the same time output storage means for the arithmetic unit 4.

2 shows the structure of an arithmetic unit 4 in somewhat more detail in a block diagram, with data A, B to be linked to one another being fed, for example, to input registers 5A, 5B (for example from data memory 3 according to FIG. 1), which are used as input Storage means 5 can be viewed, after which the data arrive in the arithmetic unit when the aforementioned microoperations are processed, here, for example, a multiplier unit 6 being provided in series with an adder unit 7. The result of these arithmetic operations is normally fed to output storage means, here illustrated schematically by a result register 8, the result being indicated by "Y". The individual components 5A, 5B to 8 define a data path 9 and in this data path A number format conversion unit 10 is also arranged directly, which at the same time contains a rounding unit, as will be explained in more detail below. This number format conversion unit 10, hereinafter referred to as conversion unit or also adaptation unit, can convert the supplied data into a predetermined number format, wherein, as shown in FIG. 2, a format specification unit 11 is provided, which is in particular in the form of a format register, and the output of which is connected to the conversion unit 10, as indicated in FIG. 2 by the connection 11a. This format specification unit 11 can be used for the respective calculation process or D Data processing process can be filled with appropriate format information, as indicated schematically in FIG. 2 at the input 11b.

The arrangement of the conversion unit 10 directly in the data path 9 leading from the input registers 5A, 5B to the results register 8 in the manner shown means that the desired format conversions and possibly rounding operations in the can take place in the same clock cycle in which the arithmetic operations are carried out, with only a certain delay being accepted until the data appear at the output of the conversion unit 10. This means an acceleration in time compared to a technology in which the format conversions and rounding operations are carried out via the program, so that they only take place in subsequent clock cycles, after the actual calculation processes, in the program's own conversion and rounding steps. The present hardware implementation of these conversion and rounding tasks directly in the data path 9 also enables a simplification of the programming, since in the respective program that is to be stored in the program memory 1 in FIG. 1, the desired formats for storage in the format are simple - Specification unit 11 are to be provided (provided that these formats do not automatically result from the storage format of the data store 3), but no conversion and rounding operations have to be programmed. If the above-mentioned delay time, which is to be taken into account in the present technology, should be rather long compared to the clock time, for example should already take half a clock cycle, which could be the case with particularly fast arithmetic units 4 with particularly short clock cycles , it can be envisaged to install a storage element (register) for buffering within the conversion unit 10, so that the format conversion and rounding activity started in the given clock cycle can then be completed in a second clock cycle without the given delay times The result of the operations in the arithmetic unit, which is stored as the result Y in register 8, could impair.

3 shows further details for the construction of such a typical arithmetic unit 4 for DSP applications (DSP digital signal processor). An important task in digital signal processing is, for example, the so-called multiply-accumulate function (MAC function; MAC - multiply-accumulate). With this function, two input numbers (operands) are multiplied, and the multiplication result is then added to the content of an accumulator. Such a MAC function is, for example, with the arithmetic unit 4 3 realized, in addition, the result obtained is subjected to a range adjustment (number format conversion and rounding). For such functions, the signed 2's complement representation is often used for the numbers, as will be explained in more detail below with reference to FIGS. 6 and 7, but the invention is of course not restricted to such representations. In the following description, however, for the sake of simplicity, such a signed 2's complement representation will be used throughout.

According to FIG. 3, the desired numbers A, B for the multiplication to be carried out are read out from the data memory 3 and loaded into the registers 5A, 5B, which is accomplished by the program control (program control 2 in FIG. 1) by means of corresponding load commands In a comparable manner, the data memory 3 also receives "CONTROL" control commands from the program memory 2 via a control line 3b. The data or operands A, B are then fed to the arithmetic unit 6 in the next step, with a corresponding control signal (MUL / DIV - multiply / divide) being applied to it by the program controller 2 at 6b. The multiplication result is fed via the connection 6a to the adder / subtractor 7, to which the program controller 2 in a corresponding manner supplies an add command (or subtract command; ADD / SUB). The current content of this accumulator 12 is fed from the output of an accumulator 12 to a second input of this adder / subtractor 7, as indicated at 12a in FIG. 3. The result of this addition is again stored in the accumulator 12, cf. the output 7a of the adder 7, a multiplexer 13 being interposed, which is set by the program controller 2 via a control input 13b (“SELECT”) such that the multiplexer 13 connects the adder output 7a to the corresponding input of the accumulator 12 (see FIG Connects 13a between multiplexer 13 and accumulator 12. The function of the accumulator 12 is initiated by the program controller 2 with a control input 12b (“OPERATION”). The multiply-accumulate command is usually repeated several times in a loop; as soon as the end result is present in the accumulator 12, in the present example it is stored again in the data memory 3, although the number format has to be adapted beforehand, since the width of the accumulator 12 is generally greater than the width of the data values A read from the data memory 3 , B. In the present example, the multiplexer 13 is used to load the accumulator 12 with an initial value from the data memory 3 with its own instruction at the start of a loop. Usually the value "00" is used as this initial value.

The content of the accumulator 12 (output 12a) is thus, as mentioned, transferred to the conversion unit 10 before being stored back in the data memory 3 for the purpose of number format conversion and preferably also for any rounding, in which the adaptation of the to be described in more detail below with reference to FIG. 5 Number format and rounding are performed. The result of this is that the calculation result corresponds to the predetermined storage format, although a larger word width (number width, ie a larger number of bits per number) can be used for the calculation processes carried out in the arithmetic logic unit 4, for a high accuracy of the calculation. The corresponding control information is received by the conversion unit 10 from the format specification unit 11, preferably a register, which contains control data relating to the respectively defined format (FXD_FORMAT); this control information is loaded in advance, at the beginning of the program, during an initialization phase, in accordance with the storage format specifications, for example of the data memory 3. For example, at the beginning of the program, a value is read directly from the data memory 3, see output 3a in FIG. 3, and loaded into the specification unit 11 with the aid of a control signal 11b (“LOAD”). This word thus indicates the target format (DST Destination which the result Y should have (cf. FIG. 2), a corresponding area DST being contained in the format specification unit or in register 11, apart from a memory area SRC (SRC - Source - Source) for corresponding format information on the format used during the calculation in arithmetic unit 4. The corresponding format information can be found in Register 11 each be 8 bits long (cf. bit positions 0-7, a total of 0-15, in the specification unit 11 according to FIG. 4).

The format SRC in the specification unit 11 thus relates to the format of the number given at the output of the accumulator 12, the "source number", whereas the format DST specifies the target format of the data words for storage in the data memory 3. Each field DST or SRC im Register 11 contains the position of the decimal point in the form of an unsigned binary number, a value of "2" indicating, for example, that the number to be considered should have two decimal places, ie two digits to the right of the decimal point, so that the decimal point is shifted two digits from the rightmost digit to the left.

The conversion unit 10 supplies the result (Y; see also FIG. 2) at its actual output 10a according to FIG. 3, which result is stored directly in the data memory 3 in output storage means according to FIG. 3; in addition, the format conversion and rounding can also result in an overflow or underflow in the number adjustment (underflow - UFL; overflow - OFL), and corresponding status signals UFL and OFL are present at outputs 10b and 10c of the conversion unit 10; these two status signals UFL, OFL can preferably be fed to a status register 14 in order to be available for handling exceptional cases.

The mode of operation of the conversion unit 10 (format conversion, rounding) will now be explained in more detail with reference to FIG. 5, reference also to FIGS. 6-9 below. FIG. 5 is composed of FIGS. 5A and 5B, which are to be thought of as being laid along the dashed dividing lines in FIGS. 5A and 5B. 5 also contains exemplary dimension details relating to the number of bits or the bit width of the individual data values to be processed, these dimension details entirely corresponding to common practical examples. Further explanations are given below on the basis of concrete, but simplified numerical examples with lower bit numbers, with particular reference to FIGS. 8 and 9, for easier understanding, with previous explanations also 6 and 7 2's complement number representations are to be explained with regard to “overflow” and “underflow”.

As already mentioned, the conversion unit 10, also called the ALIGN and ROUND unit (with regard to format adaptation and rounding), is supplied with the output value 12a of the accumulator 12, as can be seen in FIG. 3 as well as in FIG. 5. The format of this output value at the output 12a of the accumulator 12 is subsequently to be adapted by the conversion unit 10 in accordance with the specification by the register 11 (generally called format specification unit 11) in such a way that the finally obtained data word (output 10a) for storage in the data memory 3 (or any other data storage, possibly with a different number format) is suitable. The conversion unit 10 is arranged directly in the data path (see data path 9 in FIG. 2) of the arithmetic unit 4, i.e. In the normal case, the operations carried out by the conversion unit 10 are preferably carried out in the same clock cycle as the arithmetic operations in the preceding arithmetic units 6, 7, with only a slight delay time occurring from stage to stage. If, however, extremely short clock cycles are specified and the circuit modules with which the individual components, in particular the conversion unit 10, are implemented, cause a delay which is somewhat too great in comparison to this, intermediate storage within the conversion unit 10, if appropriate also before and / or after the conversion unit 10, are provided so as to carry out a first part of the operations in a first clock cycle and a second part in a second clock cycle. 5, however, the drawing of a buffer unit (in particular a register) to be inserted in this way has been dispensed with, since in the normal case such buffering will not be necessary, but rather the computing operations and the format conversions can take place in one and the same clock cycle.

The present conversion unit 10 also contains, as an integral hardware-related component, a rounding unit 15, which consists of individual logic modules and an adder, as will be explained in more detail below; furthermore, such a called "saturation function" integrated to prevent a change of sign in the event of a number overflow or underflow (overflow, underflow), cf. also the following explanations in connection with FIGS. 6 and 7.

In the example according to FIG. 5, the accumulator 12 has a width of 80 bits (cf. bit positions No. 0-79 in FIG. 5A), and a conversion into a number with a width of 32 bits is to take place in the conversion unit 10 , which corresponds to the width of a data word in the data memory 3. For this purpose, the format register 11 also contains a value of 40 in the SRC field (see FIG. 4) and a value of 16 in the DST field, which means that the 80 bit number from the accumulator 12 (the SRC -Number, i.e. the source number) has its decimal point to the right of bit no.40, whereas the 32-bit target number (DST number) should have its decimal point to the right of bit no.16 after the adaptation or conversion process.

At the beginning of the number format adaptation or conversion, the 80 bit number is expanded on both sides with the help of an expansion unit 16, namely on the right side, the LSB (least significant bit) side by 32 bits, that is, by as many bits as the target word DST, and these newly added 32 bits are all set to "0". On the other left side, the MSB side (MSB-Most Significant Bit), there are also 32 Bits corresponding to the bit width of the target word are added for expansion, the value of these bits being selected in accordance with the value of the sign bit which is taken over from the accumulator 12, that is to say the bit at the position “79”. This process is also referred to as a "sign extend" (cf. also the bit field SIGN (SRC) of the expansion unit 16 in FIG. 5A. A total of 32 + 80 + 32 = 144 bits, thus, of the bit No. 0 to bit No. 143, the bits at positions 32-111 form the original number at the output 12a of the accumulator 12.

Then the decimal point of this number, which has been extended to a total of 144 bits, must be adjusted in such a way that the decimal point is exactly at the required point with regard to the target number comes to be at the output 10a of the conversion unit 10. It is assumed that bit no. 0 in the number of sources, that is to say at the output 12a of the accumulator 12, as a bit with a value of 2 ° is always to the left of the decimal point, so that this bit is present at the position “40” in the number of sources , where it should be in the target number (output 10a of the conversion unit 10) at the point "16". There must therefore be a "shift" by (40-16 =) 24 bits to the right (as shown in FIG. 5A). This shift is accomplished with the aid of the shift unit 17 ("SHIFT"), the oblique representation of its Exit 17a this shifting process to the right (by 24 digits) is schematically illustrated. At its control input 17b, the displacement unit 17, which can be formed, for example, by a multiplexer control block, receives the corresponding control information for this displacement from a control unit 17 'that calculates the displacement quantity. This control unit 17 'calculates the shift amount from the values of the format preset register 11, which are at its output 11a and are supplied to the control unit 17'. The calculated shift amount results from the difference between the decimal point positions of the source format (SRC field in register 11) and the target format (DST field in register 11; see FIG. 4). Specifically, the control unit 17 'can thus consist of a subtractor, which forms the difference between the two contents of the fields SRC and DST of the register 11, and it can also be integrated directly into the displacement unit 17 as a control stage.

5, specifically FIG. 5A, the bit chain thus obtained is illustrated schematically by a block 18, it being illustrated by dashed, oblique lines that the number originally from the accumulator 12 is now increased by a corresponding number ( namely shifted to the right by 24 bits). With this shift, the bit positions released by the shift must be filled in with the correct sign, i.e. bits with the value of the sign bit of the source number (bit no. 79 in the accumulator 12) are used for filling.

Should be different from that shown in Fig. 5 a shift to are required on the left (in order to provide a larger number of decimal places), the bit positions that become free on the right are filled with "0" bits.

After this shift, the decimal point is already in the right place, corresponding to that in the target number, and the target number can now be selected as a partial field from the total word - i.e. can be taken from the bit chain 18. In the present case, the accuracy for the target number results from its placement with 32 bits. The fields of the overall word are not changed, but only interpreted in the format of the target number. This can also be referred to as a "mask change", and this operation is illustrated by the arrow 18a in FIG. 5. The result of this is illustrated in FIG. 5 (more precisely: FIG. 5B) with the subfield unit 19, it being evident that the actual number field 19DST (DST - destination number) is now 32 bits wide, 80 bits to the left of which are contained in a sign field 19SIGN. On the right-hand side are the bits for the "0" to "31" positions contain digits to be cut away (decimal places), whereby simply cutting away corresponds to rounding off, on the other hand rounding up under certain conditions, as explained in more detail below, with the help of rounding unit 15. When the bits for the target number (output 19a) are removed, this can be exceeded If the number of sources was positive, an undershoot is only possible if the source number was negative.

A logic unit 20 is provided in order to recognize a possible overshoot or undershoot ("overflow" or "underflow") of the number range, which, via a connection 19b from the output of the subfield unit 19, contains all 80 sign bits of the sign field 19SIGN and the sign bit of the target word in the target word field 19DST (bit at the point "31", indicated in the drawing with DST (32)). In the case of a valid number in the subfield unit 19, all sign bits are the same, either all equal to "0" or all equal to "1" With the help of an OR gate 21, it is now recognized whether all of the bit positions of the Sign field have the value "0", and with the help of an AND gate 22, it is recognized whether all bit positions of the sign field have the value "1". The outputs of these gates 21, 22 are connected to inputs of a test block 23 which determines whether the output signal (output 21a) of the OR gate 21 is not equal to "0" or the output signal 22a of the AND gate 22 is not equal Is "1". When the output signal 21a is not equal to "0" or the output signal 22a is not equal to "1", the test block 23 only has to determine whether there is an overshoot or an undershoot, and this determination is made with the aid of the sign bit of the source number, as it is contained in the accumulator 12, cf. also the connection 12s to the test block 23 in FIG. 5. If this sign bit (bit no. "79") has the value "0", there is an overflow or an overflow and the output 23o of the test block 23 a - provisional - overflow signal OFL activated. However, if the sign bit has the value "1", there is an underflow and an underflow signal UFL is activated at the output 23u of the test block 23. This is also the status signal already mentioned in the description of FIG. 3 UFL at the output 10b of the conversion unit 10.

The evaluation result of the test block 23 is also delivered via a connection 23a to a saturation unit 24, which is 33 bits wide, i.e. one bit more than the width of the target number, in order to repeat a possible overflow after a - to be described - rounding -To be able to recognize addition.

The saturation unit 24 sets the number supplied at 19a at its output 24a to the respective maximum end value in accordance with the test evaluation by test block 23 (output 23a relating to the UFL / OFL state). In more detail, this is the largest positive number in the event of an overflow (OFL), ie in this case all bits with the exception of the sign bits (bits nos. 31 and 32) are set to "1", whereas the sign bits at positions 31 and 32 are set to "0". In the event of a shortfall (UFL), the “largest” negative number (ie the negative number with the largest absolute amount) becomes output 24a This means that all bits in this output number are set to the value "0", with the exception of the two sign bits No. 31 and No. 32, which are set to the value "1". As already mentioned, a corresponding undershoot signal UFL or overflow signal OFL is additionally emitted at the outputs 10b and 10c.

When the low-order bits are cut off (in the subfield unit 19 to the right of the target word field 19DST, that is to say the bits at positions No. 0-31), a systematic error arises, with repeated execution of the operations described (for example if results are obtained in the course of filter implementations) accumulate) these errors add up unfavorably and may result in a total malfunction of certain algorithms. To counteract this, the already mentioned rounding unit 15 is provided, which is to reduce the systematic errors generated to 0 on average. In practice, IEEE rounding can be used, for example (see, for example, IEEE Standard for Binary Floating-Point Arithmetic IEEE 754-1985). In this rounding, rounding up is only carried out if at least one "1" bit in addition to a "1" bit at point No. 31 occurs somewhere in the decimal places (here bit positions No. 0-31) (it a single such additional "1" bit is sufficient, or if only bit No. 31 has the value 1, and if the LSB bit in the target word field 19DST also has the value "1". Such rounding-up means that, with the aid of an adder 25, a “1” (generally: the smallest positive value) is added to the number obtained at the output of the saturation unit 24. A logic unit 26 with an OR gate 27 and an AND gate 28 recognizes whether such a rounding (exactly rounding up) is actually to be carried out by sending the least significant bit (LSB bit) from the target word field 19DST (see connection 19c) and the cut bits (see connection 19d) to the OR gate 27 whose output 27a, as well as bit no. 31 of the cut low-order bits (see output 19e), is applied to the AND gate 28. The aforementioned IEEE rounding sees a rounding up, that is to say the addition of a “1” in the adder 25, then before (output "1" of AND gate 28, connection 28a) if any bit 19d or 19c is set to 1 and at the same time bit 19e (Bit no. 31 of subfield unit 19) also has the value 1.

However, such a rounding up also only takes place if no shortfall (signal UFL) has been determined by the test block 23, i.e. the adder 25 is also connected to the output 23u of the test block 23 with an input. If such an undershoot has not been determined and rounding is performed, the adder 25 adds the smallest possible positive number to the result in the output 24a of the saturation unit 24.

Since such a rounding up can again lead to an overflow (OFL), a further saturation unit 29 is connected to the output 25a of the adder 25, and this saturation unit 29 limits the output result in the same way as previously described with the saturation unit 24 (i.e. Target word) to the highest possible numerical value. This highest possible numerical value is output at the output 29a and stored in a register 30. If there is no overflow, the number obtained from the adder 25 is written directly into the register 30. In the event of an overflow, a corresponding OFL signal is output at the output 29b of the saturation unit 29, and this OFL signal is combined with the OFL signal at the output 23o of the test block 23 according to an OR function, see the OR gate 31 in FIG 5B, so that even in the event of an overflow, a corresponding OFL signal is obtained at the output 10c of the conversion unit 10.

From the above it can be seen that in the event that the number is not exceeded or undershot when returning to the subfield (see subfield unit 19), the units 24, 25 and 29 remain without function and the output number 19a of the subfield unit 19 goes directly to the register 30 ( as output storage means) and is stored there.

This completes the number format conversion and any rounding, and the end result, ie the target number DST, with the desired bit width (corresponding to the bit width of the target number field 10DST of the subfield unit 19) can now, as explained above with reference in particular to FIGS. 1 and 3 , as result Y again in general data storage 3 be written. The status signals UFL and OFL, however, are loaded into the status register 14 (see FIG. 3).

6 and 7, the so-called 2's complement representation of the binary numbers will now be briefly explained as an example, since this 2's complement representation was used as the basis for the operations according to FIG. 5. 6 shows 4-bit binary numbers provided with a sign bit S in a table, the value range in this example ranging from -8 to +7. The positive numbers are shown at P, the negative numbers at N. As can be seen, if the sign bit S has the value "0", the number is positive (the number 0 should also be added to the positive numbers); it is the sign bit S, on the other hand, "1", the number is a negative number N. When adding or subtracting, it can now happen that the number range limits are exceeded or undershot, cf. arrows 40 and 41 in FIG. 6. For example, if a positive number is added to a positive number (see arrow 40), the range P of the positive numbers can be exceeded (“overflow”), so that a negative number “arises” "because the bit word" Olli "(for the number +7) in the binary number representation shown is followed by the number" 1000 ", which is, however, already the largest negative number (-8). Similarly, if a negative number is added to a negative number (in terms of amount) (see arrow 41 in FIG. 6), a positive number can arise (namely with a "0" at the position of the sign bit S), so that an underflow or an undershoot of the value range results.

In Fig. 7 also signed (again in the 1st column of the bits) 4-bit binary numbers with integer parts I (I integer) and two decimal places F (F fraction) are illustrated, the range of values of which Binary numbers range from -2 to +1.75. Based on the IEEE rounding mentioned above with reference to FIG. 5, the numbers +0.75, +1.5 and +1.75 would be rounded up to +1, +2 and +2 if the decimal places were cut away become; however, no rounding up would be performed at the number +0.5. In this IEEE round, the number 0.5 is rounded down, 0.51 is already rounded up, likewise the number 1.5 is rounded up, but not the number 2.5, but again the number 3.5 etc.

8 and 9 in the form of simplified bit representations shown in lines (1) to (8) (with bit widths significantly smaller than in FIG. 5) are examples with format conversion and rounding, once with an overflow (FIG. 8) and once with a shortfall (Fig. 9).

Specifically, the 1st line in FIG. 8 shows an 8-bit source number SRC, which contains an integer 4-bit portion and 4-bit decimal places. The leftmost bit for the integer parts is the sign bit S. The target number DST shown in the 8th line, on the other hand, consists of 6 bits, the first three bits representing the integer parts including the sign bit and the further three bits the decimal places represent. The value of the source number SRC is +7.9375, which corresponds to the largest value that can be represented here.

According to line (2), an expansion is made to the left of the sign bit S, with the same number (namely six) of bits (here “0” bits) being used as the number of bits of the target number DST "Bits (ie six" 0 "bits) are appended to the right of the source number SRC.

For the shift now required, the difference between the number of decimal places of the source number SRC and that of the target number DST is to be calculated (which is accomplished with the control unit 17 according to FIG. 5), and this difference is "1" in the example of FIG. 8. , ie the bit chain is shifted to the right by one position, see line (3) in FIG. 8, the value of the sign bit is padded on the left-hand side, ie specifically a “0” bit is added here. Then, according to line (4) in FIG. 8, a new mask is placed over this chain, now with only six digits, corresponding to the number of bits of the target number DST. This mask is recognizable in FIG. 8 by a shorter block (compared to lines (1) to (3)). As can be seen, the 6-bit number in the fourth line of FIG. 8 thereby becomes negative (“1” bit on the leftmost one Job) . The nine bits to the left of it (including the sign bit of the target number) are now checked for equality, and since they are not all the same, an underflow / overflow condition is determined, cf. the logic unit 20 in FIG. 5. In order to determine exactly whether there is an overflow or an underflow, the sign bit of the source number SRC is used; in the present case, this sign bit has the value “0”, so that an overflow (OFL) is determined. If the sign bit of the source number SRC had the value “1”, an underflow would be determined. With the help of the saturation unit 24 (FIG. 5), the target word DST now receives the highest positive value, as can be seen from the fifth line in FIG. 8, this value now being +3.875. The rounding unit 15 (see FIG. 5) recognizes the need for rounding up at R in FIG. 8, the rounding unit 15 using the seven right-most bits for this. Accordingly, the target number DST is incremented by the value 0.125 (the smallest representable value with three bits), this addition value being shown in the 6th line of FIG. 8, whereas the highest positive value obtained from the saturation unit 24 is shown in the 5th line.

This addition of the numbers results in a negative number again, cf. the 6th line in FIG. 8, which is recognized by the second saturation unit 29 (see FIG. 5). The target number is therefore set again to the greatest positive value, which is shown in the 7th line of FIG. 8, and the number obtained in this way is passed on to the register 30 (see FIG. 5) as the final target number DST, as in FIG the 8th line of FIG. 8 is illustrated. At the same time, a corresponding overflow signal OFL is also output to the status register 14 (see FIG. 3).

In the example in FIG. 9, the source number SRC is again an 8 bit number with a sign bit S and four bit decimal places, the source number SRC shown having the largest negative value (in terms of amount), namely -4,000. The target number should again have six bit positions, and according to this number of bits, the sign bits are expanded with six “1” bits on the left-hand side, according to the second line of FIG the bits on the right-hand side are filled with "0". Then, again - see the 3rd line of FIG. 9 - the chain is shifted by one position to the right, with a "1" bit again on the left-hand side is inserted. When changing the mask, according to the 4th line in FIG. 9, in order to reduce the number of bits to six bits, according to the number of bits of the target number DST, it can be seen that the number has now taken a positive value (the left one Bit, the sign bit has the value "0"), and further the overflow / underflow check also determines that the nine bits on the left are not the same. Therefore, since this is recognized as an underflow, the Number set to the largest negative value, see the 5th line in Fig. 9. (The check for overflow or underflow (OFL / UFL) shows in this example that there is an underflow or an underflow because the sign bit S the source number SRC has the value "1".)

In the event of an underflow, however, the adder 25 is not able to add any rounding result to the target number, i.e. the number remains the same at the output of the adder 25, cf. the 6th line in FIG. 9. The further saturation unit 29 now recognizes no overflow or underflow (7th line in FIG. 9) and forwards the numerical value unchanged to the following register 30, cf. the 8th line in Fig. 9.

The configuration described in particular with reference to FIG. 5 can in practice preferably be implemented in combinatorial logic (in particular with AND and OR gates as well as with multiplexer chains for shifting etc.) without storing elements (registers) being provided in between , In this way it is achieved that in the same clock cycle in which the arithmetic operations are carried out, the format adjustments and any rounding operations can also take place. If very short cycle times are to be realized, memory elements (registers) can also be provided between individual units, as already mentioned.

IEEE rounding was explained above in connection with rounding as an example. Of course, other types of curves are also conceivable within the scope of the invention, such as commercial rounding, simply cutting away the back digits and other well-known types of rounding. It is only important here that the corresponding logic is implemented in terms of hardware, instead of providing programming for the arithmetic logic unit 4.

Claims

Claims:

1. Digital signal processing device with input storage means (3; 5), with an arithmetic unit (4) connected to it, which defines a data path (9) and contains at least one arithmetic unit (6) and a control input (2a) for specifying Has arithmetic operations, and with output storage means (8), the data path (9) between the arithmetic unit (6; 7) and the output storage means (8) containing a number format conversion unit (10) with a shifting unit (17) , characterized in that the number format conversion unit (10) is assigned a number format specification unit (11) and a related control unit (17 ') calculating shift operations required on the basis of the number format specification, formatting operations being automatically carried out from input and output format Information is calculated and corresponding commands are applied to the displacement unit (17).

2. Digital signal processing device according to claim 1, characterized in that the control unit (17 ') is formed by a subtractor.

3. Digital signal processing device according to claim 1 or 2, characterized in that the control unit (17 ') is integrated in the displacement unit (17).

4. Digital signal processing device according to one of claims 1 to 3, characterized in that the number format specification unit (11) is designed in the form of a register.

5. Digital signal processing device according to one of claims 1 to 4, characterized in that the number format conversion unit (10) has a width of an input number (SRC) expanding unit (16), the displacement unit (16) connected to this extension unit (16) ) shifts the bits of the extended input number by a predetermined amount.

6. Digital signal processing device according to one of the Claims 1 to 5, characterized in that a subfield unit (19) is connected to the displacement unit (17).

7. Digital signal processing device according to claim 6, characterized in that the subfield unit (19) has a sign field (19SIGN) to which a logic unit (20) is connected, which detects whether the sign field (19SIGN) only "0" (zeros) or contains only "1" (ones), or whether there are different sign bit positions, the state "only zeros" corresponding to an overflow (OFL) and the state "only ones" corresponding to an undershoot (UFL).

8. Digital signal processing device according to claim 7, characterized in that the logic unit (20) is an OR gate

(21) for recognizing the state "only zeros" and an AND gate

(22) to recognize the state "only ones".

9. Digital signal processing device according to claim 7 or 8, characterized in that a saturation unit (24) is connected to the logic unit (20) and to the sub-field unit (19), which is emitted by the sub-field unit (19) in the event of an overflow (OFL) Number sets to the largest positive number and, if the value is undershot (UFL), to the largest negative number.

10. Digital signal processing device according to one of claims 7 to 9, characterized in that the number format conversion unit (10) is combined with a rounding unit (15) which contains an adder (25) via a logic unit (26) to the subfield unit (19) is connected.

11. A digital signal processing device according to claim 10 and claim 9, characterized in that a further saturation unit (29) is connected to the rounding unit (15) and to the saturation unit (24), which results in the number of results being the largest in the event of an overflow occurring on a rounding sets a positive number and at the same time emits an overflow signal (OFL).